D. Reisis

National and Kapodistrian University of Athens, Department of Electronics, Computers, Telecommunications & Automation, Faculty of Physics, Faculty Member

Followers

Following

Co-authors

Public Views

Interests

Uploads

Papers by D. Reisis

Neural Network-Based Solar Irradiance Forecast for Edge Computing Devices

Information

Aiming at effectively improving photovoltaic (PV) park operation and the stability of the electri... more Aiming at effectively improving photovoltaic (PV) park operation and the stability of the electricity grid, the current paper addresses the design and development of a novel system achieving the short-term irradiance forecasting for the PV park area, which is the key factor for controlling the variations in the PV power production. First, it introduces the Xception long short-term memory (XceptionLSTM) cell tailored for recurrent neural networks (RNN). Second, it presents the novel irradiance forecasting model that consists of a sequence-to-sequence image regression NNs in the form of a spatio-temporal encoder–decoder including Xception layers in the spatial encoder, the novel XceptionLSTM in the temporal encoder and decoder and a multilayer perceptron in the spatial decoder. The proposed model achieves a forecast skill of 16.57% for a horizon of 5 min when compared to the persistence model. Moreover, the proposed model is designed for execution on edge computing devices and the rea...

Download

Parity Based In-Place FFT Architecture for Continuous Flow Applications

2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2018

The current paper introduces a continuous flow radix-2 FFT architecture with a conflict free para... more The current paper introduces a continuous flow radix-2 FFT architecture with a conflict free parallel access in-place technique. The parity based technique stores the FFT input elements into two memory banks, and keeps each element at its input address through the entire FFT process. Moreover, it results in improved address generation and control circuits compared to hitherto published results. The FPGA implementation and the comparison with FPGA available cores show the advantages of the resulting architecture.

GUI for the communication agent of the “Nephele” Data Center

2017 South Eastern European Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM), 2017

The evolving technology and the demand for high throughput links has led to the design of Data Ce... more The evolving technology and the demand for high throughput links has led to the design of Data Centers with optical switching. Among the latest wave of design proposals is the Nephele Data Center architecture consisting of optical data planes, optical Points of Delivery (PoD) switches and Top of Rack (ToR) switches communicating with 10 Gbps links to the PoDs and the servers. Based on a Software Defined Network it uses OpenFlow protocol and an Agent realizing the communication among the protocol and the data plane. The current paper presents the Agent's graphical user interface (GUI). The Agent's GUI is able to configure the Agent, create commands, perform step operations and monitor the results and the status. It benefits the Agent's design as well as the entire data center's organization as a testing and validation tool.

Physics Dept

This paper presents a generic shaper/flow controller, which can efficiently schedule traffic stre... more This paper presents a generic shaper/flow controller, which can efficiently schedule traffic streams in networks using statistical multiplexing. The component can operate for a large number of traffic streams of various profiles and Quality of Service. The controller uses a calendar for scheduling and has a low cost VLSI implementation. Performance measures in this work for 70-90% communication link utilization show the jitter (system impact) under various operating conditions.

Download

Real Time Demonstration of an End-to-End Optical Datacenter Network with Dynamic Bandwidth Allocation

2018 European Conference on Optical Communication (ECOC), 2018

We demonstrate combined operation of a scalable optical data-plane architecture with an SDN overl... more

Download

Parallel Memory Accessing for FFT Architectures

Journal of Signal Processing Systems, 2018

The current paper introduces an efficient technique for parallel data addressing in FFT architect... more The current paper introduces an efficient technique for parallel data addressing in FFT architectures performing in-place computations. The novel addressing organization provides parallel load and store of the data involved in radix-r butterfly computations and leads to an efficient architecture when r is a power of 2. The addressing scheme is based on a permutation of the FFT data, which leads to the improvement of the address generating circuit and the butterfly processor control. Moreover, the proposed technique is suitable for mixed radix applications, especially for radixes that are powers of 2 and straightforward continuous flow implementation. The paper presents the technique and the resulting FFT architecture and shows the advantages of the architecture compared to hitherto published results. The implementations on a Xilinx FPGA Virtex-7 VC707 of the in-place radix-8 FFT architectures with input sizes 64 and 512 complex points validate the results.

Download

Acceleration techniques and evaluation on multi-core CPU, GPU and FPGA for image processing and super-resolution

Journal of Real-Time Image Processing, 2016

Super-Resolution (SR) techniques constitute a key element in image applications, which need highr... more Super-Resolution (SR) techniques constitute a key element in image applications, which need highresolution reconstruction while in the worst case only a single low-resolution observation is available. SR techniques involve computationally demanding processes and thus researchers are currently focusing on SR performance acceleration. Aiming at improving the SR performance, the current paper builds up on the characteristics of the L-SEABI Super-Resolution (SR) method to introduce parallelization techniques for GPUs and FPGAs. The proposed techniques accelerate GPU reconstruction of Ultra-High Definition content, by achieving three (3x) times faster than the real-time performance on mid-range and previous generation devices and at least nine times (9x) faster than the real-time performance on high-end GPUs. The FPGA design leads to a scalable architecture performing four (4x) times faster than the real-time on low-end Xilinx Virtex 5 devices and sixty-nine times (69x) faster than the real-time on the Virtex 2000t. Moreover, we confirm the benefits of the proposed acceleration techniques by employing them on a different category of image-processing algorithms: on window-based Disparity functions, for which the proposed GPU technique shows an improvement over the CPU performance ranging from 14 times (14x) to 64 times (64x) while the proposed FPGA architecture provides 29x acceleration.

Download

Efficient and Expandable Interpolating FIR Filter Design and Implementation

This work describes the design and implementation of an interpolating digital filter that is plac... more This work describes the design and implementation of an interpolating digital filter that is placed at the input of a Digital to Analog Converter (DAC) to relax the characteristics of the analog filter following the DAC. The work presents techniques of parallelizing the filter computations leading to the design and implementation of efficient architectures with respect to throughput and VLSI area. Furthermore, this design involves techniques which facilitate expansion with respect to the filter length (taps) and internal and external accuracy as well as adaptivity to various sampling rates.

Download

Image computations on meshes with multiple broadcast

IEEE Transactions on Pattern Analysis and Machine Intelligence, 1989

Abstract The authors consider a mesh-connected processor array with broadcast, in which the proce... more

Address Generation Techniques for Conflict Free Parallel Memory Accessing in FFT Architectures

2006 13th IEEE International Conference on Electronics, Circuits and Systems, 2006

Speeding up FFT computations is critical for today&amp;amp;#39;s real time systems targeting ... more Speeding up FFT computations is critical for today&amp;amp;#39;s real time systems targeting signal processing and telecommunication applications. Aiming at the performance improvement and the efficiency of FFT architectures this paper presents an address generation technique which enables a b-radix processing stage to access in parallel b memory banks without conflicts and leads to increasing the speedup of the algorithm by

Conflict free, parallel memory access for radix-2 FFT processors

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012), 2012

ABSTRACT The current paper presents a parallel addressing technique for radix-2 FFT architectures... more ABSTRACT The current paper presents a parallel addressing technique for radix-2 FFT architectures. The novel technique bases on a permutation to accomplish parallel load and store of the FFT data even with a single memory bank, which stores two FFT elements at each address. Furthermore, the proposed addressing scheme minimizes the requirements for the address generation and processor control circuits. An example FPGA implementation shows the simplicity of the architecture and validates the results.

Exact Max-Log MAP Soft-Output Sphere Decoding via Approximate Schnorr–Euchner Enumeration

IEEE Transactions on Vehicular Technology, 2015

ABSTRACT The complexity gains of sphere decoders (SDs) with Schnorr–Euchner enumeration and nonco... more ABSTRACT The complexity gains of sphere decoders (SDs) with Schnorr–Euchner enumeration and nonconstant amplitude constellations are limited by the required node ordering. Aiming at improving the implementation efficiency of SD without compromising optimality, this paper proposes a novel tree traversal for soft-output SDs providing the exact max-log MAP decoder performance. It consists of a predefined visiting order that approximates the exact Schnorr–Euchner enumeration (SEE) and a modified pruning metric that preserves the exact max-log MAP despite the approximate ordering. The proposed approach significantly improves both the computational complexity and the implementation cost of exact soft-output SDs compared with previous techniques. In particular, simulations show gains of 30%–56% in the required calculations for a 4 4 multiple-input multiple-output system with 16-quadrature amplitude modulation (QAM), and field-programmable gate array (FPGA) implementations show an average power reduction of 34%–50%.

Parallel Image Processing On Enhanced Arrays

On a mesh-connected computer of size N**1**/**2 multiplied by N**1**/**2, O(N**1**/**2) time is n... more On a mesh-connected computer of size N**1**/**2 multiplied by N**1**/**2, O(N**1**/**2) time is needed to solve several image-processing problems that involve global data transfer owing to global communication overhead. An enhanced array with efficient global communication feature for image-processing applications is considered. Several geometric properties of digitized pictures can be determined in O(N**1**/**6) time, while those related to multiple objects can be computed in O(N**1**/**4) time. For several problems on digitized images, the array with multiple buses is comparable in performance to a pyramid of corresponding size.

Efficient Systolic Array Mapping of FIR Filters Used in PAM-QAM Modulators

ABSTRACT This paper presents efficient techniques for mapping FIR filter computation circuits for... more ABSTRACT This paper presents efficient techniques for mapping FIR filter computation circuits for PAM and QAM modulators onto systolic arrays. The exploitation of the inherent symmetry of these problem instances and the use of Look-Up Tables (L.U.T.) in conjunction with the use of systolic architectures, increases the performance while keeping the VLSI area minimal. Exploiting parallelism and pipelining enhances the throughput and results in linear expandability of the FIR filter with respect to the bit accuracy and to the stage count.

Conflict-Free Parallel Memory Accessing Techniques for FFT Architectures

IEEE Transactions on Circuits and Systems I: Regular Papers, 2000

ABSTRACT Speeding up fast Fourier transform (FFT) computations is critical for today&#39;s re... more ABSTRACT Speeding up fast Fourier transform (FFT) computations is critical for today&#39;s real-time systems targeting signal processing and telecommunication applications. Aiming at the performance improvement and the efficiency of FFT architectures, this paper presents an address generation technique which enables a radix- b processor to access in parallel b memory banks without conflicts during each stage&#39;s computations. Using kb memory banks at each stage leads to increasing the speedup of the algorithm by a factor of kb . The address generation can be realized in each radix- b stage by the use of lookup tables of size O ( kb 2) bits. The proposed technique is cost efficient and leads to the design of FFT architectures of high speedup and high sustained throughput.

Image computations on reconfigurable VLSI arrays

Proceedings CVPR '88: The Computer Society Conference on Computer Vision and Pattern Recognition, 1988

Abstract This paper considers image computations on a mesh with recon-figurable bus (reconfigurab... more

Optimizing PCS network performance by utilising a multilink B-ISDN routing protocol

Proceedings of 1994 3rd IEEE International Conference on Universal Personal Communications, 1994

ABSTRACT This paper discusses a multilink routing protocol implementation significantly improving... more ABSTRACT This paper discusses a multilink routing protocol implementation significantly improving the PCS&#39;s fixed network performance and reducing corresponding network delay. This implementation is based on the string mode approach for improving on the load balancing and resource sharing in ATM networks. This work presents a complete implementation of the main protocol component, namely the router, whose task is to distribute cells evenly among the communication links. It is also argued that the string mode protocol can be efficiently utilized in order to increase the effectiveness of the fixed PCS network

VLSI arrays with reconfigurable buses

Lecture Notes in Computer Science, 1988

In this paper we consider mesh connected computers with reconfigurable buses. The architecture co... more In this paper we consider mesh connected computers with reconfigurable buses. The architecture consists of N 1/2 × N 1/2 PEs, with PEs in each row and column connected to a shared bus. The buses are partitionable using N 1/2-1 switches embedded on each bus. This provides efficient global communication patterns for a variety of partitions of the mesh connected computer. We illustrate the suitability of the architecture by demonstrating efficient parallel solution to several graph problems and low level vision problems which have low interprocessor communication requirements. Compared to known reconfigurable architectures and other parallel architectures such as mesh of trees and pyramids, the proposed organization has low area requirement and simple switch control while providing fast parallel solutions to several problems.

Image Computations on Reconfigurable Mesh

Computer Vision and Pattern Recognition, 1988

Meshes with reconfigurable buses

IEEE Transactions on Computers - TC, 1993

ABSTRACT An abstract is not available.

D. Reisis

Uploads

Papers by D. Reisis

Log In