Design of Fault Tolerance Parallel FFT's Using Xilinx 14.5v

2014

In this paper, a convolution code namely low density parity check is proposed and implemented in VLSI architectures (FPGA).In general a digital communication system suffers from errors due to noise, distortion and interference during the data transmission and commonly uses various algorithms to correct the errors. A third generation wireless communication system uses convolutional codes for transmission of voice and control signals. whereas in existing system the convolution code namely the turbo codes are used with the belief propagation algorithm that plays a vital role in VLSI implementation which have low bit error rate and low signal to noise ratio but high decoding error rate and high decoding complexity. The tanner graphs are used to construct longer codes from smaller ones to perform row and column operations. The Low Density Parity Check uses the message passing algorithm that acts as the superior performer and iterative decoding technique for low decoding complexity and high decoding rate that helps in parallel processing for updating large number of messages and transferring between check nodes and bit nodes .The optimised method of Moore's Law is implemented. This attracts the public attention as a code for fourth generation in communication system and provides high security. The simulation results indicate that our proposed scheme can reduce the power dissipation by overcoming the soft error process which is the incorrect switching or an impractical activity of a memory cell and provides an optimal circuit in order to enhance the VLSI Technologies.

Aerospace Conference, 2007

IEEE Transactions on Circuits and Systems II: Express Briefs, 2012

Advanced electronic circuits suffer errors caused by multiple sources. For example, radiation can induce transient errors, and manufacturing variations can cause some devices to sporadically suffer errors. Fault tolerance is therefore an important issue in advanced electronic circuits. Digital filters are commonly used in many applications, and therefore, their protection against errors has been widely studied. However, infiniteimpulse-response (IIR) filters have received little attention as most of the existing works focus on finite-impulse-response filters. In this brief, a technique to implement concurrent error detection in IIR filters with programmable coefficients is proposed and evaluated. The protection effectiveness is assessed through fault injection experiments that show that it can efficiently detect errors. The cost is estimated using the synthesis results for a 45-nm library. The results show that the area overhead is much lower than that of a duplicated system that can also detect errors. Index Terms-Concurrent error detection (CED), filter, infinite impulse response (IIR). I. INTRODUCTION A DVANCED ELECTRONIC circuits face multiple reliability challenges that can cause errors. For example, manufacturing variations [1] or radiation [2] can cause transient errors on some circuit nodes. Fault tolerance techniques to protect against those errors can be implemented at different levels. These range from the manufacturing process of the circuits to system-level techniques that add redundancy to detect and correct errors [3]. Among the latter group of techniques, modular redundancy that replicates the design is commonly used. When two replicas are used, errors can be detected by checking for differences; with three replicas, single errors can also be corrected by voting among the replicas. Modular redundancy can be easily implemented but requires a large overhead. This has motivated research on algorithm-based fault tolerance (ABFT) that exploits the properties of the circuit to detect and correct errors [4]. ABFT has been applied to many signal processing circuits. For example, it was applied to fast Fourier transforms in [5] and to convolutions in [6]. Other works like [7] have exploited the use of different precisions to reduce the overhead of modular redundancy, while in [8], fault tolerance was considered at the word level.

A scheme based on error correction coding has been recently proposed to protect parallel FIR filters. In this scheme, each filter is treated as a bit, and redundant filters that act as parity check bits are introduced to detect and correct errors. This reduces the protection overhead and makes the Number of redundant filters independent of the number of parallel filters. The proposed scheme is first described and then illustrated with two case studies. Finally, both the effectiveness in protecting against errors and the cost are evaluated for a field-programmable gate array implementation. This Proposed System Implemented using Verilog HDL and Simulated by Modelsim 6.4 c and Synthesized by Xilinx tool. The proposed system implemented in FPGA Spartan 3 XC3S 200 TQ-144.

This paper presents a study on the various digital filers for the fault tolerance and error correction in DSP circuits. In signal processing, a filter is a device or process that removes some unwanted components or features from a signal. The study puts a light on protection of the digital filters used widely i.e. fault-tolerant implementations based on the use of residue number systems or arithmetic codes have been proposed. The use of reduced precision replication or word-level protection has been also studied. Another option to perform error correction is to use two different filter implementations in parallel. All those techniques focus on the protection of a single filter.

Electronics

Field programmable gate arrays (FPGAs) are increasingly used in industry (e.g., biomedical, space, and automotive industries). FPGAs are subjected to single, as well as multiple event upsets (SEUs and MEUs), due to the continuous shrinking of transistor dimensions. These upsets inevitably decrease system lifetime. Fault-tolerant techniques are often used to mitigate these problems. In this research, penta and hexa modular redundancy, as well as dynamic partial reconfiguration (DPR), are used to increase system reliability. We show, depending on the relative rates of the SEUs and MEUs, that penta modular redundancy has a higher reliability than hexa modular redundancy, which is a counter-intuitive result in some cases since increasing redundancy is expected to increase reliability. Focusing on penta modular redundancy, an error detection and recovery mechanism (voter) is designed. This mechanism uses the internal configuration access port (ICAP) and its associated controller, as well...

2015

Field Programmable Gate Arrays (FPGAs) are more prone to be affected by transient faults in presence of radiation and other environmental hazards compared to Application Specific Integrated Circuits (ASICs). Hence, error mitigation and recovery techniques are absolutely necessary to protect the FPGA hardware from soft errors arising due to such transient faults. In this paper, a new efficient multi-bit error correcting method for FPGAs is proposed using adaptive cross parity check (ACPC) code. ACPC is easy to implement and the needed decoding circuit is also simple. In the proposed scheme total configuration memory is partitioned into two parts. One part will contain ACPC hardware, which is static and assumed to be unaffected by any kind of errors. Other portion will store the binary file for logic, which is to be protected from transient error and is assumed to be dynamically reconfigurable (Partial reconfigurable area). Binary file from the secondary memory passes through ACPC har...

2016

The paper describes about fault tolerant parallel filters based on Hamming Code for multiple bit error correction. This filter is used on the system when is important for reliability. The ECC using in every output bit of the filter and it’s correct the error in output. For multiple bit error correction to use the hamming code as a ECC in this paper. This novel scheme of ECC allows more efficient protection. Another name of this technique is soft error correction. From analysis of the architecture the efficiency of the error correction is more compare to existing system and the leakage power is 0.113W.

2006

Transient errors in computer systems can cause abnormal behavior and degrade system reliability, data integrity and availability. This is especially true in a space environment where transient errors are a major cause of concern. Fault avoidance techniques such as radiation hardening and shielding have been the major approaches to obtaining the required reliability. Recently, unhardened Commercial Off-The-Shelf (COTS) components have been investigated for space applications because of their higher density, faster clock rate, lower power consumption and lower price. Since COTS components are not radiation hardened, and it is desirable to avoid shielding, Software-Implemented Hardware Fault Tolerance (SIHFT) has been proposed to increase the data integrity and availability of COTS systems. This dissertation presents three new SIHFT techniques for error detection: Control Flow Checking by Software Signatures (CFCSS), Error Detection by Duplicated Instructions (EDDI), and Error Detection by Diverse Data and Duplicated Instructions (ED 4 I). Previously studied software techniques are either inadequate or require assistance from special hardware, but CFCSS, EDDI and ED 4 I are pure software methods. In CFCSS, signatures are embedded into the program during compilation and compared with run-time signatures during execution. In EDDI, instructions are duplicated at compile-time, and scheduled by exploiting Instruction-Level Parallelism (ILP) to reduce performance overhead. CFCSS and EDDI detect transient errors but not permanent faults. However, in ED 4 I, a program is compiled to a new program with diverse data so that it can detect a permanent fault. Our fault injection experiment simulating bit flips in memory shows that, for the designs simulated, EDDI provides over 98% fault coverage without any extra hardware. Because of instruction duplication, code size overhead is approximately 100%, but by exploiting ILP, we reduce the performance overhead down to 61% on average. For control flow checking experiment simulating branching faults, CFCSS provides 97% fault coverage. In addition, when we duplicate programs or instructions, we can use ED 4 I to enhance data integrity in the system. Furthermore, for space experiments, we have implemented EDDI and CFCSS in sort and FFT programs running in the ARGOS satellite. During a 136 day period, our techniques have detected a total of 198 out of 203 errors, and show 98% error detection coverage. While traditional error detection and fault tolerance techniques require special dedicated hardware, our SIHFT techniques use time redundancy for error detection and significantly improve data integrity without requiring special hardware.

The uses of FFTs are unavoidable in communication systems. As most of the information may be analog in this world and as transmission of information in digital form is more acceptable and efficient, FFTs plays an important role in present communication scenario. For a reliable communication the information that we transmit should be reached at the destination as such. But due to many factors the information that we transmits get altered. One of the main problems in communication system is soft error. Even though soft error doesn't make any physical damage to the communication system it is dangerous. It has the ability to alter the values stored in the system. It may alter the transmitted message. A lot of techniques are available to detect the soft error and correct it. Those include TMR, ECC, parity SOS, and parity-SOS-ECC. All these assume that there can only be a single error in the circuit. The proposed system known as reduced precision redundancy considers Instead of using two full precision FFTs it uses two half precision FFTs as redundant FFTs. It limits the error, reduces area and power consumption.