A digital error-averaging technique for pipelined A/D conversion

InTech Ultra Wideband Systems book, 2011

Integration, 2011

This paper presents a digital background calibration technique that measures and cancels offset, linear and nonlinear errors in each stage of a pipelined analog to digital converter (ADC) using a single algorithm. A simple two-step subranging ADC architecture is used as an extra ADC in order to extract the data points of the stage-under-calibration and perform correction process without imposing any changes on the main ADC architecture which is the main trend of the current work. Contrary to the conventional calibration methods that use high resolution reference ADCs, averaging and chopping concepts are used in this work to allow the resolution of the extra ADC to be lower than that of the main ADC.

A capacitor error-averaging technique is applied to perform an accurate multiply-by-two (X 2) function required in high-resolution pipelined analog-to-digital (A/D) converters. Errors resulting from capaci-tor mismatch and switch feedthrough are corrected in the analog domain without using digital calibration and/or trimming. A differential pipelined A/D converter that achieves a throughput rate of 1 Msample/s with 12 bits of linearity has been made and evaluated. A prototype pipelined A/D converter implemented using a double-poly 1.75-pm CMOS process consumes 400 mW with a 5-V single supply and occupies 14 mrd including all digital logic and output buffers.

2006 NORCHIP, 2006

A quickly locking tracking digital phase-locked loop (PLL) has been implemented to train the digital error correction circuitry of an A/D converter. The PLL and the error correction engine are implemented on an FPGA, and the circuitry includes several speed-up techniques and adaptation loops. The training circuit has been tested using a prototype 14-bit, 300 kS/s pipeline A/D converter driven by a clean sinusoid. The correction for the four msb stages was trained, resulting in an average improvement of 10 dB in SFDR, and reducing the remaining INL below the noise floor of the system. II. PLL BASED ADAPTIVE CORRECTION A simplified block diagram of the proposed adaptation circuit is shown in Fig. 1. The A/D converter is driven by a non-distorted sinusoid. The digital PLL tracks the quantized signal and generates an ideal digital reference signal, the amplitude and offset of which is adapted to match those of the input signal. A real-time error signal is calculated as a difference of the input signal and the reference signal, and using this error signal, it is quite easy to adapt the actual error correction of the A/D converter.

The devices used in current integrated circuits technology are mostly non-linear. This issue makes the matching between such devices almost impossible. In pipelined analog-to-digital converters (ADC), this implies that achieving to the accuracies more than those allowable by the error sources is impossible without using an effective calibration technique. It can be shown by simulations that the number of the front-end stages that should be calibrated is larger than the difference of the maximum achievable bits without calibration and the required bits of the converter. In this paper, a discussion is provided on the modeling of the important error sources of the pipelined ADC in gain of the stages, and then, a novel approach is proposed for the non-linear calibration of the ADC stages.

IEEE Journal of Solid-state Circuits, 2008

A technique to rapidly correct for both DAC and gain errors in the multibit first stage of an 11-bit pipelined ADC is presented. Using a dual-ADC based approach the digital background scheme is validated with a proof-of-concept prototype fabricated in a 1.8 V 0.18 m CMOS process, where the calibration scheme improves the peak INL of the 45 MS/s ADC from 6.4 LSB to 1.1 LSB after calibration. The SNDR/SFDR is improved from 46.9 dB/48.9 dB to 60.1 dB/70 dB after calibration. Calibration is achieved in approximately 10 4 clock cycles.

IEICE Electronics Express, 2010

This paper presents a digital background calibration technique to correct the capacitors mismatch, gain error and gain nonlinearities of 1.5 bit/stage pipelined ADCs. The calibration technique uses a modified structure for the ADC stages, the skip-fill method and LMS algorithm and does not require any accurate calibration signal and any added analog circuitry; just some digital circuits are needed to fill the skipped samples and realize the LMS algorithm. Circuit level simulation results in a 90-nm CMOS technology are provided for a 12bit 80-MS/s pipelined ADC to verify the effectiveness of the proposed calibration technique.

This paper, presents a novel low power current mode 9 bit pipelined a/d converter. The a/d converter structure is composed of three 2.5 bit stages and one 3 bit stage operating in current mode and a final comparator which converts the analog current signal into a digital voltage signal. All the building blocks of the converter were designed in CMOS AMS 0.35 um technology, simulated, and then a prototype converter was manufactured and measured to verify the proposed concept. The performances of the converter are compared to performances of known voltage-mode switched-capacitance and current-mode switched-current converter structures. Low power consumption and small chip area are the advantages of the proposed converter.

2010

An analog-to-digital converter (ADC) is a link between the analog and digital domains and plays a vital role in modern mixed signal processing systems. There are several architectures, for example flash ADCs, pipeline ADCs, sigma delta ADCs, successive approximation (SAR) ADCs and time interleaved ADCs. Among the various architectures, the pipeline ADC offers a favorable trade-off between speed, power consumption, resolution, and design effort. The commonly used applications of pipeline ADCs include high quality video systems, radio base stations, Ethernet, cable modems and high performance digital communication systems. Unfortunately, static errors like comparators offset errors, capacitors mismatch errors and gain errors degrade the performance of the pipeline ADC. Hence, there is need for accuracy enhancement techniques. The conventional way to overcome these mentioned errors is to calibrate the pipeline ADC after fabrication, the socalled post fabrication calibration techniques. But environmental changes like temperature and device aging necessitates the recalibration after regular intervals of time, resulting in a loss of time and money. A lot of effort can be saved if the digital outputs of the pipeline ADC can be used for the estimation and correction of these errors, further classified as foreground and background techniques. In this thesis work, an algorithm is proposed that can estimate 10% inter stage gain errors in pipeline ADC without any need for a special calibration signal. The efficiency of the proposed algorithm is investigated on an 8-bit pipeline ADC architecture. The first seven stages are implemented using the 1.5-bit/stage architecture while the last stage is a one-bit flash ADC. The ADC and error correction algorithm is simulated in Matlab and the signal to noise and distortion ratio (SNDR) is calculated to evaluate its efficiency.

IEEE Journal of Solid-State Circuits, 2000

A pipeline analog-to-digital converter architecture can reduce the differential nonlinearity (DNL) with a swapping capacitor technique without involving special calibration techniques. An implementation of the overrange stages in the analog pipeline suitable for high-speed applications is proposed. A 14-bit 5-MSample/s converter has been fabricated in a double-poly 0.5-µm CMOS process. The 3.3 × 3.3 mm 2 chip dissipates 320 mW from a single 5-V supply and achieves a signal-to-noise ratio of 79 dB, a dynamic range of 82 dB, and a DNL below 0.4 LSB.