Khalid Javeed

High‐speed parallel reconfigurable Fp multipliers for elliptic curve cryptography applications

International Journal of Circuit Theory and Applications, 2022

Elliptic curve cryptography (ECC) protocols due to higher security strength per bit have been wid... more Elliptic curve cryptography (ECC) protocols due to higher security strength per bit have been widely accepted and deployed. Finite field multiplication is the most computational intensive operation in data security protocols developed using ECC. This paper presents two high‐speed parallel re‐configurable finite field multipliers: PIMD‐2 and PIMD‐3 over prime field (Fp) for ECC applications. The proposed designs are based on the new novel optimized interleaved multiplication algorithms. This work first identifies room of parallelism by investigating independent operations in the standard interleaved multiplication method and subsequently proposes high‐speed hardware architectures that allow the parallel execution of these operations. Due to the introduced modifications, the critical path delays and clock cycle consumption in the PIMD‐2 and PIMD‐3 designs are reduced simultaneously. The proposed Fp multipliers are synthesized using Xilinx ISE Design Suite and implemented on Virtex‐5 a...

Institutionen För Systemteknik Digital Gain Error Correction Technique for 8-bit Pipeline Adc Digital Gain Error Correction Technique for 8-bit Pipeline Adc Co-supervisor Examinator: Examiner

An analog-to-digital converter (ADC) is a link between the analog and digital domains and plays a... more An analog-to-digital converter (ADC) is a link between the analog and digital domains and plays a vital role in modern mixed signal processing systems. There are several architectures, for example flash ADCs, pipeline ADCs, sigma delta ADCs, successive approximation (SAR) ADCs and time interleaved ADCs. Among the various architectures, the pipeline ADC offers a favorable trade-off between speed, power consumption, resolution, and design effort. The commonly used applications of pipeline ADCs include high quality video systems, radio base stations, Ethernet, cable modems and high performance digital communication systems. Unfortunately, static errors like comparators offset errors, capacitors mismatch errors and gain errors degrade the performance of the pipeline ADC. Hence, there is need for accuracy enhancement techniques. The conventional way to overcome these mentioned errors is to calibrate the pipeline ADC after fabrication, the socalled post fabrication calibration techniques. But environmental changes like temperature and device aging necessitates the recalibration after regular intervals of time, resulting in a loss of time and money. A lot of effort can be saved if the digital outputs of the pipeline ADC can be used for the estimation and correction of these errors, further classified as foreground and background techniques. In this thesis work, an algorithm is proposed that can estimate 10% inter stage gain errors in pipeline ADC without any need for a special calibration signal. The efficiency of the proposed algorithm is investigated on an 8-bit pipeline ADC architecture. The first seven stages are implemented using the 1.5-bit/stage architecture while the last stage is a one-bit flash ADC. The ADC and error correction algorithm is simulated in Matlab and the signal to noise and distortion ratio (SNDR) is calculated to evaluate its efficiency.

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A high speed redundant-signed-digit based montgomery modular multiplier

2018 International Conference on Engineering and Emerging Technologies (ICEET), 2018

Modular multiplication is the most crucial operation in the cryptographic systems that are based ... more Modular multiplication is the most crucial operation in the cryptographic systems that are based on the public key cryptography. In this work, a new architecture for radix-2 Montgomery Modular Multiplier (MMM) is proposed. The proposed design utilizes Redundant-Signed-Digit (RSD) arithmetic to optimize the critical path at the arithmetic level. The incorporation of the RSD arithmetic has significantly reduced the critical path of the proposed MMM. However, RSD arithmetic increases the area of the MMM. In order to compensate the increase in area, a new architecture for MMM is proposed that is based on a single adder instead of two as required in conventional MMM. The proposed design is implemented on Virtex-6 platform for various field sizes. It can perform a 256 bit modular multiplication in 0.73us and utilizes 3.8k Look-Up Tables. The proposed design achieves higher speed than other counterparts and occupies competitive area.

A high-speed RSD-based flexible ECC processor for arbitrary curves over general prime field

International Journal of Circuit Theory and Applications, 2018

This workpresents a novel high-speed redundant-signed-digit (RSD)-based elliptic curve cryptograp... more This workpresents a novel high-speed redundant-signed-digit (RSD)-based elliptic curve cryptographic (ECC) processor for arbitrary curves over a general prime field. The proposed ECC processor works for any value of the prime number and curve parameters. It is based on a new high speed Montgomery multiplier architecture which uses different parallel computation techniques at both circuit level and architectural level. At the circuit level, RSD and carry save techniques are adopted while pre-computation logic is incorporated at the architectural level. As a result of these optimization strategies, the proposed Montgomery multiplier offers a significant reduction in computation time over the state-of-the-art. At the system level, to further enhance the overall performance of the proposed ECC processor, Montgomery ladder algorithm with (X,Y)-only common Z coordinate (co-Z) arithmetic is adopted. The proposed ECC processor is synthesized and implemented on different Xilinx Virtex (V) FPGA families for field sizes of 256 to 521 bits. On V-6 platform, it computes a single 256 to 521 bits scalar point multiplication operation in 0.65 to 2.6 ms which is up to 9 times speed-up over the state-of-the-art. KEYWORDS elliptic curve cryptography, field programmable gate array (FPGA), high-speed, redundant-signeddigit (RSD), scalar point multiplication 1 | INTRODUCTION Elliptic curve cryptograpy (ECC)-based 1,2 cryptographic systems have emerged as an attractive alternate to the traditional RSA 3 scheme due to smaller key lengths. 4 In all ECC-based cryptographic systems, scalar point multiplication (SPM) is the main and the most computationally intensive operation. Scalar point multiplication is the multiplication of a suitably chosen scalar to a point of an elliptic curve (EC). Mathematically, it is denoted as L = mQ, where m is a scalar (integer), and Q is an EC point while output L is another point on the same curve. Points Q and L are public while scalar m is private. The strength of an EC depends on the computational hardness in calculating the private value m for given public values Q and L. The SPM is computed by a series of point additions (PA) and point doubling (PD) operations. These PA and PD operations in turn use addition, subtraction, multiplication, and inversion/division over a finite field and their efficient implementation can significantly speed-up the EC SPM operation. Scalar point multiplication is usually computed using hardware accelerators due to its computational complexity. Several hardware architectures have been developed to reduce the computational cost of SPM operation targetting prime field, 5-20 binary field, 21-25 or dual field. 26-28 Among these 5-18,21-23 are FPGA-based designs while in previous

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A high-speed RSD-based flexible ECC processor for arbitrary curves over general prime field

International Journal of Circuit Theory and Applications, 2018

This workpresents a novel high-speed redundant-signed-digit (RSD)-based elliptic curve cryptograp... more This workpresents a novel high-speed redundant-signed-digit (RSD)-based elliptic curve cryptographic (ECC) processor for arbitrary curves over a general prime field. The proposed ECC processor works for any value of the prime number and curve parameters. It is based on a new high speed Montgomery multiplier architecture which uses different parallel computation techniques at both circuit level and architectural level. At the circuit level, RSD and carry save techniques are adopted while pre-computation logic is incorporated at the architectural level. As a result of these optimization strategies, the proposed Montgomery multiplier offers a significant reduction in computation time over the state-of-the-art. At the system level, to further enhance the overall performance of the proposed ECC processor, Montgomery ladder algorithm with (X,Y)-only common Z coordinate (co-Z) arithmetic is adopted. The proposed ECC processor is synthesized and implemented on different Xilinx Virtex (V) FPGA families for field sizes of 256 to 521 bits. On V-6 platform, it computes a single 256 to 521 bits scalar point multiplication operation in 0.65 to 2.6 ms which is up to 9 times speed-up over the state-of-the-art. KEYWORDS elliptic curve cryptography, field programmable gate array (FPGA), high-speed, redundant-signeddigit (RSD), scalar point multiplication 1 | INTRODUCTION Elliptic curve cryptograpy (ECC)-based 1,2 cryptographic systems have emerged as an attractive alternate to the traditional RSA 3 scheme due to smaller key lengths. 4 In all ECC-based cryptographic systems, scalar point multiplication (SPM) is the main and the most computationally intensive operation. Scalar point multiplication is the multiplication of a suitably chosen scalar to a point of an elliptic curve (EC). Mathematically, it is denoted as L = mQ, where m is a scalar (integer), and Q is an EC point while output L is another point on the same curve. Points Q and L are public while scalar m is private. The strength of an EC depends on the computational hardness in calculating the private value m for given public values Q and L. The SPM is computed by a series of point additions (PA) and point doubling (PD) operations. These PA and PD operations in turn use addition, subtraction, multiplication, and inversion/division over a finite field and their efficient implementation can significantly speed-up the EC SPM operation. Scalar point multiplication is usually computed using hardware accelerators due to its computational complexity. Several hardware architectures have been developed to reduce the computational cost of SPM operation targetting prime field, 5-20 binary field, 21-25 or dual field. 26-28 Among these 5-18,21-23 are FPGA-based designs while in previous

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Radix-4 and radix-8 booth encoded interleaved modular multipliers over general Fp

2014 24th International Conference on Field Programmable Logic and Applications (FPL), 2014

ABSTRACT This paper presents radix-4 and radix-8 Booth encoded modular multipliers over general F... more ABSTRACT This paper presents radix-4 and radix-8 Booth encoded modular multipliers over general Fp based on inter-leaved multiplication algorithm. An existing bit serial interleaved multiplication algorithm is modified using radix-4, radix-8 and Booth recoding techniques. The modified radix-4 and radix-8 versions of interleaved multiplication result in 50% and 75% reduction in required number of clock cycles for one modular multiplication over the corresponding bit serial interleaved multipliers, while maintaining a competitive critical path delay. The proposed architectures are implemented in Verilog HDL and synthesized by targeting virtex-6 FPGA platform. Due to an efficient utilization of optimized addition chains available in FPGAs and exploiting the parallelism among operations, the proposed radix-4 and radix-8 multipliers compute one 256 × 256 bit modular multiplication in 1.49μs and 0.93μs respectively, which are 35% and 94% improvement over the corresponding bit serial version. Further, this work also presents a thorough comparison on basis of area, throughput, and area × time per bit value. Which shows that these designs are efficiently optimized for area × time per bit value with a high throughput rate. Thus, these designs are suitable to construct most of the elliptic curve and pairing based cryptographic processors.

Serial and parallel interleaved modular multipliers on FPGA platform

2015 25th International Conference on Field Programmable Logic and Applications (FPL), 2015

Modular multiplication is a core operation in all public key based cryptosystems. The performance... more Modular multiplication is a core operation in all public key based cryptosystems. The performance of these cryptosystems can be enhanced substantially by incorporating an optimized modular multiplier. This paper presents serial and parallel radix-4 modular multipliers based on interleaved multiplication algorithm and Montgomery power laddering technique. A serial radix-4 interleaved modular multiplier provides 50% reduction in the required clock cycles. In addition to the reduction in clock cycles, a parallel modular multiplier maintains a critical path delay comparable to the bit serial interleaved multipliers. The proposed designs are implemented in Verilog HDL and synthesized targeting virtex-6 FPGA platform using Xilinx ISE 14.2 Design suite. The serial radix-4 multiplier computes a 256-bit modular multiplication in 1.3μs, occupies 3.9K LUTs, and runs at 96 MHz. The parallel radix-4 multiplier takes 0.77μs, occupies 5.3K LUTs, and runs at 166 MHz. The results show that the parallel radix-4 modular multiplier provides 62% and 49% speed-up over the corresponding bit serial and bit parallel versions, respectively. Thus, these designs are suitable to accelerate modular multiplication in many cryptographic processors.

A Network Traffic Classification Model Based on Metric Learning

Computers, Materials & Continua, 2020

Efficient hardware architecture for scalar multiplications on elliptic curves over prime field

Suitable cryptographic protocols are required to meet the growing demands for data security in ma... more Suitable cryptographic protocols are required to meet the growing demands for data security in many different systems, ranging from large servers to small hand-held devices. Many constraints such as computation time, silicon area, power consumption, and security level must be considered by the designers of hardware accelerators of the cryptogrpahic protocols. Elliptic curve cryptography (ECC) proposed by Koblitz and Miller, has been widely accepted. It is now considered as one of the best Public-Key Cryptography (PKC) algorithms and provides higher security strength per bit than RSA, with considerably smaller key sizes. For example, a 256-bit ECC can provide the same security strength as 3072-bit RSA. Due to its much smaller key sizes, ECC based crypto-systems are better in terms of bandwidth utilization, power consumption, and implementation cost as compared to the traditional RSA based crypto-systems. However, PKC algorithms, especially ECC are relatively expensive as compared to ...

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Speed and Area Optimized Parallel Higher-Radix Modular Multipliers

IACR Cryptol. ePrint Arch., 2016

Modular multiplication is the fundamental and compute-intense operation in many Public-Key crypto... more Modular multiplication is the fundamental and compute-intense operation in many Public-Key crypto-systems. This paper presents two modular multipliers with their efficient architectures based on Booth encoding, higher-radix, and Montgomery powering ladder approaches. Montgomery powering ladder technique enables concurrent execution of main operations in the proposed designs, while higher-radix techniques have been adopted to reduce an iteration count which formally dictates a cycle count. It is also shown that by an adopting Booth encoding logic in the designs helps to reduce their area cost with a slight degradation in the maximum achievable frequencies. The proposed designs are implemented in Verilog HDL and synthesized targeting virtex-6 FPGA platform using Xilinx ISE 14.2 Design suite. The radix-4 multiplier computes a 256-bit modular multiplication in 0.93 μs, occupies 1.6K slices, at 137.87 MHz in a cycle count of dn/2e+2, whereas the radix-8 multiplier completes the operation...

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Exploring the Potential of Transient Receptor Potential: Troubleshooting Troublesome Calcium Thoroughfares in Biomedicine

Transient Receptor Potential-Canonical (TRPC) channels are the border guards residing in the supr... more Transient Receptor Potential-Canonical (TRPC) channels are the border guards residing in the supra-molecular assembly of plasma membrane. TRPCs represent a family of channels that have dual functions of store-operated and second messenger-operated channels in a diversity of cell types. Any disruption in the spatio-temporal organization drastically influences the calcium homeostasis. This review summarizes current interpretations on the infrastructure and characteristic divalent ions regulation in molecular anomalies. A specific targeting of these channels will enable us to get a step closer to personalized medicines.

Design and Performance Comparison of Modular Multipliers Implemented on FPGA Platform

by Khalid Javeed and Xiaojun Wang

Cloud Computing and Security

Modular multiplier is the most critical component in many data security protocols based on public... more Modular multiplier is the most critical component in many data security protocols based on public key cryptography (PKC). To provide data security in many real time applications, a high performance modular multiplier is of utmost importance. Two techniques mostly used for high speed modular multiplication are Montgomery Modular Multiplication (MMM) and Interleaved Modular Multiplication (IMM). This paper presents radix-2 hardware implementation of the MMM and IMM methods with detailed performance analysis. The designs are implemented in Verilog HDL and synthesized targeting Xilinx Virtex-6 FPGA platform. Synthesized results indicate that the radix-2 MMM design is better in terms of computation time, FPGA slice area and throughput as compared to the radix-2 IMM design.

Redundant-Signed-Digit-Based High Speed Elliptic Curve Cryptographic Processor

Journal of Circuits, Systems and Computers

In this paper, a high speed elliptic curve cryptographic (ECC) processor for National Institute o... more In this paper, a high speed elliptic curve cryptographic (ECC) processor for National Institute of Standards and Technology (NIST) recommended prime [Formula: see text] is proposed. The modular arithmetic components in the proposed ECC processor are highly optimized at both architectural level and circuit level. Redundant-signed-digit (RSD) arithmetic is adopted in the modular arithmetic components to avoid lengthy carry propagation delay. A high speed modular multiplier is designed based on an efficient segmentation and pipelining strategy. The clock cycle count is reduced as result of the segmentation, whereas operating frequency and throughput are significantly increased due to the pipelining. An optimized pipelined architecture for modular division is also presented which is suitable for the design of ECC processor using projective coordinates. The Joye’s double and add (DAA) algorithm based on [Formula: see text]-only common [Formula: see text] (co-[Formula: see text]) coordina...

Secure Video Streaming with Lightweight Cipher PRESENT in an SDN Testbed

Computers, Materials & Continua

The combination of traditional processors and Field Programmable Gate Arrays (FPGA) is shaping th... more The combination of traditional processors and Field Programmable Gate Arrays (FPGA) is shaping the future networking platform for intensive computation in resource-constrained networks and devices. These networks present two key challenges of security and resource limitations. Lightweight ciphers are suitable to provide data security in such constrained environments. Implementing the lightweight PRESENT encryption algorithm in a reconfigurable platform (FPGAs) can offer secure communication service and flexibility. This paper presents hardware acceleration of security primitives in SDN using NETFPGA-10G. We implement an efficient design of the PRESENT algorithm for faster, smaller and lower power consumption hardware circuit using Verilog. We evaluate the performance of the hardware and software implementations of PRESENT. Experimental results prove that the proposed hardware design is a viable option for use in resource constrained devices in future networks and their applications.

High-speed FPGA implementation of full-word Montgomery multiplier for ECC applications

Microprocessors and Microsystems

Abstract Modular multiplication is the most crucial operation in many public-key crypto-systems, ... more Abstract Modular multiplication is the most crucial operation in many public-key crypto-systems, which can be accomplished by integer multiplication followed by a reduction scheme. The reduction scheme involves a division operation that is costly in terms of computation time and resource consumption both on hardware and software platforms. Montgomery modular multiplication is widely used to eliminate the costly division operation. This work presents an efficient implementation of full-word Montgomery modular multiplication. This incorporates the more efficient Karatsuba algorithm where the complexity of multiplication is reduced form O ( n 2 ) to O ( n 1.58 ) . The Karatsuba algorithm recommends to split the operands into smaller chunks. Two methods of operand splitting are exploited: (1) Four Parts (FP) splitting and (2) Deep Four Parts (DFP) splitting. These methods are then used in the design of Integer Multiplier (IM) and Montgomery Multiplier (MM). The design is synthesized using Xilinx ISE 14.1 Design Suite for Virtex-5, Virtex-6 and Virtex-7. Compared with the traditional implementations, the proposed scheme outperforms all other designs in terms of throughput and area-delay product. Moreover, the proposed scheme utilizes the least hardware resources in the known literature. The proposed MM design is able to compute modular multiplication for the Elliptic Curve Cryptography (ECC) field sizes of 192–512 bits.

FPGA Based High Speed SPA Resistant Elliptic Curve Scalar Multiplier Architecture

International Journal of Reconfigurable Computing

The higher computational complexity of an elliptic curve scalar point multiplication operation li... more The higher computational complexity of an elliptic curve scalar point multiplication operation limits its implementation on general purpose processors. Dedicated hardware architectures are essential to reduce the computational time, which results in a substantial increase in the performance of associated cryptographic protocols. This paper presents a unified architecture to compute modular addition, subtraction, and multiplication operations over a finite field of large prime characteristicGF(p). Subsequently, dual instances of the unified architecture are utilized in the design of high speed elliptic curve scalar multiplier architecture. The proposed architecture is synthesized and implemented on several different Xilinx FPGA platforms for different field sizes. The proposed design computes a 192-bit elliptic curve scalar multiplication in 2.3 ms on Virtex-4 FPGA platform. It is 34%faster and requires 40%fewer clock cycles for elliptic curve scalar multiplication and consumes consi...

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THE EFFECT OF 9 E INSTRUCTIONAL LEARNING AND TEACHING MODEL ON STUDENTS' IMPROVEMENT CRITICAL THINKING SKILLS

Past studies have been conducted to examine the achievement of students and performance in develo... more Past studies have been conducted to examine the achievement of students and performance in developed countries, but only rare researches were addressed in developing countries like Pakistan. Pakistan is still lacking behind to conduct the research in the improvement Critical Thinking Skills (CTS) practices. In this study to determine interpretation and analysis based on 9 E learning and teaching model in statistics learning 12 th grade students of CTS improvement. This research studies a descriptive by its nature. A total number of 110 student's 12 th grade (60 boys and 50 girls) statistics students were selected sample through stratified random sampling, and two colleges were selected with randomly sampling approach. The data was collected through questionnaire contained 5-point Likert scale. The two questionnaires (9 E learning and teaching instructional model and CTS interpretation, analysis) were developed for this study. 9 E learning and teaching instructional practices were an independent variable, whereas CTS namely interpretation, and analysis was a dependent variable. There were total 36 questions of 9 E learning and teaching instructional model and total 25 questions of interpretation and analysis of CTS. The students were taught with 9 E learning and teaching model based. The result of the study showed that there was strong and positive effect of 9 E learning and teaching instructional practices on students CTS of the interpretation and analysis at 12 th grade students. The finding of the study has revealed that there were nine processes involved in the development of CTS among students during the interpretation and analysis. The study would be helpful for teachers and students, improvement in teaching and implementing new learning approaches with instructional learning and teaching. However, there are limited research studies carryout with the 9 E learning and teaching model with CTS of the statistics students. This study will be able to respond the interpretation and analysis, whether the effectiveness relationship 9 E learning and teaching model and CTS of statistics in Pakistan.

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High performance hardware support for elliptic curve cryptography over general prime field

Microprocessors and Microsystems, 2016

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