A novel digital calibration technique for pipelined ADCs

Microsystem Technologies, 2018

Design of high resolution ADCs in scaled CMOS technology is challenging due to increased component mismatch, comparator offset, and finite op-amp gain error. In this work, a commutated feedback capacitor switching calibration technique has been proposed to improve the ENOB and linearity of ADCs with multi-bit pipeline architecture. During normal operation of ADC, the fixed sampling capacitor is swapped in the feedback capacitor. We have distributed the sampling capacitor and swap the feedback capacitor with the sampling capacitor(s) in the MDAC of each pipeline stage ADC. The mismatches of different pipeline stages are concurrently corrected in the digital domain. Proposed technique requires digital calibration circuits and requires no extra calibration phase cycles. The prime objective of this work is to achieve high linearity and ENOB in pipeline architectures with low power consumption. Behavioral simulation of 16-bit 5Ms/s pipeline ADC in UMC 0.18 lm double poly triple metal processes with proposed calibration shows significant improvement in DNL with r = 0.25% capacitor mismatch with correct 16-bit digital output. The design is implemented using HSPICE simulation. The robustness of the proposed technique has been verified by process, temperature and voltage variation simulations and Monte Carlo analysis.

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

In this paper, a digital background auto-calibration method that computes mismatch between the elements of the interstage Multiplying-Digital-to-Analog Converter (MDAC) as commonly employed in pipelined Analog-to-Digital Converters (ADCs) and then applies a linearizing algorithm in the digital domain is described. The calibration does not interrupt the normal operation of the ADC and is performed periodically, thus inherently able to track changes in the operating conditions of the device, a major limitation of one-time calibration approaches. This scheme requires an extra MDAC element and a reference element. The MDAC mismatch is digitized by the succeeding stages of the pipeline and subsequently digitally extracted. The accuracy of the calibration algorithm depends on the number of clock periods used for each calibration session. Longer sessions lead to better accuracy with the trade-off being additional digital circuitry. System simulation results demonstrate validity of the approach.

Circuits and Systems I: …, 2011

The linearity of a high-resolution pipelined analogto-digital converter (ADC) is mainly limited by the capacitor mismatch and the finite operational amplifier (OPAMP) gain in the multiplying-digital-to-analog converter (MDAC). Therefore, high resolution pipelined ADCs usually require high-gain OPAMP and large capacitors, which causes large ADC power. In recent years, various nonlinear calibration techniques have been developed to compensate both linear and nonlinear error from MDCAs so that low-power MDACs with small capacitors and low-gain OPAMP can be used. Hence, the ADC power can be greatly reduced. This paper introduces a novel interpolationbased digital self-calibration architecture for pipelined ADC. Compared to previous techniques, the new architecture is free of adaptation. Hence, long convergence is not needed. The complexity of the digital processor is also considerably lower. The new architecture does not use backend ADC to measure MDACs. Hence, it is free of the accumulation of measurement error, which leads to more accurate calibration. A prototype ADC with the calibration architecture is fabricated in a 0.35m 3.3V CMOS process. The ADC samples at 20MS/s. The calibration improves the ADC DNL and INL from 1.47LSB and 7.85LSB to 0.2LSB and 0.27LSB. For a 590kHz sinusoidal signal, the calibration improves the ADC signal-to-noise-distortion ratio(SNDR) and spurious-free dynamic range (SFDR) from 41.3dB and 52.1dB to 72.5dB and 84.4dB respectively. The 11.8-ENOB 20MS/s ADC consumes 56.3mW power with 3.3V supply. The 0.78pJ/step figure-of-merit (FOM) is low for designs in 0.35um CMOS processes. At the Nyquist frequency, SNDR of the calibrated ADC drops 8dB due to the slow settling of the first pipeline stage.

2012

In this paper, a 10-bit 50-Msample/s pipelined ADC by using dynamic charge injection technique is presented. By the proposed scheme, the input voltage range is increased and power consumption is reduced. For the calibration of the output codes, a new method is presented which uses polynomial inverse function. By the use of the inverse function and simultaneously adjustment of both the weights of stages and coefficients of polynomials, linearity is achieved. The proposed ADC is designed and simulated in a 90-nm CMOS technology. Simulation results show that the ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 59 dB, a peak spurious-free dynamic range (SFDR) of 72.5 dB. The ADC's power consumption (without calibration circuitry) is 1 mW (without calibration circuitry)

IEEE Journal of Solid-state Circuits, 2008

A technique to rapidly correct for both DAC and gain errors in the multibit first stage of an 11-bit pipelined ADC is presented. Using a dual-ADC based approach the digital background scheme is validated with a proof-of-concept prototype fabricated in a 1.8 V 0.18 m CMOS process, where the calibration scheme improves the peak INL of the 45 MS/s ADC from 6.4 LSB to 1.1 LSB after calibration. The SNDR/SFDR is improved from 46.9 dB/48.9 dB to 60.1 dB/70 dB after calibration. Calibration is achieved in approximately 10 4 clock cycles.

Circuits Systems and Signal Processing, 2009

The paper presents a digital foreground calibration technique for pipeline analog-to-digital converters (ADCs). While the conventional calibration approach requires additional buffered voltage references, the proposed technique requires only a voltage reference, already available in the converter, thus allowing a significant circuit simplification and silicon area savings. Since the number of buffered voltage references in the conventional calibration algorithm increases exponentially with the resolution of the conversion stages to be calibrated, the proposed technique is suitable for high-resolution, high-speed pipeline ADCs.

2009 International Conference on Signal Acquisition and Processing, 2009

This paper describes a new Background calibration technique for pipeline analogto-digital converters (ADCs). The new scheme utilizes an existing digital foreground calibration algorithm and extends it to work in background. The goal is to digitally calibrate the pipeline ADCs in the background without stopping the input conversion. In this method one additional stage connected in parallel to the stage under calibration and one cyclic ADC are used to accommodate the calibration. The extra stage and the cyclic ADC are only used during the calibration process. Sources of error in pipeline architectures and effects of error on residue plot of 1-bit per stage are identified and discussed. The digital background calibration accounts for capacitor mismatch, comparator offset, charge injection and finite op-amp gain. By applying proposed calibration to a 12-bit resolution pipeline ADC, maximum INL improved from 14 to 0.6 LSB, and maximum DNL improved from 26 to 0.8 LSB.

This brief proposes a low power mixed-signal foreground calibration algorithm of a pipeline ADC, using a digitally controlled re-configurable switched capacitor multiplying DAC (MDAC) gain controller. The proposed calibration technique forces the front-end stage MDAC gain towards its ideal value to achieve the ideal ADC output linearity. In this paper, a feedback mechanism has been employed to nullify the effect of change in MDAC gain from its ideal value by sensing a digital backend unit response. The proposed technique has been verified in 0.18 um CMOS process using the cadence virtuoso tool by simulating an 11- bit pipeline ADC which contains a 1.5-bit nonideal pipeline stage followed by a 10-bit linear back-end ADC (BE-ADC). Simulation results demonstrate the recovery of the lost linearity of a 11 bit pipeline ADC post calibration.

IEEE Transactions on Instrumentation and Measurement, 2004

An efficient pipeline analog-to-digital converter (ADC) self-calibration implementation is presented. The technique uses a highly linear on-chip analog ramp generator, performs a simplified on-chip integral nonlinearity (INL) measurement, and extracts the compensation coefficients. Except for the ramp generator, the whole calibration is performed in the digital domain and is done at the nominal ADC speed (at-speed). The approach does not require any modification to the original analog section of the ADC. The INL measurement can be carried off-chip to simplify the production testing or to perform performance verification in the application environment. Simulation and measurement results show an INL improvement of more than 2 bits (from 2.1 LSB to 0.5 LSB).

IEEE Transactions on Circuits and Systems II: Express Briefs, 2015

This paper presents a digital background calibration technique that embraces comparator decision time to calibrate interstage gain errors and capacitor mismatches in pipelined ADCs. It does not modify the original analog signal path except for the addition of comparator decision time binary quantizer (DTQ) built by simple digital gates. The technique does not limit either the ADC input signal swing or bandwidth. Simulation results for a 12-bit pipelined ADC show that the proposed technique can improve SNDR and SFDR from 44 dB and 48 dB to 72 dB and 86 dB, respectively. The SNDR convergence time is less than 3 × 10 6 cycles.