The significant point is to design the function so that all calculation performs within one clock cycle. The basic operation of the aligned mantissa and normalized block is shifting. Every shifting need one clock cycle and it causes huge delay to align 32 bit operand. Hence, the advanced algorithm is applied to avoid having many delays on aligning stage. This is the third advantage of the mentioned adder. Table 2: Align stage specification Table 1: Compare stage specification Table 5: Floating point adder/subtractor specification minimum equivalent of gate count (6691 gate) resulted Fig. 7: The core layout on FPGA board
