Capacitive coupling noise in high-speed VLSI circuits

2001

Abstract Scaling the minimum feature size of VLSI circuits to sub-quarter micron and its clock frequency to 2 GHz has caused crosstalk noise to become a serious problem, that degrades the performance and reliability of high speed integrated circuits. This paper presents an efficient method for computing the capacitive crosstalk in sub-quarter micron VLSI circuits. In particular, we provide closed-form expressions for the peak amplitude, the pulse width, and the time-domain waveform of the crosstalk noise.

researchweb.watson.ibm.com

This paper presents a highly accurate yet efficient crosstalk noise model, the 2-model, and applies it to interconnect optimizations for noise reduction. Compared to previous crosstalk noise mod-els with similar complexity, our 2-model takes into consideration many key ...

Circuits and Systems, IEEE Transactions …, 1989

Abstmct-A noise analysis of switched-capacitor (SC) circuits is presented that exactly d e s c n i the time-averaged second-order statistics of the cyclostationary pocesses encountered in such systems. A unified framework allows to take account of broad band as well as of low frequency (such as flicker) noise soulces by basing the modeling for all noise types on the mathematical white noise model: broad-band noise is mudeled by white noise and low frequency noise by linearly filtered white noise, respectively. 'zbe noise signal decomposition used in our appropch is different from that of other authors and does lead to simple and straightforward computer implementations on various approximation levels. Based on our solution, existing SC circuit analyzers featuring different abstraction levels c m thus easily be extended with the noise analysis feature by using much of theii original routineS. As an example, an implementation of the noise analysis for the WATSCAD program is described.

1999

Abstract—As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of very large scale integrated (VLSI) systems. A metric for noise immunity is defined, and a static noise analysis methodology based on this noise-stability metric is introduced to demonstrate how noise can be analyzed systematically on a full-chip basis using simulationbased transistor-level analysis. We then describe Harmony, a two-level (macro and global) hierarchical implementation of static noise analysis. At the macro level, simplified interconnect models and timing assumptions guide efficient analysis. The global level involves a careful combination of static noise analysis, static timing analysis, and detailed interconnect macromodels based on reduced-order modeling techniques. We describe how the interconnect macromodels are practically employed to perform coupling analysis and how timing constraint...

2002

The corruption of signals due to capacitive and inductive coupling of interconnects has become a significant problem in the design of deep submicron circuits (DSM). Noise simulators, based on worstcase assumptions, are overly pessimistic. As a result, when they are used on industrial ICs with hundreds of thousands of nets, thousands of nets are reported as having potential noise violations. There is a need to prioritize the problem nets based on the likelihood of the noise and possibly even eliminate them from further consideration if the likelihood is negligable. In this paper, a probabilistic approach is described which allows for a quantitative means to prioritize nets based on the likelihood of the reported noise violation. We derive upper bounds on the probability that the total noise injected on a given victim net by a specific set of aggressors exceeds a threshold. This bound is then used to determine a lower bound on the expected number of clock cycles (ENC) before the first violation occurs on a given net. Nets can be prioritized based on the ENC. We demonstrate the utility of this approach through experiments carried out on a large industrial processor design using a state-ofthe-art industrial noise analysis tool. A significant and interesting * Work done while on sabbatical with Advanced Design Tools group at Motorola, Austin TX.

Circuits and Systems, 2014

Recent studies using BSIM3 models have suggested that noise depends on the transconductanceto-drain ratio () m D g I of a transistor. However, to the best of our knowledge, no experimental result demonstrating m D g I dependent noise previously observed in simulation is available in the literature. This paper examines the underlying principles that make it possible to analyze noise using m D g I based noise analysis. Qualitative discussion of normalized noise is presented along with experimental results from a 130 nm CMOS process. A close examination of the experimental results reveals that the device noise is width independent from 1 Hz to 10 kHz. Moreover, noise increases as m D g I is reduced. The experiment observation that noise is width independent makes it possible for circuit designers to generate normalized parameters that are used to study noise intuitively and accurately.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1997

The performance of high-speed electronic systems is limited by interconnect-related failure modes such as coupled noise. We propose new techniques for alleviating the problems caused by coupling between signal lines on integrated circuits. We show that models used by previous work on coupled noise-constrained layout synthesis do not allow the use of several important degrees of freedom. These degrees of freedom include the ability to utilize dynamic noise margins rather than static noise margins, the dependence of coupled noise on drive strength, and the possibility of using overlaps to reduce susceptibility to noise. We derive an expression for the coupled noise integral and a bound for the peak coupled noise voltage which shows order of magnitude improvements in both accuracy and fidelity compared to the charge sharing model used in previous work. We use the new bounds to guide a greedy channel router, which manipulates exact adjacency information at every stage, allowing it to introduce jogs or doglegs when necessary for coupled noise reduction. Experimental results indicate that our algorithm compares favorably to previous work. The coupled noise is significantly reduced on benchmark instances.

Nuclear Instruments and Methods in Physics Research …, 1996

Despite extensive literature on the analysis of noise in electronic circuits [1–7], it is sometimes difficult to generate an understanding at a useful fundamental level. The plethora of symbols used for a variable in different analysis can also make it very difficult to keep track of the ...

1999

Accurate noise analysis is currently of significant concern to highperformance designs, and the number of signals susceptible to noise effects will certainly increase in smaller process geometries. Our approach uses a combination of temporal and functional information to eliminate false transition combinations and thereby overcome insufficiencies in static noise analysis. A similar idea arises in timing analysis where functional and timing information is used to eliminate false paths. The goal of our work is to develop an algorithm, software tool, and noise analysis flow that provide an accurate and conservative approach to noise analysis. In particular, this paper proposes an approach to identifying a pair of vectors that exercises the maximum crosstalk noise.

2014 Ieee Acm International Conference on Computer Aided Design, 2014

Defects or traps in semiconductors and nano devices that randomly capture and emit charge carriers result in low-frequency noise, such as burst and 1/f noise, that are great concerns in the design of both analog and digital circuits. The capture and emission rates of these traps are functions of the time-varying voltages across the device, resulting in nonstationary noise characteristics. Modeling of low-frequency, nonstationary noise in circuit simulators is a longstanding open problem. It has been realized that the low frequency noise models in circuit simulators were the culprits that produced erroneous noise performance results for circuits under strongly time-varying bias conditions. In this paper, we first identify an almost perfect analogy between trap noise in nano devices and the so-called ion channel noise in biological nerve cells, and propose a new approach to modeling and analysis of low-frequency noise that is founded on this connection. We derive two fully nonstationary models for traps, a fine-grained Markov chain model based on recent previous work and a completely novel coarse-grained Langevin model based on similar models for ion channels in neurons. The nonstationary trap models we derive subsume and unify all of the work that has been done recently in the device modeling and circuit design literature on modeling nonstationary trap noise. We also describe joint noise analysis paradigms for a nonlinear circuit and a number of traps. We have implemented the proposed techniques in a Matlab ® based circuit simulator, by expanding the industry standard compact MOSFET model PSP to include a nonstationary description of oxide traps. We present results obtained by this extended model and the proposed simulation techniques for the low frequency noise characterization of a common source amplifier and the phase jitter of a ring oscillator.