Inter-process communication

Le but de cette recherche est de produire un "vade-mecum" de l'organisation en cycles a destination des equipes des ecoles primaires en Communaute francaise pour en indiquer les differentes modalites organisationnelles et pedagogiques et pour signaler les points forts de chacune . Pour construire un tel outil d'accompagnement et pour determiner ce qui, en matiere d'organisation en cycles, est possible, ce qui est souhaitable, a redouter, etc . , ce document se refere a trois sources : • les buts assignes a l’organisation en cycles dans les textes officiels regissant l'enseignement en Communaute francaise . C'est par rapport a ces buts qu'une modalite organisationnelle ou pedagogique pourra etre consideree comme interessante ou neutre, etc . • la litterature en sciences de l'education . Les resultats dont elle fait etat donnent de precieuses indications sur les effets de differents dispositifs didactiques, pedagogiques et organisationnels qui son...

MACH is an operating system kernel under development at Carnegie-Mellon University to support distributed and parallel computation. MACH is designed to support computing environments consisting of networks of uniprocessors and multiprocessors. This manual describes the interface to the MACH kernel in detail. The MACH system currently runs on a wide variety of uniprocessor and multiprocessor architectures.

Le but de notre recherche était de produire un vade mecum de l'organisation en cycles à destination des équipes des écoles primaires, en Communauté française, pour en indiquer les différentes modalités organisationnelles et pédagogiques et pour signaler les points forts de chacune et surtout les dérives et erreurs à éviter. Trois types de sources d'informations nous ont nourris pour construire un tel outil d'accompagnement, c'est-à-dire pour déterminer, en matière d'organisation en cycles, ce qui est possible, ce qui est souhaitable, ce qui est réellement utile, ce qui est, en revanche, à redouter, etc. • Nous avons examiné d'abord quels sont les buts assignés à l'organisation en cycles dans les textes officiels régissant l'enseignement en Communauté française. C'est par rapport à ces buts qu'une modalité organisationnelle ou pédagogique pourra être considérée comme intéressante ou neutre ou négative ou risquée, etc. • Nous avons fait appel, d'autre part, à la littérature en sciences de l'éducation. Les résultats dont elle fait état, issus à la fois de l'expérimentation et de l'expérience enseignante, donnent de précieuses indications sur les effets de différents dispositifs didactiques, pédagogiques et organisationnels qui sont impliqués par l'organisation en cycles. • Mais ces deux sources auraient été insuffisantes si elles n'avaient été accompagnées de l'examen du fonctionnement concret des différentes modalités d'organisation en cycles, telles qu'on peut les rencontrer sur le terrain. En effet, les choix opérés par les enseignants et les équipes doivent toujours tenir compte de nombreuses contraintes liées aux singularités de leur école. Aucun discours théorique ne peut intégrer exhaustivement cette multiplicité de facteurs. Il aurait donc été tout à fait imprudent de proposer des modalités pédagogiques qui n'auraient pas été éprouvées concrètement et que l'on n'aurait pas observées en fonctionnement réel. Mieux encore : dans un domaine si délicat, ce qui fonctionne bien, à un endroit et à un moment donnés, n'a pas toujours des effets aussi favorables dans d'autres circonstances. Il faut se garder des généralisations imprudentes ; nous n'avons donc avancé des propositions, des suggestions ou des mises en garde qu'en les référant aux situations concrètes qui les ont inspirées. L'outil d'accompagnement que nous avons proposé au terme de cette recherche repose sur une enquête de terrain et, plus précisément, sur une double enquête dont le premier volet, mené durant l'année 2001-2002, a, à la fois, préparé le second et comporté des résultats intéressants en eux-mêmes. La manière dont ces trois références s'articulent entre elles peut être décrite ainsi : a) L'étude des textes officiels : Nous sommes partis des termes dans lesquels les textes officiels commandent l'organisation en cycles, à la fois pour relever la manière dont elle est définie et pour cerner les intentions qui lui sont sous-jacentes. Nous avons examiné les textes récents, notamment les décrets du 14 mars 1995 (relatif à la promotion de l'école de la réussite dans l'enseignement fondamental) et du 24 juillet 1997 (définissant les missions prioritaires de l'enseignement fondamental et de l'enseignement secondaire). Mais nous avons essayé aussi d'éclairer le sens des dispositions les plus récentes en les resituant dans l'historique de la mise en place des cycles et en les confrontant à des textes réglementaires plus anciens. b) La première enquête : informations organisationnelles sur 108 écoles. À partir de l'étude des textes officiels, nous avons pu déterminer les modèles possibles d'organisation en cycles. Mais il fallait faire appel à l'enquête de terrain pour déterminer, parmi ces modèles théoriquement possibles, ceux qui sont effectivement mis en oeuvre dans les écoles. C'est ce que nous avons fait grâce à l'enquête de la première année (2001-02). Cette première enquête nous a permis en outre de repérer quelques écoles dont le fonctionnement en cycles est particulièrement typique des modèles les plus courants et quelques écoles où il est, au contraire, singulier et atypique. c) Les apports de la littérature en sciences de l'éducation : Nous avons fait appel aux acquis actuels de la recherche en sciences de l'éducation pour déterminer les dispositifs pédagogiques et didactiques les plus propres à réaliser le but de l'organisation en cycles. Nous avons pu ainsi réunir des indications concernant la pédagogie différenciée, le respect de la continuité dans les apprentissages, l'évaluation formative, la collaboration entre les enseignants, le redoublement et l'année complémentaire. d) La deuxième enquête : étude de terrain dans 10 écoles (25 cycles) : Nous avons voulu, dans cette deuxième enquête conduite en 2002-03, cerner au plus près le fonctionnement en cycles de 10 écoles, au moyen de différents outils (entretiens avec les directions, entretiens avec les équipes, observations de séances de classe, questionnaire auprès des enseignants, évaluation de compétences complexes mais aussi de procédures et tests d'estime de soi auprès des élèves). Il s'agissait là de saisir concrètement aussi bien les formes organisationnelles que les pratiques pédagogiques mises en oeuvre dans le cadre des cycles, d'en repérer les effets sur les élèves et de les référer au but assigné aux cycles par le législateur. e) L'élaboration du vade mecum Sur la base des renseignements collectés, nous avons pu construire un document d'accompagnement qui comprend trois parties : • Une tentative pour définir d'une manière concise et précise ce qu'est l'organisation en cycles (et, sur certains points, ce qu'elle n'est pas). • Des indications détaillées sur les formes organisationnelles et les pratiques pédagogiques possibles, avec leur intérêt et leurs difficultés éventuelles. • Des propositions d'activités et de thèmes de réflexion permettant à une équipe d'école de se préparer à la mise en place des cycles.

As computing devices become ubiquitous and increasingly mobile, it is becoming apparent that the directed peerto-peer communication model has shortcomings for many forms of distributed interprocess communication. Undirected communication, including content-based messaging, is becoming increasingly common. This paper examines the issues involved in supporting content-based messaging to both mobile devices and users using a combination of connected and mobile (possibly disconnected) devices. These issues include persistence, multi-client shared subscriptions, non-destructive notification receipt, and notification expiry. The discussion is placed in the context of the development of a proxy-server to provide disconnectedness support for the Elvin content-based messaging service.

Our experience shows that students have difficulty understanding how operating systems work. A theoretical study of the main functions of an operating system does not give students a feel for how these functional components interact to provide a service to the user. Some way is needed to help teach the theoretical material more effectively. We have chosen a simple graphical technique to develop DYNAMIX, a tool that displays the internals of a popular operating system and demonstrates the interaction among its functional components. In this paper we describe the development of DYNAMIX and show how it can be used in the classroom.

Thoth is a real-time operating system which is designed to be portable over a large set of machines. It is currently running on two minicomputers with quite different architectures. Both the system and application programs which use it are written in a high-level language. Because the system is implemented by the same software on different hardware, it has the same interface to user programs. Hence, application programs which use Thoth are highly portable. Thoth encourages structuring programs as networks of communicating processes by providing efficient interprocess communication primitives.

Computational grids allow the sharing of geographically distributed computational resources in an efficient, reliable, and secure manner. Grid is still in its infancy, and there are many problems associated with the computational grid, namely job scheduling, resource management, information service, information security, routing, fault tolerance, and many more. Scheduling of jobs on grid nodes is an NP-class problem warranting for heuristic and meta-heuristic solution approach. In the proposed work, a meta-heuristic technique, auto controlled ant colony optimization, has been applied to solve this problem. The work observes the effect of interprocess communication in process to optimize turnaround time of the job. The proposed model has been simulated in Matlab. For the different scenarios in computational grid, results have been analyzed. Result of the proposed model is compared with another meta-heuristic technique genetic algorithm that has been applied for the same purpose. It is found that auto controlled ant colony optimization not only gives better solution in comparison to genetic algorithm, but also converges faster because initial solution itself is good because of constructive and decision-based policy adapted by the former. Concurrency and Computation: Practice and Experience, 2012.

SUMMARYComputational grids allow the sharing of geographically distributed computational resources in an efficient, reliable, and secure manner. Grid is still in its infancy, and there are many problems associated with the computational grid, namely job scheduling, resource management, information service, information security, routing, fault tolerance, and many more. Scheduling of jobs on grid nodes is an NP‐class problem warranting for heuristic and meta‐heuristic solution approach. In the proposed work, a meta‐heuristic technique, auto controlled ant colony optimization, has been applied to solve this problem. The work observes the effect of interprocess communication in process to optimize turnaround time of the job. The proposed model has been simulated in Matlab. For the different scenarios in computational grid, results have been analyzed. Result of the proposed model is compared with another meta‐heuristic technique genetic algorithm that has been applied for the same purpos...

A Network-on-Chip (NoC) is an energy-efficient on-chip communication architecture for Multi-Processor System-on-Chip (MPSoC) architectures. In an earlier paper we proposed a energy-efficient reconfigurable circuit-switched NoC to reduce the energy consumption compared to a packetswitched NoC. In this paper we investigate a chordal slotted ring and a bus architecture that can be used to handle the best-effort traffic in the system and configure the circuitswitched network. Both architectures are compared on their latency behavior and power consumption. At the same clock frequency, the chordal ring has the major benefit of a lower latency and higher throughput. But the bus has a lower overall power consumption at the same frequency. However, if we tune the frequency of the network to meet the throughput requirements of control network, we see that the ring consumes less energy per transported bit.

The performance of large software systems based on a server-slave architecture depends heavily on the design of the interprocess communication (IPC) protocol. In this paper different approaches of the logical structure of the protocol of the IPC communication are proposed and analyzed. The term of a logical protocol unit (LPU) is defined. All basic actions of the software system are logically grouped into units and transferred jointly via the interprocess communication facilities of the underlying operating system. An algorithm is given for the calculation of specific LPUs.

Emerging Metro Ethernets create new opportunities to converge data and telephony services. However, to connect legacy telephony equipment, networks have to meet customary QoS requirements even at the presence of bursty data cross traffic. We show with active probing measurements that without appropriate mechanisms the QoS requirements cannot be met. Thus, mechanisms for priorization are needed.

Efficient exploration of the system design space necessitates fast and accurate performance estimation as opposed to the computationally prohibitive alternative of exhaustive simulation. This paper addresses the issue of worst-case performance analysis of a system described as a set of concurrent communicating processes. We show that the synchronization overhead associated with inter-process communication can contribute significantly to the overall system performance. Application of existing performance analysis techniques, which target single process descriptions, lead to inaccurate performance estimates as the synchronization overhead is not accounted for. We present PERC, a fast and accurate worst-case performance analysis technique which analyzes inter-process communication, and accounts for synchronization overhead while computing the worst-case performance estimate of a given system implementation. Application of PERC to example systems described as multiple communicating processes shows the ability of the proposed method to accurately estimate the worst-case performance of the system implementation.

The EOS project is investigating the design and construction of a family of real-time distributed embedded operating systems for reliable, distributed aerospace Distributed Systems D. A Physical Device Model for Path Pascal E. Lightweight processes in an object-oriented system ! ! ! Project EOS: Mid-Year Report Project EOS: Mid-Year Report G based operating system design. The motivation for this evolution is that current operating systems are difficult to adapt to new, multi-computer/multi-processor architectures and reliable applications. The structure of many of today's operating systems are based on a sixties perception of time-sharing and real-time operation. Instead of a centralized timesharing or real-time operating system model, research is concentrating on a model systems has improved and new operating system concepts introduced. However, improved understanding of the structure of an operating system is not, by itself, a motivating force to develop a new operating system. It is our belief that the change in communication bandwidth will change how resources within a computer system are managed and that this will provide the major motivation to redesign operating systems. Adaptive and reliable system architectures provide additional motivation to explore new operating system designs, It is our intention to build a prototype embedded operating system which can be used as a testbed to decide how best aerospace operating systems _^..

In this article, we propose a new framework based on dataflow graphs to abstract and analyze designs for hardware architectures. It is called Actors with Stretchable Access Patterns (ASAP). It can overcome some limitations of all Static Data Flow (SDF) based models like mandatory buffering between actors. This article details the fundamental contributions of ASAP. Firstly, it gives the definition of actors and their different patterns. It also illustrates the link between these notions and components written in VHDL through several examples. Secondly, it presents the main algorithms to check if a graph processes an input data stream correctly, which is called compatibility checking. Thirdly, it summarizes the principles of graph modification to enforce this correctness in case of some blocks are declared incompatible. Finally, it briefly describes our EDA tool called BlAsT which integrates the above principles, before presenting an application on a realistic FPGA design. It shows that ASAP overwhelms other models in terms of resources saving without any impact on the global latency. It also points out the ability of BlAsT to compute and to propose graph modifications and to generate the VHDL code of the whole design.

Races in Message Sequence Charts may lead to a bad interpretation of described behaviours, and are often considered as a design error. While there is a quadratictime algorithm detecting races in Basic Message Sequence Charts (BMSCs), the problem is undecidable for High-level Message Sequence Charts (HMSCs). To improve this negative situation for HMSCs, we introduce two new notions: a new concept of race called trace-race and an extension of the HMSC formalism with open coregions, i.e. coregions that can extend over more than one BMSC. We present three arguments showing benefits of our notions over the standard notions of race and HMSC. First, every trace-race-free HMSC is also race-free. Second, every race-free HMSC can be equivalently expressed as a trace-race-free HMSC with open coregions. Last, the trace-race detection problem for HMSC with open coregions is decidable and PSPACE-complete (the problem is in P if the number of processes and gates is fixed).

Deploying advanced automated testing techniques, such as model-based testing, relies upon the development of rigorous models. Our extensive experience in trying to develop and deploy model-based testing within a large industrial setting has led us to the conclusion that developing requirement models is essential for good model-based testing practice. However, not only are requirements speciflcations generally incomplete, but it is also di-cult to get system architects and designers to produce requirements with the rigor needed for automation. Hence, incentives are needed that tend towards the development of rigorous requirement models. To this end, we introduce the Mint tool that enables and helps automate the early detection of errors during require- ments development and appraisal. The paper describes and discusses at length the semantic interpretation of scenario- based requirements and the various types of pathologies that can be detected. We also introduce a UML 2.0 proflle for...

This position paper outlines a new network architecture that is based on the fundamental principle that networking is interprocess communication (IPC). In this model, application processes (APes) communicate via an IPC facility. The IPC processes that make up this facility provide a protocol that implements an IPC mechanism, and a protocol for managing distributed IPC (routing, security and other management tasks). Our architecture is recursive in that the IPC processes can themselves be APes requesting services from lower IPC facilities. We present the repeating patterns and structures in our architecture, and show how the proposed model would cope with the challenges faced by today's Internet (and that of the future).

In this paper we describe LiveNet, a flexible wearable platform intended for long-term ambulatory health monitoring with real-time data streaming and context classification. Based on the MIT Wearable Computing Group's distributed mobile system architecture, LiveNet is a stable, accessible system that combines inexpensive, commodity hardware; a flexible sensor/peripheral interconnection bus; and a powerful, light-weight distributed sensing, classification, and inter-process communications software architecture to facilitate the development of distributed real-time multi-modal and context-aware applications. LiveNet is able to continuously monitor a wide range of physiological signals together with the user's activity and context, to develop a personalized, data-rich health profile of a user over time. We demonstrate the power and functionality of this platform by describing a number of health monitoring applications using the LiveNet system in a variety of clinical studies that are underway. Initial evaluations of these pilot experiments demonstrate the potential of using the LiveNet system for real-world applications in rehabilitation medicine.

In this paper we describe LiveNet, a flexible wearable platform intended for long-term ambulatory health monitoring with real-time data streaming and context classification. Based on the MIT Wearable Computing Group's distributed mobile system architecture, LiveNet is a stable, accessible system that combines inexpensive, commodity hardware; a flexible sensor/peripheral interconnection bus; and a powerful, light-weight distributed sensing, classification, and inter-process communications software architecture to facilitate the development of distributed real-time multi-modal and context-aware applications. LiveNet is able to continuously monitor a wide range of physiological signals together with the user's activity and context, to develop a personalized, data-rich health profile of a user over time. We demonstrate the power and functionality of this platform by describing a number of health monitoring applications using the LiveNet system in a variety of clinical studies th...

This paper describes interprocess communication and process dispatching on the Intel 432. The primary assets of the facility are its generality and its usefulness in a wide range of applications. The conceptual model, supporting mechanisms, available interfaces, current implementations, and absolute and comparative performance are described.

A unified facility for interprocess communication and processor dispatching on the Intel 432 is described. The facility is based on a queuing and binding mechanism called a port. The goals and motivations for ports, both abstract and implementation views of them, and their absolute and comparative performance are described.

The Intel iAPX 432 is an object-based microcomputer which, together with its operating system iMAX, provides a multiprocessor computer system designed around the ideas of data abstraction. iMAX is implemented in Ada and provides, through its interface and facilities, an Ada view of the 432 system. Of paramount concern in this system is the uniformity of approach among the architecture, the operating system, and the language. Some interesting aspects of both the external and internal views of iMAX are discussed to illustrate this uniform approach.

This paper describes interprocess communication and process dispatching on the Intel 432. The primary assets of the facility are its generality and its usefulness in a wide range of applications. The conceptual model, supporting mechanisms, available interfaces, current implementations, and absolute and comparative performance are described. The Intel 432 is an object-based multiprocessor. There are two processor types: General Data Processors (GDPs) and Interface Processors (IPs). These processors provide several operating system functions in hardware by defining and using a number of processor-recognized objects and high-level instructions. In particular, they use several types of processor-recognized objects to provide a unified structure for both interprocess communication and process dispatching. One of the prime motivations for providing this level of hardware support is to improve efficiency of these facilities over similar facilities implemented in software. With greater eff...

A unified facility for interprocess communication and processor dispatching on the Intel 432 is described. The facility is based on a queuing and binding mechanism called a port. The goals and motivations for ports, both abstract and implementation views of them, and their absolute and comparative performance are described.

This paper presents a proposal of a language, based on synchronous active objects that introduces the CSP primitives into Java. The proposal does not use channels to realise the inter-process communications, but is shown to offer the same expressive power as the channel based solutions. The paper also shows that the rendezvous defined by CSP or our synchronous objects are very well adapted to the industrial development of event driven applications, handling simultaneously GUIs and accesses to remote applications.

This paper aims at discussing several issues, both theoretical and practical, concerning family communication: theories, roles, rules, conflicts, negotiation. The authors stress the interconnection between the social, economic, psychological and cultural factors which can, through effective communication, lead to good, trust-based relationships within families/at the family level. The Literature review section approaches the concepts of communication and family, while the Case study shows the objectives, activities and outcomes of a program implemented in South Africa and focused on parents' roles and duties within the family. It tackles issues linked to fatherhood, low literacy, domestic abuse, father absence, unemployment, and a wide array of other social and cultural factors pertaining to the social and economic conditions in this country. The paper also includes some recommendations concerning the adequate and efficient use of certain family communication forms, channels and feedback strategies.

This paper proposes a novel inter-process communication, between a virtual world manager with slow update rate and a haptic controller with fast update rate, which incorporates the integrated force given from the user to the world. High-speed refresh rate, generally 1kHz, is required to present, stiff virtual objects that, have spring-damper characteristic with haptic display. On the other hand, the managing of an interactive and rich virtual world that takes a lot of computational time makes the refresh rate as low as 10Hz, which is enough for perceptual cycle. The dividing of the process into two has been proposed to interact with such a world and inter-process communication between the processes has been discussed. Although the methods proposed previously work well on condition that the virtual world is static, goes wrong on dynamic world. The importance of the force integration on the object, motion acquisition is described and an inter-process communication that cares about the...

This paper describes a new architecture for high performance distributed applications and a supporting framework. This architecture applies object-oriented design and im plementation techniques to build a framework for platform-independent distributed ap plication specification and implementation using existing programming languages and operating systems. It utilizes an efficient and extensible layering architecture that al lows new abstract data types, new presentation-layer protocols, and new interprocess communication mechanisms to be added as they become necessary. Experimental re sults are presented demonstrating that the multiple layers of abstraction used do not compromise efficiency.

Clouds is a native operating system for a distributed environment. The Clouds operating system is built on top of a kernel called Ra. Ra ís a second generation kernel derived from our experi- ence with the first version of the Clouds operating system. Rø is a minimal, flexible kernel that pro- vides a framework for implementing a variety of distributed

The proposed work explores the interprocess communication across communicating parallel tasks in a mobile cluster. The process which is linked with specific mobile or static nodes will not be resilient to the changing conditions of the mobile cluster. The proposed Mobile Distributed Pipes (MDP) model enables the location independent intertask communication among the processes executing in static and mobile nodes. This novel approach enables the migration of communicating parallel tasks during runtime, which occurs according to the context and location requirements. A transparent programming model for a parallel solution to Iterative Mobile Grid Computations (IMGC) using MDP is also proposed. The proposed model is resilient to the heterogeneity of nodes such as static or mobile and the changing conditions in the mobile cluster because of mobility. The design of runtime and functional library support for the proposed model is also presented.

The proposed work explores the interprocess communication across communicating parallel tasks in a mobile cluster. The process which is linked with specific mobile or static nodes will not be resilient to the changing conditions of the mobile cluster. The proposed Mobile Distributed Pipes (MDP) model enables the location independent intertask communication among the processes executing in static and mobile nodes. This novel approach enables the migration of communicating parallel tasks during runtime, which occurs according to the context and location requirements. A transparent programming model for a parallel solution to Iterative Mobile Grid Computations (IMGC) using MDP is also proposed. The proposed model is resilient to the heterogeneity of nodes such as static or mobile and the changing conditions in the mobile cluster because of mobility. The design of runtime and functional library support for the proposed model is also presented.

Introduction This PhD Thesis is the result of a four-year research project conducted at the Department of Functional Programming, the Faculty of Mathematics and Informatics, at the University of Nijmegen as 'Assistent-in-Opleiding' under supervision of Professor M.J. Plasmeijer. In this chapter we give a survey of the research project and its theses. 1.1 Functional programming and the Clean project 3 we will encounter some of these cases which show up because of the complexity of the I/O system. The functional programming language we consider in this PhD.Thesis is pure and lazy. Due to strong normalisation lazy functional languages are preferable over their eager relatives. However, lazyness complicates their implementation. In general lazy languages are less time and space efficient than eager languages, or imperative languages. A lot of research has been conducted in this area in the last decades, and is still continuing. One specific approach to investigate and provide solutions to the problems of efficient implementations of functional languages is the (Concurrent) Clean project. Clean is a sequential lazy, purely functional programming language (

PORT is a real-time operating system designed to operate over a large set of computer systems. It can run on computers with different architectures. It makes use of a common high-level language for both the system and application programs. As the system is implemented by the identical software on different hardware, it will have the similar interface to user programs. Hence, application programs which use PORT are highly portable. PORT enables viewing programs as networks of communicating processes by providing efficient interprocess communication primitives.

There have been many proposals of shared memory systems, each one providing different types of memory coherence for interprocess communication. However, they have usually been defined using different formalisms. This makes it difficult to compare among them the different proposals put forward. In this paper we present a formal framework for specifying memory models with different coherency properties. We specify most of the known shared memory models using our framework, showing some of the relationships that hold among them.

The nature of product modeling systems and related application programs for design and manufacture makes it difficult to integrate them into a consistent and dynamic environment. This has been especially true for rule-based application programs. Through the use of standardized functional interfaces and UNIX interprocess communication, an environment has been developed that allows modelers and application programs to behave like objects within the integration environment. Each modeler and application (objects in the system) runs as a separate process. Each object has specific methods associated with it and also incorporates the concepts of data hiding and encapsulation. The object-oriented approach creates an environment that is service oriented vs. the traditional data-oriented approach. The software that creates and controls this environment is called the Information Services Exchange (ISX). ISX is currently being used to implement a project sponsored by Computer Aided Manufacturing-International (CAM-I) aimed at integrating a wide range of product development software. The approach developed within ISX could have a significant effect on design of diverse and large-scale product development systems.

In this paper we present a cost-effective, high bandwidth server I/O network architecture, named PaScal (Parallel and Scalable). We use the PaScal server I/O network to support data-intensive scientific applications running on very large-scale Linux clusters. PaScal server I/O network architecture provides (1) bi-level data transfer network by combining high speed interconnects for computing Inter-Process Communication (IPC) requirements and low-cost Gigabit Ethernet interconnect for global IP based storage/file access, (2) bandwidth on demand I/O network architecture without rewiring and reconfiguring the system, (3) Multi-path routing scheme, (4) reliability improvement through reducing large number of network components in server I/O network, and (5) global storage/file systems support in heterogeneous multi-cluster and Grids environments. We have compared the PaScal server I/O network architecture with the Federated server I/O network architecture (FESIO). Concurrent MPI-I/O performance testing results and deployment cost comparison demonstrate that the PaScal server I/O network architecture can outperform the FESIO network architecture in many categories: cost-effectiveness, scalability, and manageability and ease of large-scale I/O network.

This research provides an in-depth analysis of the development and significance of heterogeneous computing systems, focusing particularly on their implementation in the C programming language. The study reviews historical advancements in computing systems, such as parallel processing, load balancing, and RISC architectures, which played a pivotal role in the evolution of heterogeneous systems. It highlights key contributions from renowned figures like Gene Amdahl, John L. Hennessy, and David Patterson, whose work laid the foundations for efficient parallelism and multi-processor environments. Through practical C implementations, the research demonstrates critical concepts such as task distribution, core speed-up calculations, and inter-process communication. Networking and communication technologies, essential for heterogeneous systems, are also explored through examples of TCP/IP socket programming.

Fora variety ofreasons, distributed applications often must beimplemented using exist ing conventional programming languages and operating systems. Creating new high perfor mance distributed applications without high-level support from the programming language or operating system requires thatthe mechanism of distribution be selected early in the de sign stage, reducing the flexibility and/or efficiency of the design and subsequent imple mentation. Adding distribution to existing applications can result in an inordinate amount of reengineering duetothecomplexity andheterogeneity of interapplication communication mechanisms and their interfaces. This paper describes a new architecture for high performance distributed applications and a supporting framework. This architecture applies object-oriented design and imple mentation techniques tobuild a framework forplatform-independent distributed application specification and implementation using existing programming languages and operating sys tems. It utilizes an efficient and extensible layering architecture that allows new abstract data types, new protocols, and new interprocess communication mechanisms to be addedas they become necessary. h 6.

In this article we present the PAcceptor and SConnector frameworks that facilitate rapid deployment of applications that require both concurrency and inter-process communication system services. The PAcceptor and SConnector frameworks encapsulate both threads -primitive for concurrency --and sockets -primitive for inter-process communication --. These frameworks present a single interface to these disparate but essential services and thus promote the use of these abstractions in combination with ease. These frameworks may be customized to fabricate arbitrary applications by providing appropriate hotspot definitions. The frameworks obviate the need for explicit understanding and expertise over the underlying system servicessockets and threads -as well as the intricacies involved in combining the native socket and thread level services. The PAcceptors accept incoming connect requests using socket and provide service in parallel using threads while the SConnectors permit one or more threads to share a single connection to send data over the connection. Robust infrastructures for distributed and concurrent computing have been available for well over a decade and yet significant effort is required to exploit these services. As evidenced by a recent Technical Opinion column "Parallel Computing Still Not Ready for the Mainstream", in CACM the reason is neither due to the lack of infrastructures nor due to our cognitive ability to manage parallelism and concurrency. To the contrary parallelism and concurrency are quite innate and we thrive based on our ability to solve problems concurrently. The reason for the lack of use of these powerful technologies, we posit, is due to the combinatorial explosion of the conceptual difficulty in leveraging these abstract albeit powerful system services. Simplicity and maintainability is chosen over --better performance-and overwhelming complexity. Thus, in this article we present the PAcceptor and SConnector frameworks --which encapsulate these system level abstractions, hiding many of the difficult conceptual aspects--such that these high performance services may be leveraged sans their associated conceptual barriers. Programming with threads --an abstraction for concurrency --and sockets --an abstraction for inter-process communication --is anything but simple. Both conceptually { timing errors, race conditions, synchronization } and programmatically { thread attributes, socket options, and notational nuances } programming with these services is highly distractive in nature for application developers. Combining these two abstractions is even more complex. Understandably, more often than not engineers trade performance for simplicity and choose not to use these high performance devices solely due to the complexity involved. It is in this context that frameworks become highly relevant. Frameworks mitigate the barriers and promote the use of such complex abstractions by encapsulating them, while preserving the associated semantics [See 2 for examples].

In this paper we present StarFish, a highly-available geographically-dispersed block storage system built from commodity servers running FreeBSD, which are connected by standard high-speed IP networking gear. StarFish achieves high availability by transparently replicating data over multiple storage sites. StarFish is accessed via a host-site appliance that masquerades as a host-attached storage device, hence it requires no spe- cial hardware

Real-time operating system services are required to support multimedia systems that rely heavily of the workstation processor for control of the audio and video processors and movement of audio and video data. Such services are typically not available in existing workstation operating systems. This note comments on the requirements for such services and briefly describes the YARTOS kernel; an operating system kernel that provides real-time communication and computation services.

The design of general purpose operating systems impose constraints on the way one can structure real-time applications. This paper addresses the problem of minimizing the end-to-end latency of applications that are structured as a set of cooperating (real-time) tasks. When applications are structured as a set of cooperating tasks the time required for data to progress from an input task to an output task is a function of the number of the tasks that handle the data and the deadlines of individual tasks. We present an integrated inter-process communication and scheduling scheme that can be used to minimize the end-to-end latency of multi-threaded applications. Our approach is to provide the scheduler with information on the inter-process communication interconnections between tasks and to use this information to guarantee an end-to-latency to applications that is simply a function of the timing properties of the application and not its task structure. This scheme has been implemented within the YARTOS kernel and is presently being ported to the Real-Time Mach kernel.

SystemC and Transaction Level Modeling (TLM) have become the de-facto standard for Electronic System Level (ESL) design. For the costly task of verification at ESL, simulation is the most widely used and scalable approach. Besides the Design Under Test (DUT), the TLM verification environment typically consists of stimuli generators and checkers where the latter are responsible for detecting errors. However, in case of an error, the subsequent debugging process is still very timeconsuming. In this paper, we present a scalable fault localization approach for SystemC TLM designs. The approach targets the described standard TLM verification environment and can be easily integrated into one. Our approach is inspired by software diagnosis techniques. We extend the concept of execution profiles of software programs, also known as program spectra, to handle the TLM simulation. The whole simulation consists of several runs; each run corresponds to the request-DUT-response path. During simulation our approach individually collects spectra for each run. Then, based on analyzing the differences of passed and failed runs we determine possible fault locations. We demonstrate the quality of our approach by several experiments including TLM-2.0 designs. As shown in the experiments, the fault locations are identified accurately and very fast.

The nature of product modeling systems and related application programs for design and manufacture makes it difficult to integrate them into a consistent and dynamic environment. This has been especially true for rule-based application programs. Through the use of standardized functional interfaces and UNIX interprocess communication, an environment has been developed that allows modelers and application programs to behave like objects within the integration environment. Each modeler and application (objects in the system) runs as a separate process. Each object has specific methods associated with it and also incorporates the concepts of data hiding and encapsulation. The object-oriented approach creates an environment that is service oriented vs. the traditional data-oriented approach. The software that creates and controls this environment is called the Information Services Exchange (ISX). ISX is currently being used to implement a project sponsored by Computer Aided Manufacturing-International (CAM-I) aimed at integrating a wide range of product development software. The approach developed within ISX could have a significant effect on design of diverse and large-scale product development systems.

In this Master thesis, I will introduce CommSensum, a community sensor network developed by CompNet research group. I will explain what are the needs that led to creating the platform, how is the platform until now and I will focus on the security issue. As it is a platform that is beginning its first deployment tests, security issues had been sidelined. But now, the first steps need to be done. Therefore, this thesis will analyze the various security options that exist, I will analyze which of these options are able to be adapted to the sensor network environment. Also, I will explain how the main bottleneck to provide of security to this type of platform ithe nodes own hardware limitation. I will analyze two main factors in the system to understand why there is no possibility to use HTTPS, RN171 WiFi module and mote's limitations. In addition I will compare already existing work, how other researchers design different wireless sensor network structures to give a solution. Some tricks can be done having a proxy or a intermediate router. Once immersed in the topic, I will analyze the components of CommSensum and see what security schemes I can develop. Finally, I will also provide the functions needed to implement secure connections between the nodes and the server. All of these function will run on the mote and with its hardware limitations. I will provide too, some function using RSA to use in future in a future Waspmote version or another Arduino board because in the actual version there is not enough SRAM. Finally, I presents some conclusions and future work possible to continuing implementation of the security in CommSensum platform.

Securing off-chip main memory is essential for protection from adversaries with physical access to systems. However, current secure-memory designs incur considerable performance overheads-a major cause being the multiple memory accesses required for traversing an integrity-tree, that provides protection against man-in-the-middle attacks or replay attacks. In this paper, we provide a scalable solution to this problem by proposing a compact integrity tree design that requires fewer memory accesses for its traversal. We enable this by proposing new storage-efficient representations for the counters used for encryption and integrity-tree in secure memories. Our Morphable Counters are more cacheable on-chip, as they provide more counters per cacheline than existing split counters. Additionally, they incur lower overheads due to counter-overflows, by dynamically switching between counter representations based on usage pattern. We show that using Morphable Counters enables a 128ary integrity-tree, that can improve performance by 6.3% on average (up to 28.3%) and reduce system energy-delay product by 8.8% on average, compared to an aggressive baseline using split counters with a 64-ary integrity-tree. These benefits come without any additional storage or reduction in security and are derived from our compact counter representation, that reduces the integrity-tree size for a 16GB memory from 4MB in the baseline to 1MB. Compared to recently proposed VAULT [1], our design provides a speedup of 13.5% on average (up to 47.4%).

, he has been in the computer field since 1950. At SRI Intemational, he directed the ERMA project that developed the first computer system for the banking industry in the 1950's and served as Executive Director of the Information Science and Engineering division from 1961 to 1968. He then served eight years as Chairman of Computer Science at the University of Washington. While at SRI he was a lecturer at Stanford, and during 1976-1977 he was a Visiting Professor at the Vrije Universiteit in Amsterdam. Dr. Noe is a member of Eta Kappa Nu, Tau Beta Pi, Sigma Xi, and the Association for Computing Machinery.

Rapid Prototyping has been proposed as a means to reduce development time and costs of real-time systems. Our approach uses a heterogeneous, tightly coupled multiprocessor system based on off-the-shelf components as target architecture for an executable prototype, which is generatedfrom the specification in an automated design process. Here, too, we aim to use existing tools and languages. But interface and communication synthesis, while being the key requirement of an automated translation of a abstract specification to a distributed system, is not yet state-of-the-art. The sensitivity of the overall performance of multiprocessor systems to overhead and latency introduced by communication on the other hand calls for an efficient interprocess communication (IPC). This paper presents concept and implementation of IPC functions which, implementing the message queue semantics of the specification language SDL, links the standard components of our multiprocessor system in an efficient manner, while at the same time providing the interface synthesis needed by the automated generation of a rapid prototype. The experiences gained when implementing a non-trivial, real-world CAN controller and monitor application on our rapid prototyping environment, are described as a first proof of concept.