Error Detection and Correction

Recentl y, the search for a unifying concept of the functional nature of anterior cingulate cortex (ACC) has become an important topic of research in cognitive neuroscience 1,2 . Neuroimaging 3 and electrical recording methods 4 have led to related but somewhat different conceptions for the role of ACC in information processing.

Traditional adaptive methods that compensate for PVT variations need safety margins and cannot respond to rapid environmental changes. In this paper, we present a design (RazorII) which implements a flip-flop with in situ detection and architectural correction of variation-induced delay errors. Error detection is based on flagging spurious transitions in the state-holding latch node. The RazorII flip-flop naturally detects logic and register SER. We implement a 64-bit processor in 0.13 m technology which uses RazorII for SER tolerance and dynamic supply adaptation. RazorII based DVS allows elimination of safety margins and operation at the point of first failure of the processor. We tested and measured 32 different dies and obtained 33% energy savings over traditional DVS using RazorII for supply voltage control. We demonstrate SER tolerance on the RazorII processor through radiation experiments.

This paper starts from the observation that firms are increasingly engaging in collaborations with their suppliers, even as they are reducing the extent to which they are vertically integrated with those suppliers. This fact seems incompatible with traditional theories of the firm, which argue that integration is necessary to avoid the potential for hold-ups created when non-contractible investments are made. Our view is that pragmatist mechanisms such as benchmarking, simultaneous engineering and 'root cause' error detection and correction make possible 'learning by monitoring'-a relationship in which firms and their collaborators continuously improve their joint products and processes without the need for a clear division of property rights. We argue that pragmatic collaborations based on 'learning by monitoring' both advance knowledge and control opportunism and thus align interests between the collaborators.

Adaptive motor behavior requires efficient error detection and correction. The posterior parietal cortex is critical for on-line control of reach-to-grasp movements. Here we show a causal relationship between disruption of cortical activity within the anterior intraparietal sulcus (aIPS) by transcranial magnetic stimulation (TMS) and disruption of goal-directed prehensile actions (either grip size or forearm rotation, depending on the task goal, with reaching preserved in either case). Deficits were elicited by applying TMS within 65 ms after object perturbation, which attributes a rapid control process on the basis of visual feedback to aIPS. No aperture deficits were produced when TMS was applied to a more caudal region within the intraparietal sulcus, to the parietooccipital complex (putative V6, V6A) or to the hand area of primary motor cortex. We contend that aIPS is critical for dynamic error detection during goal-dependent reach-to-grasp action that is visually guided.

There have been serious concerns recently about the security of microchips from hardware trojan horse insertion during manufacturing. This issue has been raised recently due to outsourcing of the chip manufacturing processes to reduce cost. This is an important consideration especially in critical applications such as avionics, communications, military, industrial and so on. A trojan is inserted into a main circuit at manufacturing and is mostly inactive unless it is triggered by a rare value or time event; then it produces a payload error in the circuit, potentially catastrophic. Because of its nature, a trojan may not be easily detected by functional or ATPG testing. The problem of trojan detection has been addressed only recently in very few works. Our work analyzes and formulates the trojan detection problem based on a frequency analysis under rare trigger values and provides procedures to generate input trigger vectors and trojan test vectors to detect trojan effects. We also provide experimental results.

In this paper, we present a dynamic voltage scaling (DVS) technique called Razor which incorporates an in situ error detection and correction mechanism to recover from timing errors. We also present the implementation details and silicon measurements results of a 64-bit processor fabricated in 0.18-m technology that uses Razor for supply voltage control. Traditional DVS techniques require significant voltage safety margins to guarantee computational correctness at the worst case combination of process, voltage and temperature conditions, leading to a loss in energy efficiency. In Razor-based DVS, however, the supply voltage is automatically reduced to the point of first failure using the error detection and correction mechanism, thereby eliminating safety margins while still ensuring correct operation. In addition, the supply voltage can be intentionally scaled below the point of first failure of the processor to achieve an optimal tradeoff between energy savings from further voltage reduction and energy overhead from increased error detection and correction activity. We tested and measured savings due to Razor DVS for 33 different dies and obtained an average energy savings of 50% over worst case operating conditions by scaling supply voltage to achieve a 0.1% targeted error rate, at a fixed frequency of 120 MHz.

In a recent ERP study of inhibitory control using the Stop-Signal Task [Pliszka, S., Liotti, M., Woldorff, M. (2000). Inhibitory control in children with attention-deficit/hyperactivity disorder: Event-related potentials identify the processing component and timing of an impaired right-frontal response-inhibition mechanism. Biological Psychiatry, 48, 238-246], we showed that in normal children (age 10-12 years) the Stop Signals elicited a robust, right-frontal-maximal N200 (latency ∼200 ms) that was strongly reduced in children with ADHD. To further investigate the mechanisms of response inhibition, this paradigm was applied to 11 healthy young adults. To better distinguish responseinhibition-related activity from early attentional effects, a "Stop-Signal-Irrelevant" condition was added, in which subjects performed the task while ignoring the Stop Signals. In the Stop-Signal-Relevant condition, the right frontal N200 to the Stop Signals was larger for Successful inhibition (SI) than for Failed inhibition (FI) trials. The timing and distribution of this effect was strikingly similar to that of the right-frontal ADHD deficit reported in , supporting this activity being related to successful normal inhibitory control processes. In contrast, a posterior N200 was larger for Stop-Relevant than for Stop-Irrelevant trials, likely reflecting enhanced early sensory attention to the Stop Signals when relevant. Two longer-latency failure-specific ERP effects were also observed: a greater frontopolar negative wave (370-450 ms) to Failed than Successful inhibitions, and a greater parietal positive slow wave (450-650 ms) for Failed inhibitions than ignorestop trials, likely reflecting differential recruitment of error detection and correction mechanisms following Failed attempts to inhibit a response.

In many computer systems, the contents of memory are protected by an error detection and correction (EDAC) code. Bit-flips caused by single event upsets (SEUs) are a well-known problem in memory chips and EDAC codes have been an effective solution to this problem. These codes are usually implemented in hardware using extra memory bits and encoding/decoding circuitry. In systems where EDAC hardware is not available, the reliability of the system can be improved by providing protection through software. Codes and techniques that can be used for software implementation of EDAC are discussed and compared. objective of our experiment is to see whether software-implemented hardware faulttolerance -which can include software-implemented EDAC -can provide sufficient reliability for COTS hardware to make it usable in low-radiation space applications.

Data from military / experimental flights and laboratory testing indicate that typical non radiation-hardened 64K and 256K static random access memories (SRAMs) can experience a significant soft upset rate at aircraft altitudes due to energetic neutrons created by cosmic ray interactions in the atmosphere. It is suggested that error detection and correction (EDAC) circuitry be considered for all avionics designs containing large amounts of semi-conductor memory.

Low voltage electrical wiring has largely been dismissed as too noisy and unpredictable to support high-speed communication signals. Advances in communication and modulation methodologies as well as in adaptive digital signal processing and error detection and correction have spawned novel protocols capable of supporting power line communication networks at speeds comparable to wired LANs. We motivate the use of power line LANs as a basic infrastructure for building integrated smart homes, wherein information appliances ranging from simple control or monitoring devices to multimedia entertainment systems are seamlessly interconnected by the very wires that provide them electricity. By simulation and actual measurements using "reference design" prototype commercial powerline products, we show that the HomePlug MAC and PHY layers can guarantee QoS for real-time communications, supporting delay-sensitive data streams for smart home applications.

 Many interactive human skills are based on real-time error detection and correction. Here we investigate the spectral properties of such skills, focusing on a synchronization task. A simple autoregressive error correction model, based on separate ‘motor’ and ‘cognitive’ sources, provides an excellent fit to experimental spectral data. The model can also apply to recurrent processes not based on error correction, allowing commentary on previous claims of 1/ f-type noise in human cognition. A comparison of expert and non-expert subjects suggests that performance skill is not only based on reduced variance and bias, but also on the construction of richer mental models of error correction.

In this paper, we present a new technique to improve the reliability of SRAMs used in space radiation environments. This technique deals with the SRAM power-bus monitoring by using Built-In Current Sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of the memory cell being upset. The current checking is performed on the SRAM columns and it is combined with a single-parity bit per RAM word to perform error Correction.

Embedded systems are becoming increasingly complex. Besides the additional processing capabilities, they are characterized by high diversity of computational models coexisting in a single device. Although reconfigurable architectures have already shown to be a potential solution for such systems, they just present significant speedups of very specific dataflow oriented kernels. Furthermore, reconfigurable fabric is still withheld by the need of special tools and compilers, clearly not sustaining backward software compatibility. In this paper, we propose a new technique to optimize both dataflow and control-flow oriented code in a totally transparent process, without the need of any modification in the source or binary codes. For that, we have developed a Binary Translation algorithm implemented in hardware, which works in parallel to a MIPS processor. The proposed mechanism is responsible for transforming sequences of instructions at runtime to be executed on a dynamic coarse-grain reconfigurable array, supporting speculative execution. Executing the MIBench suite, we show performance improvements of up to 2.5 times, while reducing 1.7 times the required energy, using trivial hardware resources.

This paper presents some results on multiple error detection and correction based on the Redundant Residue Number System (RRNS). RRNS is often used in parallel processing environments because of its ability to increase the robustness of information passing between the processors. The proposed multiple error correction scheme utilizes the Chinese Remainder Theorem (CRT) together with a novel algorithm that significantly simplifies the error correcting process for integers. An extension of the scheme further reduces the computational complexity without compromising its error correcting capability. Proofs and examples are provided for the coding technique.

Event-related potentials (ERPs) were used to investigate the cognitive and neural substrates of immediate and 1-week delayed error correction in a semantic retrieval task. In particular, we pursued the basis for the 'hypercorrection' effect, the finding that erroneous responses endorsed as correct with high confidence are more likely than low-confidence errors to be corrected at retest. Presentation of negative, but not positive feedback about the accuracy of one's response elicited a fronto-central negativity, similar to the ERN, which was somewhat sensitive to the degree to which negative feedback violated expectation. A fronto-central positivity, similar to the novelty-P3 / P3a, more generally indexed detection of a metamemory error, given that it was larger in conditions of high metamemory mismatch than in conditions of low metamemory mismatch, irrespective of absolute task accuracy. For errors, amplitude of the fronto-central positivity, but not the preceding negativity, was correlated with correction on an immediate retest. Thus, to the extent that the fronto-central positivity indexes an orienting response, this response appears to facilitate initial encoding processes, but does not play a key role in memory consolidation. In contrast, a broad, inferior-temporal negativity occurring 300-600 ms after presentation of the correct answer was sensitive to subsequent memory performance at both immediate and delayed retests, but only for answers containing familiar semantic information. This negativity may reflect processes involved in the formation of an association between the question and pre-existing semantic information.

Abstract-In this paper we study the problem of concurrent error detection and fault tolerance in linear analog circuits using continuous checksums. These checksums of time-varying functions are possible because the function of a linear analog circuit can be represented ...

Prosumer (producing consumer)-based desktop additive manufacturing has been enabled by the recent radical reduction in 3-D printer capital costs created by the open-source release of the self-replicating rapid prototype (RepRap). To continue this success, there have been some efforts to improve reliability, which are either too expensive or lacked automation. A promising method to improve reliability is to use computer vision, although the success rates are still too low for widespread use. To overcome these challenges an open source low-cost reliable real-time optimal monitoring platform for 3-D printing from double cameras is presented here. This error detection system is implemented with low-cost web cameras and covers 360 degrees around the printed object from three different perspectives. The algorithm is developed in Python and run on a Raspberry Pi3 mini-computer to reduce costs. For 3-D printing monitoring in three different perspectives, the systems are tested with four different 3-D object geometries for normal operation and failure modes. This system is tested with two different techniques in the image pre-processing step: SIFT and RANSAC rescale and rectification, and non-rescale and rectification. The error calculations were determined from the horizontal and vertical magnitude methods of 3-D reconstruction images. The non-rescale and rectification technique successfully detects the normal printing and failure state for all models with 100% accuracy, which is better than the single camera set up only. The computation time of the non-rescale and rectification technique is two times faster than the SIFT and RANSAC rescale and rectification technique.

An advanced stimulator for neuromuscular stimulation of spinal cord injured patients has been developed. The stimulator is externally controlled and powered by a single encoded radio frequency carrier and has four independently controlled bipolar stimulation channels. It offers a wide range of reprogrammability and flexibility, and can be used in many neuromuscular electrical stimulation applications. The implant system is adaptable to patient's needs and to future developments in stimulation algorithms by reprogramming the stimulator. The stimulator is capable of generating a wide range of stimulation waveforms and stimulation patterns and therefore is very suitable for selective nerve stimulation techniques. The reliability of the implant has been increased by using a forward error detection and correction communication protocol and by designing the chip for structural testability based on scan test approach. Implemented testability scheme makes it possible to verify the complete functionality of the implant before and after implantation. The stimulators architecture is designed to be modular and therefore its different blocks can be reused as standard building blocks in the design and implementation of other neuromuscular prostheses. Design for low-power techniques have also been employed to reduce power consumption of the electronic circuitry.

In this paper, we will show that the problem of signal reconstruction from missing samples can be handled by using reconstruction algorithms similar to the Reed-Solomon (RS) decoding techniques. Usually, the RS algorithm is used for error detection and correction of samples in finite fields. For the case of missing samples of a speech signal, we work with samples in the field of real or complex numbers, and we can use FFT or some new transforms in the reconstruction algorithm. DSP implementation and simulation results show that the proposed methods are better than the ones previously published in terms of the quality of recovered speech signal for a given complexity. The burst error recovery method using the FFT kernel is sensitive to quantization and additive noise like the other techniques. However, other proposed transform kernels are very robust in correcting bursts of errors with the presence of quantization and additive noise.

The feeling of error (FOE) is the subjective experience that something went wrong during a reasoning or calculation task. The main goal of the present study was to assess the accuracy of the FOE in the context of mental mathematical calculation. We used the number bisection task (NBT) to evoke this metacognitive feeling and assessed it by asking participants if they felt they have committed an error after solving the task. In the NBT participants have to determine whether the number presented in the middle οf a triplet corresponds to the arithmetic mean of the two outer numbers (e.g., 07_16_25) with a Yes/No answer. Our results show that FOE reports were strongly correlated with arithmetic errors and numerical properties of the NBT, suggesting that the FOE accurately represents the error. This finding indicates that even very fast metacognitive feelings are reliable when it comes to evaluating one’s own mental performance. Moreover, our results suggest that the occurrence of FOEs is determined by the fluency with which each triplet was solved and the post-decision evaluation processes that occurred after the NBT was solved. Additionally, we asked participants to report their confidence in the given answer for the cases where they did not report FOEs. Participants reported less confidence for the (objectively) incorrect answers than for the (objectively) correct ones, suggesting that in cases where they did not have a conscious FOE they still were able to implicitly detect their errors. Remarkably, confidence was also determined by the fluency of the NBT.

Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shipped to the customers fault-free. However, at-speed tests have been known to create higher-than-average switching activity, which normally is not accounted for in the design of the power supply network. This potentially creates conditions for additional delay in the chip; causing it to fail during test. In this paper, we propose a pattern compaction technique that considers the layout and gate distribution when generating transition delay fault patterns. The technique focuses on evenly distributing switching activity generated by the patterns across the layout rather than allowing high switching activity to occur in a small area in the chip that could occur with conventional delay fault pattern generation. Due to the relationship between switching activity and IR-drop, the reduction of switching will prevent large IR-drop in high demand regions while still allowing a suitable amount of switching to occur elsewhere on the chip to prevent fault coverage loss. This even distribution of switching on the chip will also result in avoiding hot-spots.

A method is proposed to compensate for local delay variations by adjusting the supply voltage of individual circuit blocks. In-situ characterization of sub-blocks allows for voltage adjustment with minimum safety margin. Different strategies and circuit techniques for in-situ delay characterization of sub-blocks are described and compared. A dual V DD power switch scheme is proposed for discrete voltage assignment to individual sub-blocks. Experimental results are presented for a test module based on an ARM9 core, fabricated in 130-nm CMOS. Yield improvement and power reduction capabilities are demonstrated by Monte Carlo simulations. For a typical setting, a reduction of 10% in power can be achieved with the proposed dual V DD power switch concept. Using more than two supply voltages is shown to produce only small additional power savings at the price of high area overhead. The effect of the proposed scheme increases with increasing intra-die variability, which makes it suitable especially for future technologies. Index Terms-Adaptive supply voltage (ASV), crystal ball flip-flop, dynamic voltage scaling (DVS), error detection and correction, in-situ characterization, local supply voltage assignment, Razor flip-flop.

In this paper we describe a methodology to measure exactly the quality of fault-tolerant designs by combining fault- injection in high level design (HLD) descriptions with a formal verification approach. We utilize BDD based symbolic simulation to determine the coverage of online error-detection and - correction logic. We describe an easily portable approach, which can be applied to a wide

All-optical digital circuits based on loop memories are demonstrated. These circuits are a variable optical buffer, an optical random access memory, an optical shift register, and an optical linear feedback shift register. Buffers are employed in network nodes to solve the contentions without loosing information. Shift registers are used for error detection and correction techniques. Linear feedback shift registers are employed for generation of pseudo-random bit sequences, data scrambling, and encryption/decryption of information in secure communication systems. Since the role of optical processing is gradually increasing within the communication systems, the possibility to store information directly in the optical domain can lead to a systems simplification and to a performance improvement. In order to make the schemes suitable for practical applications, optical integration is necessary. The use of semiconductor optical amplifier as gain element into the memory loop allows all the proposed schemes to be integrated.

The authors develop a coding theory approach to error control in residue number system product codes. Based on this coding theory framework, computationally efficient algorithms are derived for correcting single errors, double errors, and multiple errors, and simultaneously detecting multiple errors and additive overflow. These algorithms have lower computational complexity than previously known algorithms by at least an order of magnitude. In addition, it is noted that all the literature published thus far deals almost exclusively with single error correction

The notion that human error should not be tolerated is prevalent in both the public and personal perception of the performance of clinicians. However, researchers in other safety–critical domains have long since abandoned the quest for zero defects as an impractical goal, choosing to focus instead on the development of strategies to enhance the ability to recover from error. This paper presents a cognitive framework for the study of error recovery, and the results of our empirical research into error detection and recovery in the critical care domain, using both laboratory-based and naturalistic approaches. Both attending physicians and residents were prone to commit, detect and recover from errors, but the nature of these errors was different. Experts corrected the errors as soon as they detected them and were better able to detect errors requiring integration of multiple elements in the case. Residents were more cautious in making decisions showing a slower error recovery pattern, and the detected errors were more procedural in nature with specific patient outcomes. Error detection and correction are shown to be dependent on expertise, and on the nature of the everyday tasks of the clinicians concerned. Understanding the limits and failures of human decision-making is important if we are to build robust decision-support systems to manage the boundaries of risk of error in decision-making. Detection and correction of potential error is an integral part of cognitive work in the complex, critical care workplace.

Friedreich ataxia (FRDA) is the most common of the inherited ataxias. We have suggested that people with FRDA may have impairment in cognitive and/or psychomotor capacity either due to disturbance of projections of the cerebellum to the cortex, direct cortical pathology or perhaps both. To further explore this possibility, we used a movement task incorporating Fitts' Law, a robust description of the relationship between movement time and accuracy in goaldirected aiming movements. By manipulating task difficulty, according to target size and distance, we were able to quantify processes related to motor planning in 10 individuals with FRDA and 10 matched control participants. Compared to control participants, people with FRDA were significantly disadvantaged in terms of movement time to targets with an increasing index of difficulty. Successful completion of this task requires both preplanning of movement and online error detection and correction. The cerebellum and its connections to the frontal cortex via cerebro-ponto-cerebello-thalamo-cerebral loops are fundamental to both processes. These results lend further support to our contention that in FRDA these loops are impaired, reflecting a failure to access prefrontal/anterior regions necessary for effective management of preplanning of movement and online error correction.

Research on tools for automating the proofreading of Arabic text has received much attention in recent years. There is an increasing demand for applications that can detect and correct Arabic spelling and grammatical errors to improve the quality of Arabic text content and application input. Our review of previous studies indicates that few Arabic spell-checking research efforts appropriately address the detection and correction of ill-formed words that do not conform to the Arabic morphology system. Even fewer systems address the detection and correction of erroneous well-formed Arabic words that are either contextually or semantically inconsistent within the text. We introduce an approach that investigates employing deep neural network technology for error detection in Arabic text. We have developed a systematic framework for spelling and grammar error detection, as well as correction at the word level, based on a bidirectional long short-term memory mechanism and word embedding, in which a polynomial network classifier is at the top of the system. To get conclusive results, we have developed the most significant gold standard annotated corpus to date, containing 15 million fully inflected Arabic words. The data were collected from diverse text sources and genres, in which every erroneous and ill-formed word has been annotated, validated, and manually revised by Arabic specialists. This valuable asset is available for the Arabic natural language processing research community. The experimental results confirm that our proposed system significantly outperforms the performance of Microsoft Word 2013 and Open Office Ayaspell 3.4, which have been used in the literature for evaluating similar research.

This paper deals with an OCR (Optical Character Recognition) error detection and correction technique for a highly inflectional Indian language, Bangla, the second-most popular language in India and fifth-most popular language in the world. The technique is based on morphological parsing where using two separate lexicons of root words and suffixes, the candidate root-suffix pairs of each input string, are detected, their grammatical agreement is tested and the root/suffix part in which the error has occurred is noted. The correction is made to the corresponding error part of the input string by means of a fast dictionary access technique. To do so, the information about the error patterns generated by the OCR system are examined, and some alternative strings are generated for an erroneous word. Among the alternative strings, those satisfying grammatical agreement in root and suffix are finally chosen as suggested words. In the list of suggested words generated by the system, the desired word is available in 84.22% cases.

Errors introduced by radiation-induced single event upset and single event latchup in very deep submicron (VDSM) ICs necessitate concurrent error detection (CED) and correction. Power consumed by circuits used for detecting and correcting errors becomes an extra burden on the tight power budget of VDSM ICs. The triple-modular redundancy-based fault tolerance technique, which is traditionally used for error detection and correction, incurs over 200 percent power overhead. In this paper, we propose register-transfer level low-power on-demand error correction techniques. Proposed techniques implement an original computation and a recomputation in datapath and compare the results from two computations to monitor the health of circuit. A mismatch in results indicates faulty computation and a second recomputation is triggered to rectify the error. The proposed techniques can detect and correct SEU induced transient errors and detect SEL induced permanent errors with as little as 12 percent power overhead.

The difficulties involved in spelling error detection and correction in a language have been investigated in this work through the conceptualization of SpellNet-the weighted network of words, where edges indicate orthographic proximity between two words. We construct SpellNets for three languages-Bengali, English and Hindi. Through appropriate mathematical analysis and/or intuitive justification, we interpret the different topological metrics of SpellNet from the perspective of the issues related to spell-checking. We make many interesting observations, the most significant among them being that the probability of making a real word error in a language is propotionate to the average weighted degree of SpellNet, which is found to be highest for Hindi, followed by Bengali and English.

The paper is concerned with the problem of automatic detection and correction of inconsistent or out of range data in a general process of statistical data collecting. Under such circumstances, errors are usually detected by formulating a set of rules which the data records must respect in order to be declared correct. As a first relevant point, the set of rules itself is checked for inconsistency or redundancy, by encoding it into a propositional logic formula, and solving a sequence of Satisfiability problem. This set of rules is then used to detect erroneous data. In the subsequent phase of error correction, the above set of rules must be satisfied, but the erroneous records should be altered as little as possible, and frequency distributions of correct data should be preserved. As a second relevant point, error correction is modeled by encoding the rules with linear inequalities, and solving a sequence of set covering problems. The proposed procedure is tested on a real-world case of Census.

This study assessed motor limits of regular tapping, timing error detection, and correction in 60 participants aged from 19 to 98 years. Rate limitations on motor production were estimated from the average inter-tap interval when tapping as fast as possible for 30 s. Timing error detection required participants to judge whether a sound sequence presented at a slow, intermediate, or fast speed contained an irregularity because of phase shift. This was performed with or without synchronizing to the sounds. On the basis of the just-detectable positive phase shift (JND), participants synchronized with sequences containing phase shifts that were subliminal, just detectable or supraliminal. On average, JNDs were 9% of the inter-onset interval and by and large were not affected by synchronization tapping. Speed of error correction was estimated from the number of tones to return within 20% of the preshift synchronization error. Consistent with previous findings of motor slowing with aging, the fastest inter-tap interval increased with age. However, there was no age-related decline in JNDs or speed of error correction, both of which reflect predictive abilities for intervals within the motor repertoire of human adults. These results point towards intact timing error processing up to an advanced age. In assessing timing abilities in the brain of older adults, it is important to differentiate between motor slowing and its impact on rhythmic behavior (e.g., walking pace) from anticipatory mechanisms ('what to expect when') and how these are used to adjust the timing of actions ('what to do when').

In this paper we present the fundamenta. Lheory oft-Error Correcting, k-Error Detecting and d-Unidirectional Error Detecting codes with rl > k > t (t-ECIk-EDId-UED codes). We give a family of methods for designing systematic t-EClk-EDld-UED codes, with d > k > t , and we reveal the methods which give the more efficient, with respect to redundancy, codes for the various values off, k, and d. Also we present the error detection and correction algorithm.

Small satellites have to meet a big challenge: to answer high-performance requirements by means of small equipment and especially of small budgets. Out of all aspects the cost aspect is one of the most important driver for small satellite missions. To keep the costs within the low-budget frame (in comparison to big missions) the demonstration of new and not space-qualified technologies for the spacecraft is one key point in fulfilling high-performance mission requirements. Taking this into account the German DLR micro-satellite mission BIRD (Bi-spectral Infra-Red Detection) has to demonstrate a highperformance capability of spacecraft bus by using and testing new technologies basing on a mixed parts and components qualification level. The basic approach for accomplishing high-performance capability for scientific mission objectives under low-budget constraints is characterized by using • compact micro satellite structure with high mechanical stability and stiffness, • envelope qualification for several launchers,

In this paper an Algorithm Based Error Detection (ABED) scheme is applied to the multigrid algorithm which provides an iterative solution to a system of linear algebraic equations resulting from a finite difference discretization of a Poisson equation. Invariants are created to implement ...

Heartrate variability (HRV) is traditionally analyzed while a subject is in a controlled environment, such as at rest in a clinic, where it can be used as a medical indicator. This paper concerns analyzing HRV outside of controlled environments, such as on an actively moving person. We describe automated methods for inter-heartbeat interval (IBI) error detection and correction. We collected 124,998 IBIs from 18 subjects, undergoing a variety of active motions, for use in evaluating our methods. Two human graders manually labeled each IBI, evaluating 10IBIs as having an error, which is a far greater error percentage than has been examined in any previous study. Our automated method had a 96% agreement rate with the two human graders when they themselves agreed, with a 49% rate of matching specific error corrections and a 0.01% false alarm rate.

Control systems that utilize switched linear controllers have proven to be useful (and, in some cases, essential) for accomplishing certain control objectives in particular classes of plants. These controllers are often digital in nature and, as such, are subject to internal hardware malfunctions (faults). In this paper, we present a systematic methodology for constructing embeddings to protect switched linear controllers against hardware faults that corrupt their internal state. Our methodology is based on replacing the original controller with a redundant (higher dimensional) controller that preserves the functionality of the original controller while enabling error detection and correction. More importantly, this methodology allows an external mechanism to detect and identify transient state-transition faults through non-concurrent (e.g. periodic) parity checks. The resulting error detection and correction procedures can then be performed periodically, thereby relaxing the reliability requirements and overhead associated with the checking mechanism. ᭧

This paper describes the development of a VLSI device that provides memory system self-testing and redundancy without incurring the overhead penalties of error-correction coding or page-swapping techniques. This device isolates hard errors in system memory by writing a true and complement pattern to each system memory location. Locations from an on-chip fully associative cache are then mapped into the address space in place of faulty locations. Since substitutions take place at the memory word level, this method is more efficient than page swapping. Access to the on-chip cache occurs in parallel with access to system memory, so memory access time is not increased, as it is with error detection and correction (EDAC). Analysis shows that this device can extend the mission time of a nonredundant memory system by as much as 35 times. and digital design for radar signal processing systems. He is currently an Associate Department Head in MITRE'S VLSI/VHSIC

Timing error tolerance turns to be an important design parameter in nanometer technology, high speed and high complexity integrated circuits. In this work, we present a low cost, multiple timing error detection and correction technique, which is based on a new Flip-Flop design. The proposed design approach provides timing error tolerance at the small penalty of one clock cycle delay in the circuit operation for each error correction. In addition, it is characterized by very low silicon area requirements compared to previous design schemes in the open literature. The proposed technique has been applied in a 90nm pipeline design of a digital FIR filter and the simulation results validated its efficiency.

This paper proposes the Cross-Parity check as a method for an on-line detection of multiple bit-errors in registers or register files of microprocessors. Transient or 'soft' errors caused by radiation as single event upsets (SEUs) or electromagnetic coupling are in the focus of this work. Especially for register files or register groups, an easy implementable error correction method is proposed, which can be implemented by software routines or additional hardware. The method is based on the logical interpretation of Cross-Parity vectors.

We present a digital solution for the front-end electronics of high resolution calorimeters at future colliders. It is based on analogue signal compression, high speed A/D converters, a fully programmable pipeline and a digital signal processing (DSP) chain with local intelligence and system supervision. This digital solution is aimed at providing maximal front-end processing power by performing waveform analysis using DSP methods. For the system integration of the multichannel device a multi-chip, silicon-on-silicon multi-chip module (MCM) has been adopted. This solution allows a high level of integration of complex analogue and digital functions, with excellent flexibility in mixing technologies for the different functional blocks. This type of multichip integration provides a high degree of reliability and programmability at both the function and the system level, with the additional possibility of customising the microsystem to detector-specific requirements. For enhanced reliability in high radiation environments, fault tolerance strategies, i.e. redundancy, reconfigurability, majority voting and coding for error detection and correction, are integrated into the design.

The compact disc player is a synergy of optics, communication theory, digital signal processing, and control engineering. This familiar consumer product may be employed as a cost-effective laboratory instrument to teach the fundamentals of optical storage, error detection and correction, and optical communication. The compact disc audio system, from analog input, through optical storage and distribution, to audio reproduction, provides an excellent model of a complete real-world optical transmission and storage system. A series of experiments, which illustrate some of the more significant operational principles of the compact disc player, are presented in this contribution. Optical read-out and the physics of information density are explored through a set of experiments in optical storage. Error detection and correction are studied experimentally by evaluating the performance of the compact disc player's error control system. The design of an optical fiber communication system is studied by extracting the channel bit stream from a compact disc player, transmitting it over an optical fiber link, and then reinserting it back into the compact disc player for audio reproduction.

Finding the available empty space for arrival tasks on FPGAs with runtime partially reconfigurable abilities is the most time consuming phase in on-line placement algorithms. Naturally, this phase has the highest impact on the overall system performance. In this paper, we present a new algorithm which is used to find the complete set of maximum free rectangles on the FPGA at runtime. During scanning, our algorithm relies on dynamic information about the edges of all already placed tasks. Simulation results show that our algorithm has 1.5x to 5x speedup compared to state of the art algorithms aiming at maximum free rectangles. In addition, our proposal requires at least 4.4x less scanning load.