Specificity of autoimmune monoclonal Fab fragments binding to single-stranded deoxyribonucleic acid
Biochemistry, 1982
Fab fragments from hybridoma HEd 10 [Lee, J. S., Lewis, J.R., Morgan, A.R., Mosmann, T.R., &a... more Fab fragments from hybridoma HEd 10 [Lee, J. S., Lewis, J.R., Morgan, A.R., Mosmann, T.R., & Singh, B. (1981) Nucleic Acids Res. 9, 1707-1721] were prepared in large amounts by papain digestion of the immunoglobulin G (IgG) fraction from ascites fluid. Binding data were generated by a fluorescence quenching technique, and binding constants [K(0)] were estimated from Scatchard plots. The Fab fragments bound tightly to poly(dT) [K(0) = 12.7 X 10(6) M-1], and analysis of binding constants for the series p(dT)2 to p(dT)17 showed that the recognition sequence consisted of four consecutive residues. The effect of ionic strength on the interaction suggested that only two phosphates were involved. Binding constants for poly(dU), poly[d(brU)], poly[d(brC)], and poly(rU) were 1.0 X 10(6) M-1, 18.8 X 10(6) M-1, 0.5 X 10(6) M-1, and less than 0.5 X 10(6) M-1, respectively, implicating the involvement of the 3, 4, and 5 positions of the pyrimidine ring as well as the deoxyribose sugar in the recognition process. At high ionic strength (0.5 M) K(0) for whole IgG binding to poly(dT) was 75 X 10(6) M-1 compared to a value of 1.1 X 10(6) M-1 for the Fab fragment. These results may have implications for the tissue damage caused by DNA-containing immune complexes in systemic lupus erythematosus.
Coralyne is a DNA-binding antitumor antibiotic whose structure contains four fused aromatic rings... more Coralyne is a DNA-binding antitumor antibiotic whose structure contains four fused aromatic rings. The interaction of coralyne with the DNA triplexes poly(dT)*poly(dA)-poly(dT) and poly [d(TC)] -poly-[d(GA)]-poly[d(C+T)] was investigated by using three techniques. First, T m values were measured by thermal denaturation analysis. Upon binding coralyne, both triplexes showed T m values that were increased more than those of the corresponding duplexes. A related drug, berberinium, in which one of the aromatic rings is partially saturated, gave much smaller changes in Tm. Second, the fluorescence of coralyne is quenched in the presence of DNA, allowing the measurement of binding parameters by Scatchard analysis. The binding isotherms were biphasic, which was interpreted in terms of strong intercalative binding and much weaker stacking interactions. In the presence of 2 mM Mg2+, the binding constants to poly(dT)-poly-(dA)-poly(dT) and poly[d(TC)]-poly[d(GA)]*poly[d(C+T)] were 3.5 X IO6 M-l and 1.5 X lo6 M-I, respectively, while the affinity to the parent duplexes was at least 2 orders of magnitude lower. In the absence of 2 mM Mg2+, the binding constants to poly[d(TC)]*poly[d(GA)]*poly[d(C+T) J and poly-[d(TC)]*poly[d(GA)]
Scan test has been a common and useful method for testing VLSI designs due to the high controllab... more Scan test has been a common and useful method for testing VLSI designs due to the high controllability and observability it provides. These same properties have recently been shown to also be a security threat to the intellectual property on a chip . In order to defend from scan based attacks, we present the Lock & Key technique. Our proposed technique provides security while not negatively impacting the design's fault coverage. This technique requires only that a small area overhead penalty is incurred for a significant return in security. Lock & Key divides the already present scan chain into smaller subchains of equal length that are controlled by an internal test security controller. When a malicious user attempts to manipulate the scan chain, the test security controller goes into insecure mode and enables each subchain in an unpredictable sequence making controllability and observability of the circuit under test very difficult. We will present and analyze the design of the Lock & Key technique to show that this is a flexible option to secure scan designs for various levels of security.
Market and customer demands have continued to push the limits of CMOS performance. At-speed test ... more Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shipped to the customers fault-free. However, at-speed tests have been known to create higher-than-average switching activity, which normally is not accounted for in the design of the power supply network. This potentially creates conditions for additional delay in the chip; causing it to fail during test. In this paper, we propose a pattern compaction technique that considers the layout and gate distribution when generating transition delay fault patterns. The technique focuses on evenly distributing switching activity generated by the patterns across the layout rather than allowing high switching activity to occur in a small area in the chip that could occur with conventional delay fault pattern generation. Due to the relationship between switching activity and IR-drop, the reduction of switching will prevent large IR-drop in high demand regions while still allowing a suitable amount of switching to occur elsewhere on the chip to prevent fault coverage loss. This even distribution of switching on the chip will also result in avoiding hot-spots.
Scan designs used for testing also provide an easily accessible port for hacking. In this paper, ... more Scan designs used for testing also provide an easily accessible port for hacking. In this paper, we present a new lowcost secure scan design that is effective against scan-based sidechannel attacks. By integrating a test key into test vectors that are scanned into the chip, testing and accessing scan chains are guaranteed to be allowed only by an authorized user. Any attempt to use the scan chain without a verified test vector will result in a randomized output preventing potential side-channel attacks. The proposed technique has a negligible area overhead, has no negative impact on chip performance, and places several levels of security over the scan chain protecting it from potential attacks.
IEEE Transactions on Dependable and Secure Computing, 2007
Traditionally, the only standard method of testing that has consistently provided high fault cove... more Traditionally, the only standard method of testing that has consistently provided high fault coverage has been scan test due to the high controllability and high observability this technique provides. The scan chains used in scan test not only allow test engineers to control and observe a chip, but these properties also allow the scan architecture to be used as a means to breach chip security. In this paper, we propose a technique, called Lock & Key, to neutralize the potential for scan-based side-channel attacks. It is very difficult to implement an all inclusive security strategy, but by knowing the attacker, a suitable strategy can be devised. The Lock & Key technique provides a flexible security strategy to modern designs without significant changes to scan test practices. Using this technique, the scan chains are divided into smaller subchains. With the inclusion of a test security controller, access to subchains are randomized when being accessed by an unauthorized user. Random access reduces repeatability and predictability making reverse engineering more difficult. Without proper authorization, an attacker would need to unveil several layers of security before gaining proper access to the scan chain in order to exploit it. The proposed Lock & Key technique is design independent while maintaining a relatively low area overhead.
As technology scales, gate sensitivity to noise increases due to supply voltage scaling and limit... more As technology scales, gate sensitivity to noise increases due to supply voltage scaling and limited scaling of the voltage threshold. As a result, power supply noise plays a greater role in sub-100nm technologies and creates signal integrity issues in the chip. It is vital to consider supply voltage noise effects (i) during design validation to apply sufficient guardbands to critical paths and (ii) during path delay test to ensure the performance and reliability of the chip. In this paper, a novel layout-aware pattern generation procedure for maximizing power supply noise effects on critical paths while considering local voltage drop impacts is proposed. The proposed pattern generation and validation flow is implemented on the ITC'99 b19 benchmark. Experimental results for both wire-bond and flip-chip packaging styles are presented in this paper. Results demonstrate that our proposed method is fast, significantly increases switching around the functionally testable critical paths, and induces large voltage drop on cells placed in the critical paths which results in increased path delay. The proposed method eliminates the very time consuming pattern validation phase that is practiced in industry.
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