CANDIDATE TO 2019 IEEE PRESIDENT-ELECT (2020 IEEE PRESIDENT)
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Papers by Vincenzo Piuri
A unified view of CORDIC processor design
Midwest Symposium on Circuits and Systems, 1996
CORDIC processors are powerful computing systems for applications involving large amount of rotat... more CORDIC processors are powerful computing systems for applications involving large amount of rotation operations or for evaluating several elementary functions. In this paper, a unified view of the different architectures proposed in literatures is presented. The goal is to provide a wide spectrum of architectures, a coordinated and comprehensive design methodology, and the main figures of merit characterizing architectures' performance
IEEE International Workshop on Haptic, Audio and Visual Environments and Their Applications, 2002
A procedure for 3D surface reconstruction from range data in strict real-time is presented. The p... more A procedure for 3D surface reconstruction from range data in strict real-time is presented. The process is based on a connectionist model, the hierarchical radial basis function (HRBF) network, which has been proved to be effective in the reconstruction of smooth, space varying surfaces. An efficient data structure and locality assumptions allowed the derivation of a faster configuration algorithm, without
Sensitivity to errors in artificial neural networks: a behavioral approach
Abstract The problem of sensitivity to errors in artificial neural networks is discussed here con... more Abstract The problem of sensitivity to errors in artificial neural networks is discussed here considering an abstract model of the network and the errors that can affect a neuron's computation. Feed-forward multilayered networks are considered; the performance taken ...
Diagnosis is a basic issue of any fault-tolerance policy. Fault localization within the neural ar... more Diagnosis is a basic issue of any fault-tolerance policy. Fault localization within the neural architecture is necessary to provide information for hardware reconÿguration in order to achieve system survival, possibly with reduced computational capabilities. In this paper, a comprehensive approach to architectural fault-tolerant design of neural networks is proposed and evaluated, with speciÿc reference to concurrent high-level diagnosis and fault localization. The approach refers to the operational life of trained neural networks. Two error detection techniques are applied: on-line concurrent diagnosis with the use of data coding for error detection at neuron level and on-line compact testing for localization of the faulty neuron within the network.
A computational intelligence approach to solar panel modelling
2014 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings, 2014
ABSTRACT The power produced by a solar panel depends on several parameters. In order to optimize ... more ABSTRACT The power produced by a solar panel depends on several parameters. In order to optimize the production, the ability to operate in the Maximum Power Point (MPP) condition is requested. The ability to identify and reach the MPP condition is therefore critical to an efficient conversion of the photovoltaic energy. In this paper, several computational intelligence paradigms are challenged in the task of identifying the MPP power from the working condition directly measurable from the solar panel, such as the voltage, V, the current, I, and the temperature, T, of the panel.
Proceedings of 1995 IEEE Instrumentation and Measurement Technology Conference - IMTC '95, 1995
In this paper we prove the effectiveness of using neural networks of regression type to identify ... more In this paper we prove the effectiveness of using neural networks of regression type to identify time series and non linear dynamic systems. It is experimentally shown that, whenever the process generating the data is ruled by a linear model (such as an ARMA for time series), performances provided by the neural network are comparable with the optimal predictor given by the Kolmogorov-Wiener theory. On the other hand, performances outcome classical linear identification approaches when the system to be modelled is intrinsically non-linear. The work extends the one suggested by Narendra et Al. in [7] by considering a reduced set of training data and a blackbox model for the system to be identified.
Proceedings of ISCAS'95 - International Symposium on Circuits and Systems, 1995
The use of neural networks in mission-critical applications requires concurrent error detection a... more The use of neural networks in mission-critical applications requires concurrent error detection and correction at architectural level to provide high consistency and reliability of system outputs. Time redundancy allows for fault tolerance in digital realizations with low circuit complexity increase when timing constraints are not particularly strict: the use of time redundancy implemented via operand rotation is discussed in this paper.
The Kluwer International Series in Engineering and Computer Science, 1996
Page 1. A UNIFIED VIEW OF CORDIC PROCESSOR DESIGN 3 Shaoyun Wang , Vincenzo Piuri , and Earl E. S... more Page 1. A UNIFIED VIEW OF CORDIC PROCESSOR DESIGN 3 Shaoyun Wang , Vincenzo Piuri , and Earl E. Swartzlander, Jr. Crystal Semiconductor Corporation, 4210 S. Industrial Dr., Austin, TX 78744, USA. ... piuri@elet.polimi.ite.swartzlander@compmail.com 2 3 ...
IPSec is a suite of protocols that adds security to communications at the IP level. This suite of... more IPSec is a suite of protocols that adds security to communications at the IP level. This suite of protocols is becoming more and more important as it is included as mandatory security mechanism in IPv6. In this paper we provide an evaluation of the hardware resources needed for supporting virtual private networking through IPSec. The target system of this study is a home secure gateway, therefore only the tunnel mode is considered. Focus is on ESP protocol, but also some evaluations on AH are provided. We discuss usage of the AES, HMAC-SHA-1, and HMAC-SHA-2 cryptographic algorithms. In this paper we show that enabling IPSec in a 100Mbit/s network kills its performance in almost every case. In a 10Mbit/s network the results obtained for performance and CPU usage are much better. An interesting case within this network configuration is that in which IPComp is enabled and used on compressible data: CPU usage grows to 100%, but network throughput rises over the 10Mbit/s limit, due to data compression. This performance evaluation leads the conclusion that while a hardware crypto-accelerator is really key in reaching high performance, it may also be useful in small, slow systems (e.g. small embedded systems) where it would help improving performance and security.
Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002, 2002
Spectral warping is a technique that transforms a digital signal in the time domain by a warping ... more Spectral warping is a technique that transforms a digital signal in the time domain by a warping of the frequency axis in its frequency representation. This corresponds to a mapping of the samples in the z-domain such that they are unevenly spaced around the unit circle. Spectral warping can be implemented with a network of linear all-pass filters. The Spectral Warping has a property that a time-shifted impulse function is transformed into a chirp function. This has useful applications in the electronic testing of mixed-signal (analog-digital) circuits. The properties of the spectral warping network, generation of the chirp signals, and their applications are discussed in the paper.
2006 IEEE Symposium on Virtual Environments, Human-Computer Interfaces and Measurement Systems, 2006
Grid computing systems are emerging as a consequence of the growing internet connectivity in comb... more Grid computing systems are emerging as a consequence of the growing internet connectivity in combination with the need of shared resources to deploy large-scale scientific applications. In such a context, heterogeneity, decentralization, location, access and availability of resources need to be dealt with suitable simulation tools. In particular, overloading conditions may be critical and difficult to analyse when the grid is requested to guarantee affordable high performances. To deal with such a challenging task, a virtual simulation environment provided with a suitable graphical interface has been developed as the means for comparative analysis with real test bed activities.
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Papers by Vincenzo Piuri