Compositional Modeling

We explore the meanings of the terms 'structure ', 'behaviour', and, especially, 'function' in engineering practice. Computers provide great assistance in calculation tasks in engineering practice, but they also have great potential for helping with reasoning tasks. However, realising this vision requires precision in representing engineering knowledge, in which the terms mentioned above play a central role. We start with a simple ontology for representing objects and causal interactions between objects. Using this ontology, we investigate a range of meanings for the terms of interest. Specifically, we distinguish between function as effect on the environment, and a device-centred view of device function. In the former view, function is seen as an intended or desired role that an artifact plays in its environment. We identify an important concept called mode of deployment that is often left implicit, but whose explicit representation is necessary for correct and complete reasoning. We discuss the task of design and design verification in this framework. We end with a discussion that relates needs in the world to functions of artifacts created to satisfy the needs.

Unsaturated, nitrogenated and sulfured compounds may reach undesirable levels in lubricant base oils, requiring hydrotreatment (HDT) at high temperatures and pressures. HDT processes are well known for their high capital and operational costs due to the use of hydrogen, compressors and multistage heterogeneous reactors. Process costs are thus highly dependent on the applied conditions. An oversized process entails unnecessary costs and capital investment. On the other hand, mild reaction conditions lead to unspecified products. This work analyzes the process using a compositional modeling and a kinetic framework developed previously (Barbosa et al., 2002) for the HDT of lubricant base oils. The industrial reactor is rigorously modeled on an adiabatic and multistage configuration. For the remaining equipment in the flowsheet, we adopt shortcut models for compressors and exchangers. The process is then optimized in terms of its variables subject to product specification constraints.

Unsaturated, nitrogenated and sulfured compounds may reach undesirable levels in lubricant base oils, requiring hydrotreatment (HDT) at high temperatures and pressures. HDT processes are well known for their high capital and operational costs due to the use of hydrogen, compressors and multistage heterogeneous reactors. Process costs are thus highly dependent on the applied conditions. An oversized process entails unnecessary costs and capital investment. On the other hand, mild reaction conditions lead to unspecified products. This work analyzes the process using a compositional modeling and a kinetic framework developed previously (Barbosa et al., 2002) for the HDT of lubricant base oils. The industrial reactor is rigorously modeled on an adiabatic and multistage configuration. For the remaining equipment in the flowsheet, we adopt shortcut models for compressors and exchangers. The process is then optimized in terms of its variables subject to product specification constraints.

Les systèmes embarqués critiques (utilisés dans le domaine avionique, militaire ou médical) doivent assurer une continuité de service et la sécurité des données qu'ils contiennent ou échangent. La garantie de ces exigences s'effectue au travers d'un processus de développement rigoureux qui s'attache à détecter et corriger toute erreur avant la mise en production du système. Toutefois, plusieurs exemples (explosion de la fusée Ariane 5, échec de la mission Mars Climate Orbiter} ont montré les limites de ces méthodes. De plus, l'augmentation des fonctionnalités fournies par ces systèmes complique la garantie de règles de sécurité et de sûreté. Ce travail de thèse propose une méthode de conception de systèmes critiques visant à faciliter le respect des politiques de sécurité et de sûreté dans la production de systèmes critiques. L'approche décrite au sein de ce manuscrit définit des règles de spécifications des systèmes sûrs et sécurisés qui sont utilisés au cou...

march 30th.] 2.4. Highlights The main headline of 2010 is the delivery of the Polychrony toolset in open-source under GPL and EPL licenses. It is the result of a process initiated early this year and conducted in close collaboration with INRIA's DTI in order to precisely identify the perimeter of the license and identify the best-suited licensing terms compatible with its users and potential contributors. Our second headline is the publication of a book on the "Synthesis of embedded software" with Springer, coedited by Sandeep Shukla and Jean-Pierre Talpin. The publication of this book is consecutive to organization of a one-day tutorial at the Design Automation and Test in Europe (DATE) 2009 Conference on "Correct-by-Construction Embedded Software Synthesis: Formal Frameworks, Methodologies, and Tools", in 2009.

Nous présentons une expérience appliquant l'ingénierie dirigée par les modèles à l'analyse et à la mise en oeuvre d'une chaîne complète de gestion de dépêches d'agence traitant de manifestations dans les domaines de la culture et des loisirs. La prise en compte d'événements, structurellement complexes, porteurs d'information spatiale et surtout temporelle, associée à la nécessité de gérer l'interopérabilité d'applications hétérogènes, justifient pleinement le recours à l'IDM. Nous donnons une vue d'ensemble de notre démarche et présentons les métamodèles utilisés, notamment le modèle d'événements servant de pivot entre l'interface avec les applications de traitement de la langue naturelle en amont et les environnements de visualisation d'information temporelle du côté de l'utilisateur final. ABSTRACT. This paper presents an application of Model Driven Engineering to the design of a complete news processing line within the scope of culture and leisure information. MDE is the only technology actually enabling to master the management of complex composite events with spatial and temporal properties, and to cope with making heterogeneous applications interoperate. We provide an overview of our approach and outline the salient points of our metamodels. The stress is put on the event metamodel, standing as a pivot between the beforehand Natural Language Processing, and temporal information visualization frameworks on the end user side.

Markovian performance models are impractical for large systems because their state space grows very rapidly with the system size. This paper derives an approximate Mean Value Analysis (AMVA) solution for Markov models that represent a composition of subsystems. The goal is robust scalable analytical approximation. The approach taken here is to create approximate aggregated Markov chain submodels, each representing a view of the Markov chain for the entire system from the perspective of a selected set D of tagged components, and to derive mean value equations from them. The analytic solutions of submodels are then combined using system-level relationships, which must be identified for each system; this is not automatic but is usually straightforward. The first point of novelty is the method used to create the aggregate submodels for different sets D, building up each submodel by composition of the components in D rather than by aggregating the entire state space. Another point of novelty is the use of partitioned Markov models to obtain analytic solutions.

In this paper, we discuss a synchronous, componentbased approach to the modeling of avionics applications. The specification of the components relies on the avionics standard ARINC 653 and the synchronous language SIGNAL is considered as modeling formalism. The POLY-CHRONY tool-set allows for a seamless design process based on the SIGNAL model, which provides possibilities of high level specifications, verification and analysis of the specifications at very early stages of the design, and finally automatic code generation through formal transformations of these specifications. This suits the basic stringent requirements that should be met by any design environment for embedded applications in general, and avionics applications in particular.

High-level architecture modeling languages, such as Architecture Analysis & Design Language (AADL), are gradually adopted in the design of embedded systems so that design choice verification, architecture exploration, and system property checking are carried out as early as possible. This paper presents our recent contributions to cope with clock-based timing analysis and validation of software architectures specified in AADL. In order to avoid semantics ambiguities of AADL, we mainly consider the AADL features related to real-time and logical time properties. We endue them with a semantics in the polychronous model of computation; this semantics is quickly reviewed. The semantics enables timing analysis, formal verification and simulation. In addition, thread-level scheduling, based on affine clock relations is also briefly presented here. A tutorial avionic case study, provided by C-S, has been adopted to illustrate our overall contribution.

Concevoir un système embarqué implique de trouver un compromis algorithme/architecture en fonction des contraintes temps-réel. Thèse : pour un MPSoC et plus particulièrement avec les circuits reconfigurables qui permettent de modifier le support d'exécution en cours de fonctionnement, l'évaluation préalable des comportements fluctuants d'un système réactif devient une nécessité. Il faut donc valider par simulation (de haut niveau) tout en permettant l'exploration de l'espace de conception architectural, matériel et logiciel. Le point de vue du gestionnaire de la plateforme est choisi pour explorer à haut niveau les réactions du système aux choix de partitionnement et surtout l'influence de l'algorithmique des services du système d'exploitation et de leurs implémentations possibles. Pour cela un modèle de services d'OS modulaire permet de simuler fonctionnellement et conjointement, en SystemC, le matériel, les tâches logicielles et le système d&#39...

The aim of studying musical modeling and "borrowing" between a composer such as Schumann and Beethoven is to explore how common and how conscious such practices were, and to explain the function and meaning of different kinds of borrowing. Quotations, allusions, and structural modelings may differ from each other in terms of function or content, or in terms of relative fidelity of the later work to the model. And yet they may also have much in common: the symbolic function of a quotation within a new musical context may be similar to that of an allusion, and, I argue, a composer could adapt either a quotation or an allusion to a new context in ways also evident in a composer's adaptation of an earlier formal plan in a structural modeling. The primary focus in this study is on the motivic debts and influences of Beethoven's opera Fidelio, an opera that has long attracted opinions about its musical influence. Passages from Fidelio that provided later composers with musical-textual symbols have received comparatively less attention. I propose several instance in which Schubert, Schumann and Brahms derived inspiration from Beethoven's opera.

AADL (Architecture Analysis & Design Language) has been increasingly adopted in the design of embedded systems, and corresponding scheduling and formal verification have been well studied. However, little work takes code distribution and architecture exploration into account, particularly considering clock constraints, for distributed multi-processor systems. In this paper, we present an overview of our approach to handle these concerns, together with the associated toolchain, AADL-P-SDE. First, in order to avoid semantic ambiguities of AADL, the polychronous/multiclock semantics of AADL, based on a polychronous model of computation, is considered. Clock synthesis is then carried out in P, which bridges the gap between the polychronous semantics and the synchronous semantics of SDE. The same timing semantics is always preserved in order to ensure the correctness of the transformations between different formalisms. Code distribution and corresponding schedulin...

The Modeling paradigm for Integrated Modular Avionics Design (Mimad) is an extensible component-oriented framework that enables high level models of systems designed on integrated modular avionics architectures. It relies on the generic modeling environment (Gme), a configurable object-oriented toolkit that supports the creation of domain-specific modeling and program synthesis environments. Mimad is built upon component models dedicated to avionic applications design, which are defined within the Polychrony platform. Hence, its descriptions can be transformed into Polychrony's models in order to access the available formal tools and techniques for validation. Users do not need to be experts of formal methods (in particular, of the synchronous approach) to be able to manipulate the proposed concepts. This contributes to satisfying the present industrial demand on the use of general-purpose modeling formalisms for system design. This paper first presents the main features of Mimad V0. Then, it illustrates the use of the paradigm to design a simple application example within Gme.

High-level modelling languages and standards, such as Simulink, UML, SysML, MARTE and AADL (Architecture Analysis & Design Language), meet increasing adoption in the design of embedded systems in order to carry out system-level analysis, verification and validation (V&V) and architecture exploration, as early as possible. These analysis, V&V, architecture exploration techniques rely on mathematical foundations and formal methods in order to avoid semantics ambiguities in the design of safety-critical systems. In order to support integration validation, it is necessary to define a formal framework of virtual prototyping to integrate, verify, exercise and analyse the application code generated by modelling tools as early as possible and virtually integrate it with simulators of third-party middleware and hardware. Such a virtual prototyping platform makes it possible to validate the expected behaviour of the final application software and check that the resulting system indeed meets the specified performance requirements before the actual hardware even actually exists. In this paper, we present the definition, development and case-study validation of such a comprehensive framework, based on the synchronous paradigm and the polychronous model of computation and communication of its supportive open-source toolset: Polychrony. A longer-term aim of our work is to equip the AADL standard with an architecturecentric framework allowing for synchronous modelling, verification and synthesis of embedded software.

The increasing system complexity and time to market constraints are great challenges in current electronic system design. Raising the level of abstraction in the design and performing fast yet efficient high-level analysis, validation and synthesis has been widely advocated and considered as a promising solution. Motivated by the same approach, our work on system-level synthesis is presented in this paper: use the high-level modeling, domain-specific, language AADL for systemlevel co-design; use the formal framework Polychrony, based on the synchronous language SIGNAL, for analysis, validation and synthesis. According to SIGNAL's polychronous model of computation, we propose a model for AADL, which takes both software, hardware and allocation into account. This model enables an early phase timing analysis and synthesis via tools associated with Polychrony.

High-level modeling languages and standards, such as Simulink, SysML, MARTE and AADL (Architecture Analysis & Design Language), are increasingly adopted in the design of embedded systems so that system-level analysis, verification and validation (V&V) and architecture exploration are carried out as early as possible. This paper presents our main contribution in this aim by considering embedded systems architectural modeling in AADL and functional modeling in Simulink; an original clock-based timing analysis and validation of the overall system is achieved via a formal polychronous/multi-clock model of computation. In order to avoid semantics ambiguities of AADL and Simulink, their features related to real-time and logical time properties are first studied. We then endue them with a semantics in the polychronous model of computation. We use this model of computation to jointly analyze the non-functional real-time and logical-time properties of the system (by means of logical and affine clock relations). Our approach demonstrates, through several case-studies conducted with Airbus and C-S Toulouse in the European projects CESAR and OPEES, how to cope with the system-level timing verification and validation of high-level AADL and Simulink components in the framework of Polychrony, a synchronous modeling framework dedicated to the design of safety-critical embedded systems.

Embedded real-time systems consist of hardware and software that controls the behavior of a device or plant. They are ubiquitous in today's technological landscape and found in domains such as telecommunications, nuclear power, avionics, and medical technology. These systems are difficult to design and build because they must satisfy both functional and timing requirements to work correctly in their intended environment. Furthermore, embedded systems are often critical systems, where failure can lead to loss of life, loss of mission, or serious financial consequences. Because of the difficulty in creating these systems and the consequences of failure, they require rigorous and reliable design approaches. The synchronous approach is one possible answer to this demand. Its mathematical basis provides formal concepts that favor the trusted design of embedded real-time systems. The multiclock or polychronous model stands out from other synchronous specification models by its capabil...

George Gershwin greatly admired Alban Berg and his opera Wozzeck. He visited Berg in Vienna; the score he owned of Wozzeck was reputedly one of his prize possessions; and he traveled to Philadelphia in 1931 to attend the American premiere. This study argues that Gershwin's Porgy and Bess is heavily indebted to Berg's Wozzeck. The debts primarily involve structural processes-understanding structure as patterns of discrete events shared by the two operas. Motives and chords play a small role in the discussion, taking their place alongside musical events that range from the large-a fugue or a lullaby-to the small-a pedal, an ostinato, or some detail of counterpoint. Beyond the presence in both operas of a lullaby, a fugue, a mock sermon, and an upright piano, the greater relevance of these parallels and others is to be found in the ways in which Gershwin situated them in comparable musical contexts. Evidence, in the form of an overlooked interview and a previously unknown recollection by one of Gershwin's friends, supports this argument and leads to questions about how we are to understand Gershwin's use of Wozzeck.

Winner of the H. Colin Slim Award from the AMS, and of the Kurt Weill Prize from the Kurt Weill Foundation (for outstanding article on music theatre since 1900).

Using Government drawings, specifications, or other data included in this document for any purpose other than Government procurement does not in any way obligate the U.S. Government. The fact that the Government formulated or supplied the drawings, specifications, or other data does not license the holder or any other person or corporation; or convey any rights or permission to manufacture, use, or sell any patented invention that may relate to them. This report is the result of contracted fundamental research deemed exempt from public affairs security and policy review in accordance with SAF/AQR memorandum dated 10 Dec 08 and AFRL/CA policy clarification memorandum dated 16 Jan 09. This report is available to the general public, including foreign nationals. Copies may be obtained from the Defense Technical Information Center (DTIC) (http://www.dtic.mil).

OATAO is an open access repository that collects the work of Toulouse researchers and makes it freely available over the web where possible. This is an author-deposited version published in : http://oatao.univ-toulouse.fr/ Eprints ID : 17057 The contribution was presented at AFADL 2016 : Résumé Nous présentons une méthodologie basée sur le raffinement manuel et automatique pour le développement d'applications distribuées correctes par construction. À partir d'un modèle Event-B, le processus étudié définit des étapes successives pour décomposer et ordonnancer les calculs associés aux événements et distribuer le code sur des composants. La spécification de ces deux étapes est faite au travers de deux langages dédiés. Enfin, une implan-tation distribuée en BIP est générée. La correction du processus repose sur la correction des raffinements et de la traduction vers le code cible BIP.

Résumé. Dans un travail antérieur, nous avons proposé une annexe comportementale ABAReL (AADL Behavioral Annex based on generalized Rewriting Logic), basée sur la logique de réécriture révisée, décrivant le composant "thread AADL" tout en préservant sa syntaxe initiale. Un modèle mathématique représenté par une théorie de réécriture décrivant son comportement simplifié, a été alors validé et implémenté sous l'environnement Maude. L'objectif de cet article est de raffiner l'annexe ABAReL et l'enrichir par d'autres constructions formelles de la logique de réécriture, à travers une extension de son langage Maude qui est RT-Maude (Real Time Maude). Cet enrichissement permettra de décrire les modes et les propriétés relatives au temps d'exécution théorique (la période, la politique d’expédition, etc.), déclarées dans le composant thread et leur prise en compte lors de son exécution. L'approche de formalisation proposée offre un cadre sémantique génér...

Ce travail porte sur le test fonctionnel, base sur les specifications et completement automatise des logiciels synchrones. Nous proposons une extension des techniques de test proposees par l'outil Lutess afin de prendre en compte des logiciels qui comportent des entrees/sorties numeriques. La generation de donnees de test est abordee en s'appuyant sur les techniques de programmation par contraintes. Nous avons redefini les methodes de guidage de la generation afin de les adapter a ce nouveau contexte numerique. Ainsi, nous proposons, en plus de la generation aleatoire respectant les proprietes invariantes de l'environnement, le guidage du test base sur des probabilites conditionnelles ou sur des proprietes de surete. Des connaissances partielles sur le logiciel, que nous appelons hypotheses de test, peuvent etre integrees dans le processus de generation et contribuer a l'amelioration du pouvoir de detection de fautes du guidage par proprietes de surete. Enfin, nous p...

Resume-Nous presentons dans ce travail une approche automatique de haut niveau pour l’analyse de code de la cospecification java, et pour la description des composants qui composent l’architecture cible sur laquelle l’application s’execute dessus. Dans ce contexte, nous avons developpe deux outils pour extraire toutes les informations pertinentes concernant les entites materielles et logicielles. Ces informations sont utilisees pour alimenter les etapes suivantes du processus de conception des systemes mixtes tels que le partitionnement et la cosynthese des interfaces de communication.

Concevoir un systeme embarque implique de trouver un compromis algorithme/architecture en fonction des contraintes temps-reel. These : pour concevoir un MPSoC et plus particulierement avec les circuits reconfigurables modifiant le support d'execution en cours de fonctionnement, la necessaire validation des comportements fluctuants d'un systeme reactif impose une evaluation prealable que l'on peut realiser par simulation (de haut niveau) tout en permettant l'exploration de l'espace de conception architectural, materiel mais aussi logiciel, au plus tot dans le flot de conception. Le point de vue du gestionnaire de la plateforme est adopte pour explorer a haut niveau les reactions du systeme aux choix de partitionnement impactes par l'algorithmique des services du systeme d'exploitation et leurs implementations possibles. Pour cela un modele modulaire de services d'OS simule fonctionnellement et conjointement en SystemC le materiel, les tâches logicielle...

Les applications temps-réel de traitement du signal et d'images ont des contraintes de temps très importantes, nécessitant l'utilisation de plusieurs unités de calcul puissantes. Le but de nos travaux est de développer un processus de prototypage rapide dédié aux architectures parallèles constituées de plusieurs processeurs de traitement numérique du signal de dernière génération. Nous utilisons pour cela SynDEx, l'outil basé sur la méthodologie AAA 1 , pour améliorer l'implantation de l'algorithme sur une architecture multiprocesseurs. Nous avons donc développé un noyau d'exécutif SynDEx pour la famille de DSP C6x, afin de générer automatiquement un exécutif statique, distribué et optimisé de l'algorithme spécifié sur ces processeurs.

Model-Based Engineering (MBE) is a promising approach to cope with the challenges of designing the next-generation automotive systems. The increasing complexity of automotive electronics, the platform, distributed real-time embedded software, and the need for continuous evolution from one generation to the next has necessitated highly productive design approaches. However, heterogeneity, interoperability, and the lack of formal semantic underpinning in modeling, integration, validation and optimization make design automation a big challenge, which becomes a hindrance to the wider application of MBE in the industry. This paper briefly presents the interoperability challenges in the context of MBE and summarizes our current contribution to address these challenges with regard to automotive software control systems. A novel model-based formal integration framework is being developed to enable architecture modeling, timing specification, formal semantics, design by contract and optimization in the system-level design. The main advantages of the proposed approach include its pervasive use of formal methods, architecture analysis and design language (AADL) and associated tools, a novel timing annex for AADL with an expressive timing relationship language, a formal contract language to express component-level requirements and validation of component integration, and the resulting high assurance system delivery.

In this paper, we use the UML MARTE profile to model high-performance embedded systems (HPES) in the Gaspard2 framework. We address the design correctness issue on the UML model by using the formal validation tools associated with synchronous languages, i.e., the Sigali model checker, etc. This modeling and validation approach benefits from the advantages of UML as a standard, and from the number of validation tools built around synchronous languages. In our context, model transformations act as a bridge between UML and the chosen validation technologies. They are implemented according to a model-driven engineering approach. The modeling and validation are illustrated using the multimedia functionality of a new-generation cellular phone.

Dans cet article, nous présentons un flôt MDE de conception de SoC (System-On-Chip) basé sur l'utilisation du profile UML MARTE (Modeling and Analysis of Real-Time Embedded Systems), dédié a la conception et l'analyse de système temps réel embarqués et récemment standardisé par l'OMG. Le flôt présenté adresse les problèmatiques de la communauté de l'ESL (Electronic System Level) et s'inscrit dans le cadre du projet MoPCoM (http ://www.mopcom.fr).

Current embedded systems are increasingly more complex and heterogeneous, but they are expected to be more safe, reliable and adaptive. In consideration of all these aspects, their design is always a great challenge. Developing these systems with conventional design approaches and programming methods turns out to be difficult. In this paper, we mainly present the informative background and the general idea of an ongoing yet young research project, including the modelbased design and an architecture-centric approach, to address previous challenges. Our idea adopts a formal-methods-based model integration approach, dedicated to architecture-centric virtual integration for embedded software systems, in an early design phase. We thus expect to improve and enhance Correct By Construction in the design. The considered formal methods consist of timing specification, design by contracts, and semantics interoperability for models to be integrated in the system. The application domains of our approach include automotive and avionic systems.

Ce travail porte sur le test fonctionnel, basé sur les spécifications et complètement automatisé des logiciels synchrones. Nous proposons une extension des techniques de test proposées par l'outil Lutess afin de prendre en compte des logiciels qui comportent des entrées/sorties numériques. La génération de données de test est abordée en s'appuyant sur les techniques de programmation par contraintes. Nous avons redéfini les méthodes de guidage de la génération afin de les adapter à ce nouveau contexte numérique. Ainsi, nous proposons, en plus de la génération aléatoire respectant les propriétés invariantes de l'environnement, le guidage du test basé sur des probabilités conditionnelles ou sur des propriétés de sûreté. Des connaissances partielles sur le logiciel, que nous appelons hypothèses de test, peuvent être intégrées dans le processus de génération et contribuer à l'amélioration du pouvoir de détection de fautes du guidage par propriétés de sûreté. Enfin, nous p...

Les nouveaux systemes monopuces deviennent de plus en plus complexe, et ceci est dûa la demande grandissante de puissance de calcul et de fonctionnalités. Par exemple, dans le monde de la téléphonie mobile, en quelques années les appareils téléphoniques portables sont passés du simple combiné permettant d'émettre et de recevoir des appels téléphoniquesa des mini-ordinateurs intégrant des caméras/appareils photos, des agendas, des navigateurs internet, des programmes de lecture de courrier électronique, des ...

Nous présentons les problématiques temps réel de l'accompagnement musical automatique vu comme un système réactif. Nous introduisons un modèle de datation prenant en compte les différentes échelles de temps spécifiques à la musique, et nous proposons plusieurs stratégies de synchronisation et de rattrapage d'erreurs effectivement utilisées dans diverses compositions musicales. ABSTRACT. We sketch the real-time features required by automatic musical accompaniment seen as a reactive system. We formalize the datation of musical event taking into account the various temporal scales used in music. Various strategies for the handling of synchronization constraints and the handling of errors are presented.

La modélisation des systèmes répartis et des systèmes électroniques modernes nécessite des référentiels temporels multiples. Nous désignons ces systèmes sous le nom de "systèmes polychrones". Le profil UML pour les systèmes temps réel et embarqués (MARTE) permet leur modélisation ainsi que la spécification de contraintes temporelles avec CCSL (Clock Constraint Specification Language). Dans MARTE, CCSL est non normatif et sa sémantique est informelle. Nous proposons ici une sémantique formelle en termes d'évolutions d'un "Time System" pour un noyau de CCSL. Un "Time System" est un modèle dynamique qui associe un ensemble de configurations à un modèle structurel constitué d'un ensemble d'horloges discrètes et de relations sur ces horloges. Les Time Systems sont comparés à d'autres modèles de causalités asynchrones, synchrones et polychrones. CCSL et sa mise en oeuvre sont illustrés sur un exemple de contrôleur d'ABS. ABSTRACT. "Polychronous systems" are systems referring to multiple, usually interdependent, time bases. The UML profile for real-time and embedded system (MARTE) can deal with such systems, and the Clock Constraint Specification Language (CCSL), part of MARTE, can be used to specify temporal constraints. In MARTE, the semantics of CCSL is informal. In this paper, we propose a formal semantics of a kernel of CCSL, in terms of "Time System" evolutions. A Time System is a dynamic model which associates a set of configurations with a structural model made of discrete clocks and relationships among these clocks. Time Systems are compared to other existing causality models. An ABS controller illustrates the use of CCSL. MOTS-CLÉS : modèle de temps, contraintes temporelles, parallélisme, polychronie

In this paper, we study the modular compilation of imperative synchronous programs. We rely on a formal framework well suited to perform compilation and formal validation of systems. In practice, we design and implement a special purpose language (LE) and its \execution equational semantics that allows the modular compilation of programs into software and hardware targets (C code, Vhdl code, FPGA synthesis, Verification tools). We show the correctness of this semantics, and we introduce a new algorithm to check program causality with respect to our modular approach. Relying in this formal approach, we defined a toolkit dedicated to the compilation and the verification of reactive applications.

We define the inductive process modeling task as the automated construction of quantitative process models from time series and background knowledge. In this task, the background knowledge comprises generic processes that along with a given set of entities define the space of candidate model structures. Typically this space grows exponentially with the size of the library, so past research introduced a hierarchical organization on the processes to constrain that space to a limited set of plausible configurations. However, organizing the processes into a hierarchy takes considerable effort, leads to implicit constraints, and creates a complex relationship between the knowledge of what processes exist and the knowledge of how one can combine them. To address these problems, we developed SC-IPM 1 , an inductive process modeler that uses declarative constraints to reduce the size of the model structure space. In this paper, we describe the constraint formalism and how it guides SC-IPM's search.

In previous publications, we have reported a computational approach to constructing quantitative process models of dynamic systems from time-series data and background knowledge. However, our experience with these systems suggests that process knowledge is insufficient to avoid the consideration of implausible models. To this end, we have identified and introduced constraints that specify which processes can or must occur together, which in turn limit search to candidates that scientists will consider acceptable. We have also developed methods for inducing such constraints from the results of search through the model space. We maintain that the ability to specify, utilize, and induce constraints on quantitative process models will support deeper understanding of complex systems and constitutes an important addition to eScience.

In this paper, we review the paradigm of inductive process modeling and examine its application to human physiology. This framework represents models as a set of interacting processes, each with associated differential or algebraic equations that express causal relations among variables. Simulating such a quantitative process model produces trajectories for variables over time that one can compare to observations. Background knowledge about candidate processes enables search through the space of model structures and their associated parameters, and thus identify quantitative models that explain time-series data. We present an initial process model for aspects of human physiology, consider its uses for health monitoring, and discuss the induction of such models. In closing, we consider related efforts on physiological modeling and our plans for collecting data to evaluate our framework in this domain.

Research on inductive process modeling combines background knowledge with time-series data to construct explanatory models, but previous work has placed few constraints on search through the model space. We present an extended formalism that organizes process knowledge in a hierarchical manner, and we describe HIPM, a system that carries out constrained search for hierarchical process models. We report experiments that suggest this approach produces more accurate and plausible models with less effort. We conclude by discussing related research and directions for future work.

Quantitative modeling plays a key role in the natural sciences, and systems that address the task of inductive process modeling can assist researchers in explaining their data. In the past, such systems have been limited to data sets that recorded change over time, but many interesting problems involve both spatial and temporal dynamics. To meet this challenge, we introduce SCISM, an integrated intelligent system which solves the task of inducing process models that account for spatial and temporal variation. We also integrate SCISM with a constraint learning method to reduce computation during induction. Applications to ecological modeling demonstrate that each system fares well on the task, but that the enhanced system does so much faster than the baseline version.

ABSTRACT In this paper, we introduce an approach for extracting constraints on process model construction. We begin by clarifying the type of knowledge produced by our method and how one may apply it. Next, we review the task of inductive process modeling, which provides ...

Abstract. In this paper, we introduce an inductive logic programming approach to learning declarative bias. The target learning task is in- ductive process modeling, which we briefly review. Next we discuss our approach to bias induction while emphasizing predicates that character- ize ...

People constantly apply acquired knowledge to new learning tasks, but machines almost never do. Research on transfer learning attempts to address this dissimilarity. Working within this area, we report on a procedure that learns and transfers constraints in the context of inductive process mod-eling, which we review. After discussing the role of constraints in model induction, we describe the learning method, MISC, and introduce our metrics for assessing the cost and benefit of transferred knowledge. The reported results suggest that cross-domain transfer is beneficial in the scenarios that we investigated, lending further evidence that this strategy is a broadly effective means for increasing the efficiency of learning systems. We conclude by discussing the aspects of inductive process modeling that encourage effective transfer, by reviewing related strategies, and by describing future research plans for constraint induction and transfer learning. Copyright {\textcopyright} 2010, Association for the Advancement of Artificial Intelligence (www.aaai.org). All rights reserved.

In this paper, we pose a novel research problem for machine learning that involves
constructing a process model from continuous data. We claim that casting learned
knowledge in terms of processes with associated equations is desirable for scientific and
engineering domains, where such notations are commonly used. We also argue that existing
induction methods are not well suited to this task, although some techniques hold partial
solutions. In response, we describe an approach to learning process models from time-series
data and illustrate its behavior in three domains. In closing, we describe open issues in
process model induction and encourage other researchers to tackle this important problem.

Nous présentons les problématiques temps réel de l'accompagnement musical automatique vu comme un système réactif. Nous introduisons un modèle de datation prenant en compte les différentes échelles de temps spécifiques à la musique, et nous proposons plusieurs stratégies de synchronisation et de rattrapage d'erreurs effectivement utilisées dans diverses compositions musicales.

RÉSUME : Cet article présente un prototype de langage de programmation de composants interfaçables. Nous y définissons les composants interfaçables comme des entités logicielles dotées de propriétés et assemblables entre elles, selon une logique "métier" mais qui en plus sont dotées de caractéristiques spécifiques permettant de les assembler de façon semi-automatique avec des composants d'interfaçage. Nous présentons un nouveau langage (ICL) permettant de développer de tels composants, de les assembler et de les interfacer avec le logiciel dédié T hings T M de la société Gatonero. L'article décrit ce langage, sa mise en oeuvre avec OpenJava et la connexion des programmes avec T hings T M .

Le développement d'applications critiques distribuées est un challenge difficile. Une panne du système peut causer d'importants dommages commme la perte de vies humaines ou l'échec de la mission. Par conséquent, de telles applications doivent être conçues et développées avec rigueur. La réduction des erreurs produites dans les différentes étapes du processus de développement est requise et nous pensons que la génération automatique d'applications est une solution naturelle. Pour faciliter le processus de vérification et de certification, l'utilisateur peut décrire les différents aspects de l'application à l'aide de langages de modélisation. Dans ce papier, nous présentons AADL comme langage de modélisation pour les applications Temps Réel Réparties Embarquées (TR 2 E). Puis nous présentons notre suite d'outils OCARINA permettant la génération automatique d'applications critiques à partir de modèle AADL. Finalement, nous présentons un cas d'étude et nos résultats obtenus.

The UML Profile for Modeling and Analysis of Real-Time and Embedded systems (MARTE) defines a mathematically expressive model of time, the Clock Constraint Specification Language (CCSL), to specify timed annotations on UML diagrams and thus provides them with formally defined timed interpretations. Thanks to its expressive capability, the CCSL allows for the specification of static and dynamic properties, of deterministic and non-deterministic behaviors, or of systems with multiple clock domains. Code generation from such multiclocked specifications (for the purpose of synthesizing a simulator, for instance) is known to be a difficult issue. We address it by using the approach of controller synthesis. In our framework, a timed CCSL specification is regarded as a property whose satisfaction should be enforced for any UML diagram carrying it as annotation. To do so, CCSL statements are first translated into dynamical polynomial systems. Such systems can be manipulated using the model-checker Sigali to synthesize an executable property (a controller) which enforces the satisfaction of the specified timing constraints on the UML diagram with which it is executed.

The increasing system complexity and time to market constraints are great challenges in current electronic system design. Raising the level of abstraction in the design and performing fast yet efficient high-level analysis, validation and synthesis has been widely advocated and considered as a promising solution. Motivated by the same approach, our work on system-level synthesis is presented in this paper: use the high-level modeling, domain-specific, language AADL for systemlevel co-design; use the formal framework Polychrony, based on the synchronous language SIGNAL, for analysis, validation and synthesis. According to SIGNAL's polychronous model of computation, we propose a model for AADL, which takes both software, hardware and allocation into account. This model enables an early phase timing analysis and synthesis via tools associated with Polychrony.