Analog macromodeling

L'industrie des semi-conducteurs continue ses progrès impressionnants dans la miniaturisation des circuits intégrés VLSI. Les concepteurs ont inventé des méthodes permettant d'exploiter la complexité croissante des circuits intégrés à haute densité d'intégration. L'une d'elles consiste à concevoir des systèmes embarqués sur puce (SoC) à l'aide de blocs pré-existants et déjà validés (appelés IP, comme Intellectual Property), qu'ils aient été élaborés en interne à l'entreprise réalisant l'intégration du SoC ou issus d'une tierce partie. Disposer d'une bibliothèque de blocs IP paramétrés selon leurs performances en temps, surface et consommation est une clef pour optimiser le système intégré vis à vis de l'application ciblée. S'il existe un flot standard bien établi pour concevoir les blocs intégrés numériques, reposant sur une méthode de conception descendante, la conception de circuits analogiques reste toujours une opération sur mesure. Alors que les systèmes intégrés sur puce sont souvent mixtes analogique-numérique, les méthodes de conception diffèrent complètement entre les deux mondes. Dans cette thèse, nous proposons une méthode pour automatiser le dimensionnement et la polarisation d'un circuit analogique dans le cas général, conduisant ainsi à une définition possible d'un IP analogique. Cette méthode permet de générer automatiquement une procédure pour calculer les dimensions d'une topologie électrique connue et son point de fonctionnement en se fondant sur l'expression de la connaissance du concepteur. Cette méthode permet de détecter des hypothèses conflictuelles émises par le concepteur et de traiter les cycles résultant des boucles de contre-réaction. Plusieurs circuits analogiques sont présentés pour illustrer la généralité et la précision de cette approche. IP analogique, circuits analogiques intégrés CMOS, synthèse hiérarchique basée sur la connaissance, point de polarisation, analyse des dépendances, détection des conflits, résolution de conflits.

In this paper we explore the potential of using a general class of functional representation techniques, kernel-based regression, in the nonlinear model reduction problem. The kernel-based viewpoint provides a convenient computational framework for regression, unifying and extending the previously proposed polynomial and piecewise-linear reduction methods. Furthermore, as many familiar methods for linear system manipulation can be leveraged in a nonlinear context, kernels provide insight into how new, more powerful, nonlinear modeling strategies can be constructed. We present an SVD-like technique for automatic compression of nonlinear models that allows systematic identification of model redundancies and rigorous control of approximation error.

We investigate the use of support vector machines (SVMs) to determine simpler and better fit power macromodels of functional units for high-level power estimation. The basic approach is first to obtain the power consumption of the module for a large number of points in the input signal space. Least-Squares SVMs are then used to compute the best model to fit this set of points. We have performed extensive experiments in order to determine the best parameters for the kernels. We propose a new method for power macromodeling of functional units for high-level power estimation based on Least-Squares Support Vector Machines (LS-SVM). Our method improves the already good modeling capabilities of the basic LS-SVM method in two ways. First, a modified norm is used that is able to take into account the weight of each input for global power consumption in the computation of the kernels. Second, an iterative method is proposed where new data-points are selectively added as support-vectors to increase the generalization of the model. The macromodels obtained compare favorably with those obtained using industry standard table models, providing not only excellent accuracy on average (close to 1% error), but more importantly, thanks to our proposed modified kernels, we were able to reduce the maximum error to values close to 10%.

The aim of this work was to elaborate two-dimensional behavioral modeling method of thick-film resistors working in low-temperature conditions. The investigated resistors (made from 5 various resistive inks: 10 resistor coupons, each with 36 resistors with various dimensions), were measured automatically in a cryostat system. The low temperature was achieved in a nitrogen-helium continuous-flow cryostat. For nitrogen used as a freezing liquid the minimal temperature possible to achieve was equal to −195.85 °C (77.3 K). Mathematical model in the form of a multiplication of two polynomials was elaborated based on the above mentioned measurements. The first polynomial approximated temperature behavior of the normalized resistance, while the second one described the dependence of resistance on planar resistors dimensions. Special computational procedures for multidimensional approximation purpose were elaborated. It was shown that proper approximation polynomials and sufficiently exact ...

This paper formulates a new modeling technique for the analog circuits like OPAMP (Operational Amplifier). One of the fastest learning techniques, extreme learning machine along with best suitable kernel Radial Basis Function has been implemented for modeling. The simulated result shows that the training speed is very high and can handle a large set of data without compromising accuracy.

This paper proposes performance based macro modeling of analog circuit using Multi Output Modeling (MOM) with the help of Support Vector Machine (SVM). SVM models the analog circuits and provides a relation between multi-input and multi-output parameters. In this work, Voltage Controlled Oscillator (VCO) is modeled as a test circuit which is designed in Cadence Virtuoso GPDK 45nm technology. From the Spice simulation results, the feasible dataset has been extracted from the complete dataset. Then, the VCO output frequency and phase noise is modeled by the width of the transistors which are the input parameters of the transistors. After tuning the model properly by k-cross validation method, the accuracy was found to be 96.1% which is good enough to make it use for the circuit synthesis purpose.

Fast and accurate performance estimation methods are essential to automated synthesis of analog circuits. Development of analog performance models is difficult due to the highly nonlinear nature of various analog performance parameters. This paper presents a neural network-based methodology for creating fast and efficient models for estimating the performance parameters of CMOS operational amplifier topologies. Effective methods for generation and use of the training data are proposed to enhance the accuracy of the neural models. The efficiency and accuracy of the resulting performance models are demonstrated via their use in a genetic algorithm-based circuit synthesis system. The genetic synthesis tool optimizes a fitness function based on user-specified performance constraints. The performance parameters of the synthesized circuits are validated by SPICE simulations and compared with those predicted by the neural network models. Experimental studies demonstrate that neural network modeling is an effective, fast, and accurate methodology for performance estimation.

Yield estimation for analog integrated circuits are crucial for analog circuit design and optimization in the presence of process variations. In this paper, we present a novel analog yield estimation method based on performance bound analysis technique in frequency domain. The new method first derives the transfer functions of linear (or linearized) analog circuits via a graph-based symbolic analysis method. Then frequency response bounds of the transfer functions in terms of magnitude and phase are obtained by a nonlinear constrained optimization technique. To predict yield rate, bound information are employed to calculate Gaussian distribution functions. Experimental results show that the new method can achieve similar accuracy while delivers 20 times speedup over Monte Carlo simulation of HSPICE on some typical analog circuits.

This paper proposed ship classification based on covariance of discrete wavelet using probability Neural Network A set of ship profiles are used to build a covariance matrix by discrete wavelet transform using Neural Network. It is found that this method for ship classifier design offers good class discriminacy when trained with 5 ship classes. This method can discriminate noisy ship very well. Simulation results are very promising.

During analog circuit synthesis in nanometer technology, process variability analysis is mandatory during design space exploration. This would ensure that the circuit will function as per specifications after fabrication even with impact of statistical variations in nanometer regimes. The methodology necessitates the evaluation of performance metrics of an analog circuit for different sizing instances of the transistors. Circuit simulation for performance evaluation is very time consuming and is seldom a choice while sizing a circuit for a chosen topology. The complexity of sizing methodology increases with the need to consider effects of variations in process and environment parameters. We employ macromodeling approach for analog circuits based on support vector machine (SVM), which enables efficient evaluation of performance of such circuits during sizing and yield optimization loops. The objective to improve evaluation efficiency has been the motivation behind efforts to develop performance macromodels, which should be as accurate as SPICE and at the same time have shorter evaluation time for use in the sizing of analog circuits, where they are used as substitutes for full circuit simulation during circuit sizing (synthesis). Process variability aware SVM macromodels are used in the multiobjective multivariate sizing method which is also yield optimal. Post design centering, the sized circuits will be able to provide functions as per specifications upon fabrication. Its application as process variability analysis tool is illustrated on two stage op amp and a voltage controlled oscillator using 90 nm BSIM4 models of transistors.

This paper presents a design of Folded Cascode operational amplifier with power optimization using Geometric Programming. Operational Amplifiers are the backbone for many analog circuit designs. The architecture of folded-cascode op-amp is commonly used in many analog applications. The cascode arrangement has high open-loop voltage gain in low frequency range that makes it easy to be designed as a high-speed operational amplifier. The basic idea of the folded-cascode opamp is to apply cascode opamp transistors to the input differential pair. In this study, the main concepts of power optimization using geometric programming are introduced. Geometric Programming, a method for optimizing and automating component and transistor sizing will apply to the power optimization of Folded Cascode operational amplifier. The simulation of the folded cascode circuit is done using TSPICE simulation tool and 0.035 μm CMOS technology is used. Design of the circuit and simulation results are presented demonstrating the amplifier power optimization.

The decision tree (DT) approach is most useful in classification problem. In conventional decision tree learning the weights of every training instances are set to one or equal value, which contradicts general intuition. In this paper, we proposed a new decision tree learning algorithm by assigning appropriate weights to each training instance in the training data that increases classification accuracy of the decision tree model. The main advantage of this proposed approach is to set appropriate weights to training instances using naïve Bayesian classifier before trying to construct the decision tree. In our approach the training instances are assigned to weight values based on the posterior probability. The training instances having less weight values are either noisy or posses unique characteristics compared to other training instances. The experimental results manifest that the proposed approach for decision tree construction can achieve high classification accuracy with compare to traditional decision tree algorithms on different types of benchmark datasets from UCI machine learning repository.

Electronic applications with a display, like for example a cell phone or a PDA, must have all LEDs from the display shining with the same intensity. Meaning that the current that flows through a LED must be the same that flows through all the others. To fulfill this requirement it was developed a current regulator to be able to drive a LED with a constant current between 0 and 50mA, proportional to a digital eight bit word, with ultra low dropout voltage was developed. The lower the dropout voltage, the longer the battery life time is. The regulator must work for multicolor LEDs, meaning LEDs with different voltage drops. The proposed solution is able to drive a LED with a 50mA current, with only 25mV dropout voltage at 2% (meaning a 2% maximum current variation).

During analog circuit synthesis in nanometer technology, process variability analysis is mandatory during design space exploration. This would ensure that the circuit will function as per specifications after fabrication even with impact of statistical variations in nanometer regimes. The methodology necessitates the evaluation of performance metrics of an analog circuit for different sizing instances of the transistors. Circuit simulation for performance evaluation is very time consuming and is seldom a choice while sizing a circuit for a chosen topology. The complexity of sizing methodology increases with the need to consider effects of variations in process and environment parameters. We employ macromodeling approach for analog circuits based on support vector machine (SVM), which enables efficient evaluation of performance of such circuits during sizing and yield optimization loops. The objective to improve evaluation efficiency has been the motivation behind efforts to develop performance macromodels, which should be as accurate as SPICE and at the same time have shorter evaluation time for use in the sizing of analog circuits, where they are used as substitutes for full circuit simulation during circuit sizing (synthesis). Process variability aware SVM macromodels are used in the multiobjective multivariate sizing method which is also yield optimal. Post design centering, the sized circuits will be able to provide functions as per specifications upon fabrication. Its application as process variability analysis tool is illustrated on two stage op amp and a voltage controlled oscillator using 90 nm BSIM4 models of transistors.

1-This paper presents a circuit/system level synthesis and optimization approach based on a learning scheme using Support Vectors Machines (SVMs) and evolutionary strategies applied to the design of analog and mixed-signal ICs. This approach combines the best qualities of these two techniques, a robust classification and regression method and a powerful global optimization. The SVM is used to dynamically model performance space and identify the feasible design space regions while at the same time the evolutionary techniques are looking for the global optimum. Finally, the proposed optimization-based approach is demonstrated for the design of some analog circuits using HSPICE as the evaluation engine. I.

This paper presents a technique for performing analog design synthesis at circuit level providing feedback to the designer through the exploration of the Pareto frontier. A modified simulated annealing which is able to perform crossover with past anchor points when a local minimum is found which is used as the optimization algorithm on the initial synthesis procedure. After all specifications are met, the algorithm searches for the extreme points of the Pareto frontier in order to obtain a non-exhaustive exploration of the Pareto front. Finally, multi-objective particle swarm optimization is used to spread the results and to find a more accurate frontier. Piecewise linear functions are used as single-objective cost functions to produce a smooth and equal convergence of all measurements to the desired specifications during the composition of the aggregate objective function. To verify the presented technique two circuits were designed, which are: a Miller amplifier with 96 dB Voltage gain, 15.48 MHz unity gain frequency, slew rate of 19.2 V/ls with a current supply of 385.15 lA, and a complementary folded cascode with 104.25 dB Voltage gain, 18.15 MHz of unity gain frequency and a slew rate of 13.370 MV/ls. These circuits were synthesized using a 0.35 lm technology. The results show that the method provides a fast approach for good solutions using the modified SA and further good Pareto front exploration through its connection to the particle swarm optimization algorithm.

Chapter 1 provides an overview of the thesis motivations, research goals and main contributions. Chapter 2 presents a state-of-the-art review in analog IC design automation field by analyzing and comparing methods, strategies and tools presented in literature, including some commercial tools. Chapter 3 starts with an overview on computation techniques to solve nonlinear optimization problems with focus on evolutionary optimization algorithms. Then, it introduces a new optimization kernel based on genetic algorithms applied to analog circuit optimization. It includes a detailed description of the fitness function, the genetic operators and design methodology in order to obtain an efficient and robust analog circuit design. Chapter 4 explores the main learning techniques used to manage large amount of information, to discover complex relationships among various factors and extract meaningful knowledge to improve the efficiency and quality of decisionmaking. In particular, it discusses the use and the integration of a learning model based in support vector machine (SVM) in order to improve the evolutionary optimization strategy for analog circuit design applications introduced in chapter 3. Chapter 5 describes the analog design environment and architecture of GENOM optimization tool. It discusses the methodology, representation and architecture issues, giving details of the analog IC design representation, interfaces between the synthesizer and evaluation algorithms, and software architecture. The main options taken in this work approach will be described and justified. Chapter 6 presents several synthesis experiments, demonstrating the capabilities of the system and providing some insight into factors that affect the synthesis process. The suite of test circuits is taken from standard text books and technical papers. The first section describes the performance metrics, the algorithm optimization strategy and input data of each the experiment. The resulting performances computed automatically by the optimization tool during the evolutionary process are delivered to the user in the form of output reports or by dynamic graphics or reports. Apart from accuracy, mean and standard deviation of execution time and evaluation cycles are also presented. Additionally, information regarding the circuit, such as circuit sizing, corner information and performance are also specified. Finally, chapter 7 presents the conclusions and the research contributions of the thesis and the improvements that are possible to GENOM.

The advantages of using macromodels of functional blocks in the simulation of large scale circuits have long been pointed out. However, all the methods for generating macromodels that have so far appeared in the literature make very stringent assumptions about either the type of circuits to be modeled or the shape of the waveforms involved. The models generated in this way are, therefore, of limited use in general circuit simulation. In this paper we propose a general purpose macromodeling algorithm applicable to any type of circuit without any restrictions on the waveforms. Starting from a user-supplied template, the algorithm modifies the values and the branch characteristics of macromodel elements with the goal of optimizing the macromodel's time-domain accuracy. Experimental results obtained so far indicate that the algorithm requires reasonable amounts of CPU time and that the models are accurate enough to be used for standard circuit simulation.

The advantages of using macromodels of functional blocks in the simulation of large scale circuits have long been pointed out. However, all the methods for generating macromodels that have so far appeared in the literature make very stringent assumptions about either the type of circuits to be modeled or the shape of the waveforms involved. The models generated in this way are, therefore, of limited use in general circuit simulation. In this paper we propose a general purpose macromodeling algorithm applicable to any type of circuit without any restrictions on the waveforms. Starting from a user-supplied template, the algorithm modifies the values and the branch characteristics of macromodel elements with the goal of optimizing the macromodel's time-domain accuracy. Experimental results obtained so far indicate that the algorithm requires reasonable amounts of CPU time and that the models are accurate enough to be used for standard circuit simulation.

This paper discusses under-codified and possibly undervalued skills of security staff and cleaners, as part of an empirical study of skill perceptions and their impacts in a range of low-status occupations. In both industries, contracting has contributed to restricted bargaining power, low wages and undifferentiated classification structures. Yet divergent views of skill requirements emerged from 30 cross-sectional interviews conducted in 2012 in these two industries. In peak employer and employee bodies, the relevant industry skills council and training organisations, security and cleaning jobs were seen as being more skilled than commonly stereotyped. Follow-up case studies in two security and two cleaning organisations elicited a range of perspectives from senior managers, HR managers, supervisors and workers, suggesting that on criteria such as discretion, judgment, self-organisation and communication skills, there is scope for enhanced work value recognition and career pathing in both occupations.

Abstract: This paper presents a new open environment for the design of analog circuits exchanging information from existing tools. The main features of these tools have been extended in CONNAN by means of a netlist analyzer, the interaction with a commercial CAD tool and a transistor model manager that solves some common problems of sizing tools based on electrical simulators. As an initial test CONNAN is applied to the sizing of analog IC based on electrical simulators and simulated annealing algorithms. 1.

Abstract: This paper presents a new open environment for the design of analog circuits exchanging information from existing tools. The main features of these tools have been extended in CONNAN by means of a netlist analyzer, the interaction with a commercial CAD tool and a transistor model manager that solves some common problems of sizing tools based on electrical simulators. As an initial test CONNAN is applied to the sizing of analog IC based on electrical simulators and simulated annealing algorithms.

Abstract—Support Vector Machines (SVMs) have been used as classifier to identify the feasible design space of analog circuits. A feasibility design space is defined as a multidimensional space in which every point representing a design satisfies all the design constraints. The minimum set of constraints is the one that ensures the correct functionality of the given circuit topology. Performance Macromodels that facilitates accelerated analog circuit synthesis are constructed and thereby valid only in the functionally correct design space. A kernel function is an integral part of the SVM and contributes in obtaining an optimized and accurate classifier. A kernel function serves as a separating function, a hypersurface which optimally separates input data into two classes involving minimal support vectors. The support vectors are data points in input space lying on kernel function hypersurface. There is no formal way to decide, which kernel function is suited to a class of classifier ...

Ci si chiede – assegnata una lingua umana L – quale sia la probabilità che esista almeno un’altra lingua con almeno una parola di due sillabe in comune con L. Per parola si intenderà qui la associazione della così detta parola ortografica (o significante), ovvero una sequenza di lettere che rappresentano la trascrizione di una sequenza di suoni (parola fonologica), e del suo significato. Si anticipa che il risultato ottenuto in questo documento porta alla soluzione corretta del caso sbagliato: l’errore consiste nel fatto che vengono considerate solo lingue che hanno parole in comune ma non hanno significanti in comune oltre quelli per i quali si realizza la coincidenza anche del significato. Quello che intendo credo risulterà chiaro quando, seguito il ragionamento, si rileggeranno le presenti righe. Ciò nondimeno ritengo che i calcoli che seguono siano ricchi di spunti interessanti e inoltre mi hanno fornito le basi per sviluppare la analisi corretta, che presenterò altrove.

A high-speed precision CMOS continuous-time autozeroed operational amplifier has been carefully designed and simulated on HSPICE. It is shown theoretically that this op-amp will achieve a worst-case input referred offset voltage of only 16.19uV (97.3% of all fabricated op-amps will have offset voltages less than this value). It is also expected that the offset drift with temperature and the input-referred noise in the range 0.001Hz to 100Hz will be extremely low. When loaded down with a 10kM resistor in parallel with a 12pF capacitor, the op-amp boasts an extremely high DC gain of 1010 and a very high unity-gain frequency of 7.25MHz, while achieving positive and negative slew rates of 6.97V/us and 3.87V/us respectively and a unity-gain phase margin somewhere between 54' and 59'. The CMRR at DC is expected to be much higher than 124dB and the PSRR+ and PSRR-at DC are both expected to be much higher than 94dB. The power consumption of the nulling op-amp in the design is only 125uW. Use of a power-hungry stock Draper op-amp (NFAMPDR4) for the main op-amp unfortunetly adds 3.3mW to the overall power consumption, making the total 3.425mW. However, the total power can be drastically reduced in future designs by simply choosing a more power-efficient main op-amp. Our carefully designed and optimized micro-power nulling op-amp never needs to be changed. These specifications make the op-amp stack up quite well against the Analog Devices AD8551, which is the highest precision 5V op-amp ever built. Although the AD8551 will most likely have somewhat higher precision, our design is superior in several respects. We have achieved a DC gain that is higher than the AD8551 by 3 orders of magnitude and a unity-gain frequency that is higher by almost a factor of 5. In addition, our design has a positive slew rate that is over 17 times faster than the AD8551 and a negative slew rate that is over 9 times faster. We also expect that the CMRR and PSRR of our design will be at least as high as the AD8551. The power consumption of the AD8551 does appear to be lower than our design, but not by very much. We believe that the op-amp designed in this thesis, when fabricated in the correct 0.6um CMOS process for which it was designed, will be one of the highest performance continuous-time autozeroed opamps ever built. It will probably be as good as, and very likely better, than many of the commercial continuous-time autozeroed op-amps available on the market today.

Automation tools for circuit optimization have proven their usefulness in solving design issues by considering the technological aspects of downscaling. Recent advances have proven that the optimization method based on simulation is a powerful and important solution for the optimal sizing of electronic circuits. In this paper, we propose a simulation-based methodology for automatic optimization of the multi-objective design of an analog/RF circuit. As applications, we use both analog and RF circuits, respectively the LC tank Voltage Controlled Oscillator (VCO) and the new Current-Feedback Operational Amplifier (CFOA). For the LC-VCO, we optimize the power consumption and the phase noise. For the CFOA, we optimize its important performances such as bandwidth and parasitic resistances, for low-voltage, low-power applications. All simulations are performed by HSPICE using 0.13 µm RF CMOS and 0.18 µm CMOS technologies for the LC-VCO and the CFOA, respectively.

Support Vector Machines (SVM) have been used for creating fast and efficient models for quickly predicting the performance parameters of analog circuits. These models have proved to be not only effective and fast but accurate also for performance estimation. Kernels are an integral part of SVM to obtain an optimized and accurate model. The most commonly used kernels are RBF, polynomial, spline, multilayer perceptron. In this paper, many other kernels are explored, some of which are less popular, while others are modified compositions of the some of the standard kernels. These kernel functions are tested on different analog circuits to check for their robustness and for improved performance they provide. SPICE has been used for generation of learning data. Least Square SVM toolbox interfaced with MATLAB was used for regression. Models containing modified compositions of kernels were found to be more accurate and having lower mean square error than those containing standard kernels.

Support Vector Machines (SVM) have been widely used for creating fast and efficient performance macro-models for quickly predicting the performance parameters of analog circuits. These models have proved to be not only effective and fast but accurate also while predicting the performance. A Kernel function is an integral part of SVM to obtain an optimized and accurate model. There is no formal way to decide, which kernel function is suited to a class of regression problem. While most commonly used kernels are Radial Basis Function (RBF), Polynomial, Spline, Multilayer perceptron; we have explored many other un-conventional kernel functions and report their efficacy and computational efficiency in this paper. These kernel functions are used with SVM regression models and these macromodels are tested on different analog circuits to check for their robustness and performance. We have used HSPICE for generating the set of learning data. Least Square SVM toolbox along with MATLAB was used for regression. The models which contained modified compositions of kernels were found to be more accurate and thus have lower root mean square error than those containing standard kernels. We have used different CMOS Address(es) of author(s) should be given *Manuscript Click here to download Manuscript: ALOG1497-revised-2.tex Click here to view linked References 2 circuits varying in size and complexity as test vehicles-two-stage op amp, cascode op amp, comparator, differential op amp and voltage controlled oscillator.

Automation tools for circuit optimization have proven their usefulness in solving design issues by considering the technological aspects of downscaling. Recent advances have proven that the optimization method based on simulation is a powerful and important solution for the optimal sizing of electronic circuits. In this paper, we propose a simulation-based methodology for automatic optimization of the multi-objective design of an analog/RF circuit. As applications, we use both analog and RF circuits, respectively the LC tank Voltage Controlled Oscillator (VCO) and the new Current-Feedback Operational Amplifier (CFOA). For the LC-VCO, we optimize the power consumption and the phase noise. For the CFOA, we optimize its important performances such as bandwidth and parasitic resistances, for lowvoltage, low-power applications. All simulations are performed by HSPICE using 0.13 μm RF CMOS and 0.18 μm CMOS technologies for the LC-VCO and the CFOA, respectively.

Performance Macromodeling facilitates accelerated analog circuit synthesis. It usually consist of two steps: feasibility design space identification and performance macromodels generation. A feasibility design space is defined as a multidimensional space in which every design satisfies all the design constraints. The minimum set of constraints is the one that ensures the correct functionality of the given circuit topology. Performance macromodels are only constructed and thereby valid in the functionally correct design space. Support vector machines (SVMs) are used as classifier to identify the feasible design space of analog circuits. A kernel is an integral part of the SVM and contributes in obtaining an optimized and accurate classifier. The most commonly used kernels are Radial Basis Function (RBF), polynomial, spline, multilayer perceptron. In this paper, some new kernels and some other kernels composed through modifications on the some of the standard kernels, are explored. Th...

Although many design tools have been developed for digital design, analog design tools are only just being introduced. This paper presents a new optimization method for automatically sizing the circuit topology of analog cells. This method minimizes a cost function, which depends on a set of designer specifications. It employs the tabu search heuristic to avoid being trapped in a local minimum of the cost function. Experimental results show that this method can get very close to the global minimum of the cost function with a small number of iterations. Hence, an analog simulation program, such as SPICE, can be used for the evaluation of the cost function at each iteration.

Presented in this paper is a tool that automatically migrates analog designs from one process to another while keeping circuit and layout topologies. A netlist migration engine recalculates the new device dimensions in the target technology followed by a layout migration engine that compacts the design according to the new process design rules. The overall framework preserves design intelligence embedded in the original IP such as symmetry, hierarchy, placement and routing. The circuit migration engine, being very fast, can retarget large analog blocks in only a few minutes while giving same or better performance of the original design. The migration of 3 different circuits is presented to validate the overall methodology. These circuits have been fabricated and measured.

Presented in this paper is a tool that automatically migrates analog designs from one process to another while keeping circuit and layout topologies. A netlist migration engine recalculates the new device dimensions in the target technology followed by a layout migration engine that compacts the design according to the new process design rules. The overall framework preserves design intelligence embedded in the original IP such as symmetry, hierarchy, placement and routing. The circuit migration engine, being very fast, can retarget large analog blocks in only a few minutes while giving same or better performance of the original design. The migration of 3 different circuits is presented to validate the overall methodology. These circuits have been fabricated and measured.

Specifications of Radio Frequency (RF) analog integrated circuits have increased strictly as their applications tend to be more complicated and high test cost demanding. This makes them very expensive due to an increased test time and to the use of sophisticated test equipment. Alternative test measures, extracted by means of Built-In Self Test (BIST) techniques, are useful approaches to replace standard specification-based tests. One way to evaluate the efficiency of the CUT measures at the design stage is by estimating the Test Escapes (T E) and the Yield Loss (Y L) at ppm level. Unfortunately, an important number of Monte Carlo simulations must be run in order to guarantee their accuracy. For certain types of circuits, this requires many months or even years to generate millions of circuits. To overcome this limitation, we present in this paper a new technique where a small number of simulations is sufficient to reach an important precision. This method is based on a classification using machine learning methods, such as SVM and Neural Networks based classifiers to determine pass/fail regions. The proposed approach requires a few number of simulations only to determine the region separating the process parameters generating good and faulty, or pass and fail circuits. Then only this region is needed to estimate the test metrics without running any additional simulation. The proposed methodology is illustrated for the evaluation of a filter BIST technique. Keywords Analog/RF test • SVM classification • Neural Network classification • BIST evaluation 1 Introduction The test is a very important notion in the field of the validation step of analog circuit design. It is the way to confirm whether a circuit under test (CUT) satisfies all functional specifications that represent its performance parameters. Since there are no manufactured circuits at the design stage, test errors can only be

Support Vector Machines (SVM) have been used for creating fast and efficient models for quickly predicting the performance parameters of analog circuits. These models have proved to be not only effective and fast but accurate also for performance estimation. Kernels are an integral part of SVM to obtain an optimized and accurate model. The most commonly used kernels are RBF, polynomial, spline, multilayer perceptron. In this paper, many other kernels are explored, some of which are less popular, while others are modified compositions of the some of the standard kernels. These kernel functions are tested on different analog circuits to check for their robustness and for improved performance they provide. SPICE has been used for generation of learning data. Least Square SVM toolbox interfaced with MATLAB was used for regression. Models containing modified compositions of kernels were found to be more accurate and having lower mean square error than those containing standard kernels.

The introduction of simulation-based analog synthesis tools creates a new challenge for analog modeling. These tools routinely visit 10 3 to 10 5 fully simulated circuit solution candidates. What might we do with all this circuit data? We show how to adapt recent ideas from large-scale data mining to build models that capture significant regions of this visited performance space, parameterized by variables manipulated by synthesis, trained by the data points visited during synthesis. Experimental results show that we can automatically build useful nonlinear regression models for large analog design spaces.

Eco friendly inventory models are gaining momentum as the human race is marching towards environmental conservation by battling against waste generation and pollutants. As the global market also revolves with customer as its prime focus, the product production becomes customer centered. To set a balance between eco-consciousness and customer centeredness the environmental costing and customer acquisition costing is incorporated with the costs of inventory. Environmental oriented inventory models are being formulated by the researchers with different solution procedure but less focus of customer centric inventory model prevails. This stimulated us to frame inventory models by integrating the facets of eco consciousness and customer centric with the goal of profit maximization and costs minimization using fractional calculus approach as the application of fractional calculus in optimizing the inventory models is being explored by several scholars and this research work is a contribution to it. This model will aid the decision makers at managerial level.

We investigate the use of support vector machines (SVMs) to determine simpler and better fit power macromodels of functional units for high-level power estimation. The basic approach is first to obtain the power consumption of the module for a large number of points in the input signal space. Least-Squares SVMs are then used to compute the best model to fit this set of points. We have performed extensive experiments in order to determine the best parameters for the kernels. We propose a new method for power macromodeling of functional units for high-level power estimation based on Least-Squares Support Vector Machines (LS-SVM). Our method improves the already good modeling capabilities of the basic LS-SVM method in two ways. First, a modified norm is used that is able to take into account the weight of each input for global power consumption in the computation of the kernels. Second, an iterative method is proposed where new data-points are selectively added as support-vectors to increase the generalization of the model. The macromodels obtained compare favorably with those obtained using industry standard table models, providing not only excellent accuracy on average (close to 1% error), but more importantly, thanks to our proposed modified kernels, we were able to reduce the maximum error to values close to 10%.

The decision tree (DT) approach is most useful in classification problem. In conventional decision tree learning the weights of every training instances are set to one or equal value, which contradicts general intuition. In this paper, we proposed a new decision tree learning algorithm by assigning appropriate weights to each training instance in the training data that increases classification accuracy of the decision tree model. The main advantage of this proposed approach is to set appropriate weights to training instances using naïve Bayesian classifier before trying to construct the decision tree. In our approach the training instances are assigned to weight values based on the posterior probability. The training instances having less weight values are either noisy or posses unique characteristics compared to other training instances. The experimental results manifest that the proposed approach for decision tree construction can achieve high classification accuracy with compare to traditional decision tree algorithms on different types of benchmark datasets from UCI machine learning repository.

In this paper, we have studied some memory dependent Economic order quantity models as the memory effect has an important role to handle the business policy of the inventory system. Demand of a company product depends on many factors like behavior of staff, environment of the shop, product quality etc which are the main reasons of memory effect on the system. Once the customers gain some poor experience, further they will never purchase products from those companies or shop. So inclusion of memory effect in the inventory model is necessary to handle practical business policy. One of the best way of inclusion of memory effect in the EOQ model is the use of fractional calculus as fractional derivative is defined in terms of integration where the limits of integration are the initial state and current state. Three fractional order models have been developed considering (i) only the rate of change of the inventory level of fractional order  (ii) demand rate as a fractional polynomial of degree 2,  where  is the rate of change of the inventory level (iii) demand rate as a fractional polynomial of degree 2m , where m may be different from the order of the rate of change of the inventory level. Here fractional order is physically treated as an index of memory. To develop the models here Caputo type fractional derivative has been applied. Due to solve those problems, we have used primal geometric programming method and finally some numerical examples are cited to establish the memory effect. Our investigation establishes the existence of memory effect on inventory management through fractional formulation of EOQ models which can never be obtained from classical calculus.

The hierarchical graph-based sizing and biasing method of analog circuits has been previously developed. Its potential application in the field of knowledge-based analog synthesis is studied. This method reduces the number of optimization variables by taking into account their circuit dependency relations. This is done by automatically generating a design plan to express circuit dependencies. The design plan is then introduced into an optimization loop. The optimization engine uses the Nelder-Mead simplex method. The whole method is successfully applied to a single-ended two-stage amplifier. It produces simulator-like quality designs in a reasonable time, thus allowing interactive design of analog circuits.

This paper presents a methodology for the classification of power system voltage stability, the trajectory of which to instability is monotonic, using an interior point method based support vector machine (IPMSVM). The SVM based voltage stability classifier can provide real-time stability identification only using the local measurement data, without the topological information conventionally used.

The effects of internet over media had changed either content production of mass media or audience way of using media. The breaking point created by internet has caused to call Radio, television and newspaper as “traditional media” while creating new media.The passive audience of traditional media had gained an active role by spread of Internet. New audience or user had gain content producer role for new media. There are considerable effects of Social Network Sites on content producing. Social network sites which are simulating social networks existing in public life, had give a new dimension to interpersonal communication with the help of asynchronous, independent from place and continuously opened communication channel. Another word, the interpersonal communication carried to public sphere had become a content of mass communication. When the technology had kept in step with this new situation, audience had increased rapidly. This development had caused wider the age range. Differe...

Performance Macromodeling facilitates accelerated analog circuit synthesis. It usually consist of two steps: feasibility design space identification and performance macromodels generation. A feasibility design space is defined as a multidimensional space in which every design satisfies all the design constraints. The minimum set of constraints is the one that ensures the correct functionality of the given circuit topology. Performance macromodels are only constructed and thereby valid in the functionally correct design space. Support vector machines (SVMs) are used as classifier to identify the feasible design space of analog circuits. A kernel is an integral part of the SVM and contributes in obtaining an optimized and accurate classifier. The most commonly used kernels are Radial Basis Function (RBF), polynomial, spline, multilayer perceptron. In this paper, some new kernels and some other kernels composed through modifications on the some of the standard kernels, are explored. The classifiers using these kernel functions have been tested on different analog circuits in order to identify the feasible design space. HSPICE has been used for generation of learning data. Least Square SVM toolbox interfaced with MATLAB was used for classification. We found that use of modified kernels improves classification accuracy as well as shortens classifier generation time.

Design centering is the term used for a procedure of obataining enhanced parametric yield of a circuit despite variations in device and design parameters. The process variability in nanometer regimes manifest into these device and design paramters. During design space exploration of analog circuits, a methodology to find design-instances with better yield is necessitated; this would ensure that the circuit will function as per specifications after fabrication even with impact of statistical variations. We need to evaluate circuit performance for a given instance of a circuit-design identified by possessing a set of nomial values of device-design parameters. A lot of instantces need be searhed having different sizes for a given circuit topology. HSPICE is very compute intensive. Instead, we employ macromodeling approach for analog circuits based on support vector machine (SVM), which enables efficient evaluation of performance of such circuits of different sizings during yield optimization loops. These performance macromodels are found to be as accurate as SPICE and at the same time time-efficicient for use in sizing of analog circuits with optimal yield. Process variability aware SVM macromodels are first trained and then used inside the Genetic algorithm loops for design centering of different circuits, subsequently resulting into sized-circuit instances having optimal yield. Post design centering, the sized circuits will be able to provide functions as per specifications upon fabrication. The application this design centering approach as process variability analysis tool is illustrated on various circuits e.g. two stage op amp, voltage controlled oscillator and mixer circuit with layouts drawn into 90 nm AMC technology.

The decision tree (DT) approach is most useful in classification problem. In conventional decision tree learning the weights of every training instances are set to one or equal value, which contradicts general intuition. In this paper, we proposed a new decision tree learning algorithm by assigning appropriate weights to each training instance in the training data that increases classification accuracy of the decision tree model. The main advantage of this proposed approach is to set appropriate weights to training instances using naïve Bayesian classifier before trying to construct the decision tree. In our approach the training instances are assigned to weight values based on the posterior probability. The training instances having less weight values are either noisy or posses unique characteristics compared to other training instances. The experimental results manifest that the proposed approach for decision tree construction can achieve high classification accuracy with compare to traditional decision tree algorithms on different types of benchmark datasets from UCI machine learning repository.

Presented in this paper is a tool that automatically migrates analog designs from one process to another while keeping circuit and layout topologies. A netlist migration engine recalculates the new device dimensions in the target technology followed by a layout migration engine that compacts the design according to the new process design rules. The overall framework preserves design intelligence embedded in the original IP such as symmetry, hierarchy, placement and routing. The circuit migration engine, being very fast, can retarget large analog blocks in only a few minutes while giving same or better performance of the original design. The migration of 3 different circuits is presented to validate the overall methodology. These circuits have been fabricated and measured.

A ring oscillator using 3 stages of a NMOS driving a current load and a capacitor is described. Its frequency can be shown to increase monotonically with the load current giving rise to the name current controlled oscillator (CCO). An accurate derivation of the formulae relating the frequency with the NMOS size and the current shows that nonlinearity error of its tuning characteristic is proportional to the cube root of the NMOS width/length ratio. The CCO circuit using 180um/0.18um NMOS with 1pF load can be tuned to oscillate from 468 Hz to 305 MHz using load current from 1nA to 1mA.

In this paper, we have studied some memory dependent Economic order quantity models as the memory effect has an important role to handle the business policy of the inventory system. Demand of a company product depends on many factors like behavior of staff, environment of the shop, product quality etc which are the main reasons of memory effect on the system. Once the customers gain some poor experience, further they will never purchase products from those companies or shop. So inclusion of memory effect in the inventory model is necessary to handle practical business policy. One of the best way of inclusion of memory effect in the EOQ model is the use of fractional calculus as fractional derivative is defined in terms of integration where the limits of integration are the initial state and current state. Three fractional order models have been developed considering (i) only the rate of change of the inventory level of fractional order  (ii) demand rate as a fractional polynomial of degree 2,  where  is the rate of change of the inventory level (iii) demand rate as a fractional polynomial of degree 2m , where m may be different from the order of the rate of change of the inventory level. Here fractional order is physically treated as an index of memory. To develop the models here Caputo type fractional derivative has been applied. Due to solve those problems, we have used primal geometric programming method and finally some numerical examples are cited to establish the memory effect. Our investigation establishes the existence of memory effect on inventory management through fractional formulation of EOQ models which can never be obtained from classical calculus.