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Table 6.54 GENOM benchmarks

Table 6 54 GENOM benchmarks

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Fig. 1.1 (a) SoCs including analog circuitry by year [3], (b) Digital circuit density by proc- ess technology The microelectronics market trends present an ever-increasing level of integration with special emphasis on the production of complex mixed-signal systems-on-chip (SoC), as a consequence of the boom in telecom devices, wireless communications, electronic consumer products, etc. These devices integrate complex digital cores with analog and RF functions on a single chip [1]-[2]. Fig. 1.1 illustrates the relevance of analog circuitry in this renewed invigorating market showing the evo- lution of SoC percentage that will contain analog parts. According to IBS Corpora- tion, digital/mixed-signal SoCs accounted for approximately 20% of worldwide SoCs in 2001[3]. The tendency curve in the left graph shows that the percentage continues to rise, and it was around 75% in 2006. Driven by the demand to provide higher performances, i.e., increasing functionalities with less power consumption, semiconductor manufacturers developed newer technologies allowing an exponen- tial increase in IC density, described by the well known Moore’s law. The famous Moore’s law observed for the first time in 1965, which states that
Fig. 1.1 (a) SoCs including analog circuitry by year [3], (b) Digital circuit density by proc- ess technology The microelectronics market trends present an ever-increasing level of integration with special emphasis on the production of complex mixed-signal systems-on-chip (SoC), as a consequence of the boom in telecom devices, wireless communications, electronic consumer products, etc. These devices integrate complex digital cores with analog and RF functions on a single chip [1]-[2]. Fig. 1.1 illustrates the relevance of analog circuitry in this renewed invigorating market showing the evo- lution of SoC percentage that will contain analog parts. According to IBS Corpora- tion, digital/mixed-signal SoCs accounted for approximately 20% of worldwide SoCs in 2001[3]. The tendency curve in the left graph shows that the percentage continues to rise, and it was around 75% in 2006. Driven by the demand to provide higher performances, i.e., increasing functionalities with less power consumption, semiconductor manufacturers developed newer technologies allowing an exponen- tial increase in IC density, described by the well known Moore’s law. The famous Moore’s law observed for the first time in 1965, which states that
fabrication technologies but now, more than ever it has become a source of concerns. As far as new process technologies evolve, more and more functionalities can be in- tegrated, increasing as a side effect, the complexity of IC design. A large augment of parasitics and leakage currents that make chips fail are the first visible sign. Actually, while the exponential growth in capacity moves on into the nanometer technology domain, the design teams are facing a curve of complexity that rises exponentially faster, thereby slowing down the productivity design rate. This phenomenon, referred as the design productivity gap [3] is illustrated in Fig. 1.1 (right) and represents the growing difference between the improvement in manufacturing productivity needed to satisfy the pressures of the market and the progress in productivity achieved by Computer-Aided-Design (CAD) development teams. The development of new CAD tools and design methodologies is essential to increase the designer’s productivity and reduce design productivity gap. However, the development of mixed-signal SoC de- signs can be very challenging since the design and verification processes for both digital and analog sections are supported by design automation tools in different stages of maturity. The analog section, despite of typically occupying a minor frac- tion of the overall circuit area (20% approximately as illustrated in Fig. 1.2), is the bottleneck in terms of design time by being far more complex than the digital coun- terpart. Generally, digital design is based on well-established practices supported by well-defined automated synthesis methodologies and tools. As a result, digital intel- lectual property (IP) reuse is a common practice available through different CAD companies leading to an increase in the design productivity. Unlike digital circuits, analog/mixed-signal designs are ruled by many different strategies. There are not a large variety of tools or mature design methodologies that efficiently support the complexity of analog design flow. The strong sensitiv- ity of analog design parameters to the fabrication process made the analog IP re- use expensive when compared with the capacity of acquiring and using digital IPs. The circuit libraries, as known from the digital world, became easily out-of- date/obsolete as the technology or the rules of the project changed. For example, the performance noise of an operational amplifier degenerates with smaller dimen- sion technologies whereas the gain DC of small signal improves. This way, the
fabrication technologies but now, more than ever it has become a source of concerns. As far as new process technologies evolve, more and more functionalities can be in- tegrated, increasing as a side effect, the complexity of IC design. A large augment of parasitics and leakage currents that make chips fail are the first visible sign. Actually, while the exponential growth in capacity moves on into the nanometer technology domain, the design teams are facing a curve of complexity that rises exponentially faster, thereby slowing down the productivity design rate. This phenomenon, referred as the design productivity gap [3] is illustrated in Fig. 1.1 (right) and represents the growing difference between the improvement in manufacturing productivity needed to satisfy the pressures of the market and the progress in productivity achieved by Computer-Aided-Design (CAD) development teams. The development of new CAD tools and design methodologies is essential to increase the designer’s productivity and reduce design productivity gap. However, the development of mixed-signal SoC de- signs can be very challenging since the design and verification processes for both digital and analog sections are supported by design automation tools in different stages of maturity. The analog section, despite of typically occupying a minor frac- tion of the overall circuit area (20% approximately as illustrated in Fig. 1.2), is the bottleneck in terms of design time by being far more complex than the digital coun- terpart. Generally, digital design is based on well-established practices supported by well-defined automated synthesis methodologies and tools. As a result, digital intel- lectual property (IP) reuse is a common practice available through different CAD companies leading to an increase in the design productivity. Unlike digital circuits, analog/mixed-signal designs are ruled by many different strategies. There are not a large variety of tools or mature design methodologies that efficiently support the complexity of analog design flow. The strong sensitiv- ity of analog design parameters to the fabrication process made the analog IP re- use expensive when compared with the capacity of acquiring and using digital IPs. The circuit libraries, as known from the digital world, became easily out-of- date/obsolete as the technology or the rules of the project changed. For example, the performance noise of an operational amplifier degenerates with smaller dimen- sion technologies whereas the gain DC of small signal improves. This way, the
Fig. 1.3 Design of an analog frontend ADSL using a typical design flow The increase in complexity of analog and mixed-signal integrated circuits leads to the general use of IC design methodologies based on divide-to-conquer strategies, sustained by a hierarchical decomposition model that define the top-down design and bottom-up verification flows [4][6][7][8][9][10] and a set of design tasks in each hierarchical level [4][6][7][8]. In order to illustrate the above concepts of a typical design flow, Fig. 1.3 shows the design of an Analog Front-end ADSL mo- dem system [11] using a top-down methodology.
Fig. 1.3 Design of an analog frontend ADSL using a typical design flow The increase in complexity of analog and mixed-signal integrated circuits leads to the general use of IC design methodologies based on divide-to-conquer strategies, sustained by a hierarchical decomposition model that define the top-down design and bottom-up verification flows [4][6][7][8][9][10] and a set of design tasks in each hierarchical level [4][6][7][8]. In order to illustrate the above concepts of a typical design flow, Fig. 1.3 shows the design of an Analog Front-end ADSL mo- dem system [11] using a top-down methodology.
Fig. 1.6 CADENCE - Virtuoso custom design platform diagram
Fig. 1.6 CADENCE - Virtuoso custom design platform diagram
Fig. 1.7 Hierarchical top-down bottom-up applied to analog design automation
Fig. 1.7 Hierarchical top-down bottom-up applied to analog design automation
Fig. 1.9 Trends or trade-off in automatic design
Fig. 1.9 Trends or trade-off in automatic design
Fig. 2.1 Hierarchical level and design tasks of design flow architectures [1] A typical design flow for analog and mixed-signal IC circuits (AMS) consists of a series of design steps repeated from the system level to the device-level, and bot- tom-up for layout generation and verification. The steps between any two of these hierarchical levels are: topology selection, circuit sizing, design verification and layout generation task, illustrated in Fig. 2.1. M.F.M. Barros et al.: Analog Circuits and Systems Optimization, SCI 294, pp. 19-47. springerlink.com © Springer-Verlag Berlin Heidelberg 2010
Fig. 2.1 Hierarchical level and design tasks of design flow architectures [1] A typical design flow for analog and mixed-signal IC circuits (AMS) consists of a series of design steps repeated from the system level to the device-level, and bot- tom-up for layout generation and verification. The steps between any two of these hierarchical levels are: topology selection, circuit sizing, design verification and layout generation task, illustrated in Fig. 2.1. M.F.M. Barros et al.: Analog Circuits and Systems Optimization, SCI 294, pp. 19-47. springerlink.com © Springer-Verlag Berlin Heidelberg 2010
Fig. 2.2 Topology selection mechanism before (a) and during (b) device sizing system is defined now by a hardware description language. Then, an automatic translation is carried out, mapping the functional description into an internal repre- sentation and then into a specific topology. The mapping step is implemented after or during the device sizing process. This class of tools usually differs from the type of internal representation used. In the case of [13] the internal representation is a data flow graph, whereas in TAGUS [5]-[6], [14] and Konczykowska [15] it is a symbolic signal flow graph and in ARCHGEN [16] a state-space description is used. Then, a mapping operation is performed, resulting in a connection of lower- level building blocks whose parameters are optimized, obeying to some design constraints. The operation flow is executed in a top-down basis. Finally, a design methodology able to create new topologies explores the im- mense potential from low abstraction level. Small elementary blocks are con- nected bottom-up to each other to form a new topology. The general description of this design methodology illustrated in Fig. 2.3 begins by selecting an initial topol- ogy, having in mind the desired specifications. As the design process takes place, an optimizer selects a transformation, adding or deleting a basic entity and/or at- tributing a value to a parameter. Various fundamental entities can be applied, such as, single transistors, elementary building blocks or node connections. As soon as the architecture is generated, the performance function is evaluated, providing some hints to the optimizer who makes a new selection of transformation. Essen- tially two exploration methods can be applied in topology generation for analog design. The knowledge-based exploration is based on a systematic or a random strategy where the circuit elements can be added, replaced or removed by an ex- perienced designer with the help of standard CAD tools, like SPICE, and a circuit schematic editor. This method mimics the daily basis design approach supported mainly by simulation tools, and, therefore, suffers from the same drawbacks, i.e., as the number of entities in the system rise, the computational time increases ac- cordingly. The computation time at the circuit description level can become intol- erable if no efficient guidance is provided during the exploration step.
Fig. 2.2 Topology selection mechanism before (a) and during (b) device sizing system is defined now by a hardware description language. Then, an automatic translation is carried out, mapping the functional description into an internal repre- sentation and then into a specific topology. The mapping step is implemented after or during the device sizing process. This class of tools usually differs from the type of internal representation used. In the case of [13] the internal representation is a data flow graph, whereas in TAGUS [5]-[6], [14] and Konczykowska [15] it is a symbolic signal flow graph and in ARCHGEN [16] a state-space description is used. Then, a mapping operation is performed, resulting in a connection of lower- level building blocks whose parameters are optimized, obeying to some design constraints. The operation flow is executed in a top-down basis. Finally, a design methodology able to create new topologies explores the im- mense potential from low abstraction level. Small elementary blocks are con- nected bottom-up to each other to form a new topology. The general description of this design methodology illustrated in Fig. 2.3 begins by selecting an initial topol- ogy, having in mind the desired specifications. As the design process takes place, an optimizer selects a transformation, adding or deleting a basic entity and/or at- tributing a value to a parameter. Various fundamental entities can be applied, such as, single transistors, elementary building blocks or node connections. As soon as the architecture is generated, the performance function is evaluated, providing some hints to the optimizer who makes a new selection of transformation. Essen- tially two exploration methods can be applied in topology generation for analog design. The knowledge-based exploration is based on a systematic or a random strategy where the circuit elements can be added, replaced or removed by an ex- perienced designer with the help of standard CAD tools, like SPICE, and a circuit schematic editor. This method mimics the daily basis design approach supported mainly by simulation tools, and, therefore, suffers from the same drawbacks, i.e., as the number of entities in the system rise, the computational time increases ac- cordingly. The computation time at the circuit description level can become intol- erable if no efficient guidance is provided during the exploration step.
* Properties depend on methodology. This column considers knowledge-based approach. Table 2.1 General characteristics of automated topology selection and generation
* Properties depend on methodology. This column considers knowledge-based approach. Table 2.1 General characteristics of automated topology selection and generation
Fig. 2.3 A general description of the topology selection bottom-up methodology
Fig. 2.3 A general description of the topology selection bottom-up methodology
The sizing stage receives a topology description, a set of performance specs and a technology reference and, based on these inputs, produces a sizing solution for each block or component depending on the abstraction level. Several solutions were proposed derived from either knowledge-based methods, using some kind of knowledge and heuristics, or optimization-based approaches for both topology se- lection and specification translation or circuit sizing [1],[20]. The knowledge- based approach requires the expert knowledge of a designer to produce a set of rules and equations for every new circuit topology or technology. Another alterna- tive is obtained considering the circuit sizing as an optimization problem. In these approaches the design problem is first mapped or modeled into an optimization problem and then solved by an appropriate optimization method, as illustrated in Fig. 2.4.
The sizing stage receives a topology description, a set of performance specs and a technology reference and, based on these inputs, produces a sizing solution for each block or component depending on the abstraction level. Several solutions were proposed derived from either knowledge-based methods, using some kind of knowledge and heuristics, or optimization-based approaches for both topology se- lection and specification translation or circuit sizing [1],[20]. The knowledge- based approach requires the expert knowledge of a designer to produce a set of rules and equations for every new circuit topology or technology. Another alterna- tive is obtained considering the circuit sizing as an optimization problem. In these approaches the design problem is first mapped or modeled into an optimization problem and then solved by an appropriate optimization method, as illustrated in Fig. 2.4.
2.2 Automated Circuit Synthesis Approaches
2.2 Automated Circuit Synthesis Approaches
illustrates the general design flow of knowledge-based approach. In these methods, the main purpose is to encapsulate the designer’s knowledge, building a pre-design plan with design equations and a design strategy that pro- duce the component sizes in order to meet the performance requirements. This ap- proach presents as major drawbacks the large overhead required to define a new design plan, the reformulation of the entire design plan when expanding the sys- tem to new topologies, and, finally, the migration to other technologies. Not only, it is a very time-consuming process to encode design knowledge for a given set of specifications, but design knowledge also has a limited lifetime. The rapid pro- gress in process technologies made the acquired knowledge quickly out-of-date. Therefore, the application of these tools in industrial environments has been lim- ited. However, after defining the design plan, the execution speed associated to the sizing procedure is extremely fast and the solution quality only depends on the models precision [1]. Naturally, this approach finds its applications restricted to small circuits or to more complex circuits but using simplified equations with the goal of achieving the first cut design.
illustrates the general design flow of knowledge-based approach. In these methods, the main purpose is to encapsulate the designer’s knowledge, building a pre-design plan with design equations and a design strategy that pro- duce the component sizes in order to meet the performance requirements. This ap- proach presents as major drawbacks the large overhead required to define a new design plan, the reformulation of the entire design plan when expanding the sys- tem to new topologies, and, finally, the migration to other technologies. Not only, it is a very time-consuming process to encode design knowledge for a given set of specifications, but design knowledge also has a limited lifetime. The rapid pro- gress in process technologies made the acquired knowledge quickly out-of-date. Therefore, the application of these tools in industrial environments has been lim- ited. However, after defining the design plan, the execution speed associated to the sizing procedure is extremely fast and the solution quality only depends on the models precision [1]. Naturally, this approach finds its applications restricted to small circuits or to more complex circuits but using simplified equations with the goal of achieving the first cut design.
The optimization algorithm searches through the design space for values for each circuit component, whereas the performance evaluation tool verifies if the erformance constraints are met. If the system requirements are satisfied, then a so- lution is found and the component sizes are associated to the selected topology. The optimization engine should apply the appropriate techniques to efficiently guide the search mechanism in order to minimize the number of iterations required for the optimization process. ™ Per 7 1 1 1 +1 ae 4 7 rer r
The optimization algorithm searches through the design space for values for each circuit component, whereas the performance evaluation tool verifies if the erformance constraints are met. If the system requirements are satisfied, then a so- lution is found and the component sizes are associated to the selected topology. The optimization engine should apply the appropriate techniques to efficiently guide the search mechanism in order to minimize the number of iterations required for the optimization process. ™ Per 7 1 1 1 +1 ae 4 7 rer r
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Table 2.3 Overview of analog sizing tools (continued 4/4)
Table 2.3 Overview of analog sizing tools (continued 4/4)
M- means “by manual equation” and A-“automatic by symbolic methods” Table 2.4 Factors affecting tools performance
M- means “by manual equation” and A-“automatic by symbolic methods” Table 2.4 Factors affecting tools performance
Table 2.5 Optimization-based techniques A significant part of the tools initially employed simulated annealing but later SA was used more frequently as a complement to other techniques, i.e., ALPAYDIN [59], MAELSTROM [57]. Combinations of two or more different methods are named hybrid methods (sometimes the hybridization of EA with local search techniques is also known as Memetic algorithms (see Sect. 3.1.4) and were developed to take advantage from the potentials of each solution. The idea is to create a new algorithm with improved capacity to explore the promising regions of the search space. For example, in MAELSTROM [57] system, Krasnicki et. al. applied a “parallel recombinative simulated annealing (PRSA) method which combines multiple simulated annealing algorithms that run concurrently and share information via a genetic algorithm scheme. The same group of researchers devel- oped another variation called ANACONDA [56] that introduces constraints varia- tions in transistor devices which incorporate a genetic algorithm, coupled with a local “pattern search” technique. The FASY [10] system is a fuzzy-logic based synthesis tool with simulated annealing for coarse and gradient search for fine op- timization. The fuzzy logic chooses a topology from a pre-defined library. The originality of this approach is the use of a NN model, built from data collected in optimization runs that is employed to update the fuzzy rules. The ALPAYDIN [59] system is an analog integrated circuit synthesis that computes the device siz- ing using neural-fuzzy performance models and user defined equations. The neu- ral-fuzzy model is used to estimate some of the AC performance metrics. The remainder AC performance metrics are modeled by user specific equations. The performance model is built from a set of training data collected from SPICE simu- lations. This system incorporates the effect of process variations but has a draw- back since new equations must be calculated by the user for each new topology.
Table 2.5 Optimization-based techniques A significant part of the tools initially employed simulated annealing but later SA was used more frequently as a complement to other techniques, i.e., ALPAYDIN [59], MAELSTROM [57]. Combinations of two or more different methods are named hybrid methods (sometimes the hybridization of EA with local search techniques is also known as Memetic algorithms (see Sect. 3.1.4) and were developed to take advantage from the potentials of each solution. The idea is to create a new algorithm with improved capacity to explore the promising regions of the search space. For example, in MAELSTROM [57] system, Krasnicki et. al. applied a “parallel recombinative simulated annealing (PRSA) method which combines multiple simulated annealing algorithms that run concurrently and share information via a genetic algorithm scheme. The same group of researchers devel- oped another variation called ANACONDA [56] that introduces constraints varia- tions in transistor devices which incorporate a genetic algorithm, coupled with a local “pattern search” technique. The FASY [10] system is a fuzzy-logic based synthesis tool with simulated annealing for coarse and gradient search for fine op- timization. The fuzzy logic chooses a topology from a pre-defined library. The originality of this approach is the use of a NN model, built from data collected in optimization runs that is employed to update the fuzzy rules. The ALPAYDIN [59] system is an analog integrated circuit synthesis that computes the device siz- ing using neural-fuzzy performance models and user defined equations. The neu- ral-fuzzy model is used to estimate some of the AC performance metrics. The remainder AC performance metrics are modeled by user specific equations. The performance model is built from a set of training data collected from SPICE simu- lations. This system incorporates the effect of process variations but has a draw- back since new equations must be calculated by the user for each new topology.
However, determining the global optimum to the general nonlinear program- ming problem can be a challenging task since there is no specific method capable to do it in a systematic way [3], although it can be found in certain circumstances, i.e., when the objective functions and the constraints satisfy certain properties. Appendix B will briefly address the characteristics of some general purpose opti- mization techniques for nonlinear problems including random search methods (Appendix B.1), gradient-based methods (Appendix B.2), constraints program- ming (Appendix B.3), stochastic methods (Appendix B.4), and multiple objective optimizations (Appendix B.5). The table 3.1 briefly resumes the described optimi- zation methods as well as their main advantages and limitations.
However, determining the global optimum to the general nonlinear program- ming problem can be a challenging task since there is no specific method capable to do it in a systematic way [3], although it can be found in certain circumstances, i.e., when the objective functions and the constraints satisfy certain properties. Appendix B will briefly address the characteristics of some general purpose opti- mization techniques for nonlinear problems including random search methods (Appendix B.1), gradient-based methods (Appendix B.2), constraints program- ming (Appendix B.3), stochastic methods (Appendix B.4), and multiple objective optimizations (Appendix B.5). The table 3.1 briefly resumes the described optimi- zation methods as well as their main advantages and limitations.
3.3.1 Fitness Function Study
3.3.1 Fitness Function Study
Fig. 3.6 Tolerance limits of a class function
Fig. 3.6 Tolerance limits of a class function
Fit(x) is a set of normalized objective functions derived from goals and perform ance specifications to be optimized and Ctr;,(x) is a set of normalized user-define functional constraints. Once the user specifies an upper or a lower bound for th design constraints (goal), these are used to translate the achieved design and con straints specifications in cost function profiles accordingly to the Fig. 3.5. Th indices j and k are the number of objective and functional constraint functions, re spectively. The aim of these normalized functions is to assign an equal importanc to each competing specification. The designer can now setup the relative impot tance for each competing specification adjusting the individual scalar weights wy and wc,. At the beginning, greater weight values can be assigned to important de sign objectives and design constraints. With this formulation the optimized alge rithm can further explore the solution space and generate more than one circu: feasible solution. When it is not known any preference information about performance metrics be- yond the target performances values, a weighted cost function (3.6) is being used giving each evaluation a satisfying degree (rank) of a candidate solution related to the desired specification. It privileges solutions with maximum satisfied specifica- tions and distinguishes the best solution, as the one that minimizes the difference between achieved performance values and specified target value.
Fit(x) is a set of normalized objective functions derived from goals and perform ance specifications to be optimized and Ctr;,(x) is a set of normalized user-define functional constraints. Once the user specifies an upper or a lower bound for th design constraints (goal), these are used to translate the achieved design and con straints specifications in cost function profiles accordingly to the Fig. 3.5. Th indices j and k are the number of objective and functional constraint functions, re spectively. The aim of these normalized functions is to assign an equal importanc to each competing specification. The designer can now setup the relative impot tance for each competing specification adjusting the individual scalar weights wy and wc,. At the beginning, greater weight values can be assigned to important de sign objectives and design constraints. With this formulation the optimized alge rithm can further explore the solution space and generate more than one circu: feasible solution. When it is not known any preference information about performance metrics be- yond the target performances values, a weighted cost function (3.6) is being used giving each evaluation a satisfying degree (rank) of a candidate solution related to the desired specification. It privileges solutions with maximum satisfied specifica- tions and distinguishes the best solution, as the one that minimizes the difference between achieved performance values and specified target value.
Table 3.6 Normalization overview Table 3.6 gives an overview of the two different types of normalization applied n GENOM.
Table 3.6 Normalization overview Table 3.6 gives an overview of the two different types of normalization applied n GENOM.
Table 3.7 Sampling criteria
Table 3.7 Sampling criteria
Fig. 3.11 (a) Search space decomposition (b) Search space contour and chromosome location In a parallel environment, the master processor after decomposing the search space in small subspaces assigns to each slave processor the execution of one sub- space optimization task. The slave task, executes one independent sequential GA of a unique search subspace. Then, the best chromosomes, from each slave proc- essor run, are transferred to the global optimization array in the Master processor. Finally, when all the optimization sub-tasks are completed and the global optimi- zation array is full with the best overall chromosomes from all search space, the Master processor executes a final global optimization task having those chromo- somes as the initial population.
Fig. 3.11 (a) Search space decomposition (b) Search space contour and chromosome location In a parallel environment, the master processor after decomposing the search space in small subspaces assigns to each slave processor the execution of one sub- space optimization task. The slave task, executes one independent sequential GA of a unique search subspace. Then, the best chromosomes, from each slave proc- essor run, are transferred to the global optimization array in the Master processor. Finally, when all the optimization sub-tasks are completed and the global optimi- zation array is full with the best overall chromosomes from all search space, the Master processor executes a final global optimization task having those chromo- somes as the initial population.
Fig. 3.15 Ideal pair using satisfiability constraints (masks genes) Fig. 3.14 The GENOM Constraint-based Selection scheme
Fig. 3.15 Ideal pair using satisfiability constraints (masks genes) Fig. 3.14 The GENOM Constraint-based Selection scheme
Fig. 3.19 Heuristics associated to the mutation operator
Fig. 3.19 Heuristics associated to the mutation operator
Fig. 3.24 Expected distributed processing speed-up tested with GENOM transfers another evaluation task to the free slaves, as soon as, they finish their tasks. The expected speed-up of the proposed parallel method, for expensive fit- ness evaluations, can increase nearly linear along with the number of used slave processors [26],[69],[75]-[76], as depicted in Fig. 3.24. The main advantage of this model resides in increasing the algorithm speed without introducing extra complexity. The results are in conformance with the expected theoretical model given in [26]. The real values are slightly below the linear speed-up reference line due to communications costs. The search space decomposition, described in Sect. 3.3.2, is an additional tech- nique whic h can raise the algorithm performance when used together with paral- lelization. Basically, the master processor after decomposing the search space in small p” problem subspaces, assigns to each slave processor the execution of one subspace o ptimization task and at the end the Master processor executes a final zlobal optimization task having those chromosomes as the initial population. The program code was relatively simple to adapt and it can easily keep the load palance. T he inter-processor data communication overheads produced in this
Fig. 3.24 Expected distributed processing speed-up tested with GENOM transfers another evaluation task to the free slaves, as soon as, they finish their tasks. The expected speed-up of the proposed parallel method, for expensive fit- ness evaluations, can increase nearly linear along with the number of used slave processors [26],[69],[75]-[76], as depicted in Fig. 3.24. The main advantage of this model resides in increasing the algorithm speed without introducing extra complexity. The results are in conformance with the expected theoretical model given in [26]. The real values are slightly below the linear speed-up reference line due to communications costs. The search space decomposition, described in Sect. 3.3.2, is an additional tech- nique whic h can raise the algorithm performance when used together with paral- lelization. Basically, the master processor after decomposing the search space in small p” problem subspaces, assigns to each slave processor the execution of one subspace o ptimization task and at the end the Master processor executes a final zlobal optimization task having those chromosomes as the initial population. The program code was relatively simple to adapt and it can easily keep the load palance. T he inter-processor data communication overheads produced in this
Fig. 3.25 Theoretical speedup of GAs with Npop = 100
Fig. 3.25 Theoretical speedup of GAs with Npop = 100
Table 3.9 Overview of the common used attributes in GENOM and EAs
Table 3.9 Overview of the common used attributes in GENOM and EAs
Fig. 3.26 Performance specification violation arouse from operational circuit deviations One of the major challenges facing semiconductor companies today is how to in- crease yield. There are many factors that affect yield. Here, this focus is given mainly to those related to process, temperature and supply voltage variations in- herent to any IC design environment and fabrication process. A corner point, as seen by an IC designer, is a combination of a particular technological model de- scribing some process variations with a particular operating context representing some combination of operating conditions. The corner analysis represents the cir- cuit performance analysis for all the combinations of extreme corner points as il- lustrated in Fig. 3.26. Corners simulation is perhaps the most widely and less time-consuming method used to test process, temperature and voltage variations. Usually, a designer de- termines the worst case corners, or conditions, under which the circuit or system is expected to function and these are the minimum requirements to produce a robust design. This important requirement was taken into consideration in the develop- ment of GENOM optimization methodology. ee ee 1 my "
Fig. 3.26 Performance specification violation arouse from operational circuit deviations One of the major challenges facing semiconductor companies today is how to in- crease yield. There are many factors that affect yield. Here, this focus is given mainly to those related to process, temperature and supply voltage variations in- herent to any IC design environment and fabrication process. A corner point, as seen by an IC designer, is a combination of a particular technological model de- scribing some process variations with a particular operating context representing some combination of operating conditions. The corner analysis represents the cir- cuit performance analysis for all the combinations of extreme corner points as il- lustrated in Fig. 3.26. Corners simulation is perhaps the most widely and less time-consuming method used to test process, temperature and voltage variations. Usually, a designer de- termines the worst case corners, or conditions, under which the circuit or system is expected to function and these are the minimum requirements to produce a robust design. This important requirement was taken into consideration in the develop- ment of GENOM optimization methodology. ee ee 1 my "
Fig. 3.27 Circuit/System optimization methodology Next, the required design goals, the circuit design constraints and the type of op- timization procedure must be appropriately specified. In case of a circuit design optimization with corner analysis, the information like process and operation vari- ations to be used, and their associated weight, should also be described. Finally, the job is executed in a single machine or in a distributed environment using the built-in distributed processing capability described in [69] and sub-Sect. 5.2.4.
Fig. 3.27 Circuit/System optimization methodology Next, the required design goals, the circuit design constraints and the type of op- timization procedure must be appropriately specified. In case of a circuit design optimization with corner analysis, the information like process and operation vari- ations to be used, and their associated weight, should also be described. Finally, the job is executed in a single machine or in a distributed environment using the built-in distributed processing capability described in [69] and sub-Sect. 5.2.4.
The tree representation helps to identify the important factors of the problem (the nodes) and how these factors have been affecting the outcomes of the deci- sion in the past. The final decision is found in one of the leaf nodes at the bottom of the tree, after traveling from the root at the top and traversing several sub-nodes according to some test execution in each sub-node. The decision trees are mostly used for classification. The graphical representation is an attractive characteristic because it is easy to understand, which makes this technique become one of the most popular tools for data mining problems. variables. Therefore, more sophisticated algorithms are used for these cases such is, logistic regression, decision trees, neural nets and support vector machines. Neural networks (NN) [3-8] are inspired on an early model of human brain unction, whereas support vector machines (SVM) had their inspiration on the sta- istical learning theory [9]. Both have proven great efficiency either in classifica- ion as in regression type of problems. They require the configuration of model yarameters in order to be efficient. The input for these models is limited to nu- nerical data and the output is essentially predictive, i.e., they were designed to yuild models to forecast future behaviors but do not have mechanisms to summa- ize data and highlight their interesting properties. Due to this behavior, they are yften referred to as "black box" technologies. Generally, the training of these nodels can be time consuming, although the predictions for new values are proc- -ssed very fast. A great advantage of these algorithms is their ability to be used as in arbitrary function approximation constructed from past observations. This as- yect is particularly useful in complex and expensive data analysis functions or ven in situations where there is no defined function, but only a set of samples. \lthough both NN and SVM have common characteristics, they differ radically in yne important aspect: SVM training always finds a global minimum [9]. The decision tree is a technique in which the resulting model is represented by eenremiknie ofmintiera: in a facem afl teen ime mvrarinat mt theic -ramracanitintimm ita -iallac_
The tree representation helps to identify the important factors of the problem (the nodes) and how these factors have been affecting the outcomes of the deci- sion in the past. The final decision is found in one of the leaf nodes at the bottom of the tree, after traveling from the root at the top and traversing several sub-nodes according to some test execution in each sub-node. The decision trees are mostly used for classification. The graphical representation is an attractive characteristic because it is easy to understand, which makes this technique become one of the most popular tools for data mining problems. variables. Therefore, more sophisticated algorithms are used for these cases such is, logistic regression, decision trees, neural nets and support vector machines. Neural networks (NN) [3-8] are inspired on an early model of human brain unction, whereas support vector machines (SVM) had their inspiration on the sta- istical learning theory [9]. Both have proven great efficiency either in classifica- ion as in regression type of problems. They require the configuration of model yarameters in order to be efficient. The input for these models is limited to nu- nerical data and the output is essentially predictive, i.e., they were designed to yuild models to forecast future behaviors but do not have mechanisms to summa- ize data and highlight their interesting properties. Due to this behavior, they are yften referred to as "black box" technologies. Generally, the training of these nodels can be time consuming, although the predictions for new values are proc- -ssed very fast. A great advantage of these algorithms is their ability to be used as in arbitrary function approximation constructed from past observations. This as- yect is particularly useful in complex and expensive data analysis functions or ven in situations where there is no defined function, but only a set of samples. \lthough both NN and SVM have common characteristics, they differ radically in yne important aspect: SVM training always finds a global minimum [9]. The decision tree is a technique in which the resulting model is represented by eenremiknie ofmintiera: in a facem afl teen ime mvrarinat mt theic -ramracanitintimm ita -iallac_
The next group of techniques has its origin in the Naive-Bayes algorithm whic uses the computation of probabilities as the main tool to make predictions. Naive Bayes is a classification technique that is not only predictive but also owns a de scriptive feedback that describes the basic features and the interesting propertie of the data. This approach assumes the statistically independence of all the inde pendent variables which may not be true and is tailored to deal with categoric< problems. The categorical limitation can be overcome to handle continuous dat using bracket techniques that determine categories defined by limits of continuou data. Although technically simple to implement, the selection of the ranges ca have a dramatic impact on the quality of the final model. The Naive-Bayes cor Sept is based on the relationship between dependent and independent variables an because the perrormance Of the model depends on it. K-means [10] is one of the simplest unsupervised learning algorithms tailored to solve the clustering problems. It is used to classify data, following a procedure that groups a given data set through a certain number of clusters (assume k clus- ters or subsets) defined by the user. The grouping routine minimizes the sum of squares of distances between data and the corresponding cluster centroid. When all samples have been assigned to a group which has the closest centroid, the algo- rithm recalculates the positions of the K centroids and repeats the process until the centroids get a stationary phase. Despite the simplicity, the k-means algorithm is also significantly sensitive to the initial randomly selected cluster centers and sometimes misses to find the most optimal configuration related to the global ob- jective function minimization expressed in Fig. 4.5.
The next group of techniques has its origin in the Naive-Bayes algorithm whic uses the computation of probabilities as the main tool to make predictions. Naive Bayes is a classification technique that is not only predictive but also owns a de scriptive feedback that describes the basic features and the interesting propertie of the data. This approach assumes the statistically independence of all the inde pendent variables which may not be true and is tailored to deal with categoric< problems. The categorical limitation can be overcome to handle continuous dat using bracket techniques that determine categories defined by limits of continuou data. Although technically simple to implement, the selection of the ranges ca have a dramatic impact on the quality of the final model. The Naive-Bayes cor Sept is based on the relationship between dependent and independent variables an because the perrormance Of the model depends on it. K-means [10] is one of the simplest unsupervised learning algorithms tailored to solve the clustering problems. It is used to classify data, following a procedure that groups a given data set through a certain number of clusters (assume k clus- ters or subsets) defined by the user. The grouping routine minimizes the sum of squares of distances between data and the corresponding cluster centroid. When all samples have been assigned to a group which has the closest centroid, the algo- rithm recalculates the positions of the K centroids and repeats the process until the centroids get a stationary phase. Despite the simplicity, the k-means algorithm is also significantly sensitive to the initial randomly selected cluster centers and sometimes misses to find the most optimal configuration related to the global ob- jective function minimization expressed in Fig. 4.5.
Table 4.1 Classification of data mining techniques
Table 4.1 Classification of data mining techniques
The SVM learning algorithm finds the optimal separating hyperplane (OSH) that maximizes the distance between the decision boundary between the two class groups and the closest point to the boundary, known as the margin, as illustrated in Fig. 4.7. The decision boundary points overlapping the margins are called support vectors. Support vectors are the most relevant in the decision process. The separat- ing hyperplane in the feature space can correspond to a nonlinear decision bound- ary in the original input space. A more extended background on SVM concepts, issues and formulation, is presented in Appendix D. SVMs belong to a class of supervised learning algorithms which are able to ac- quire knowledge from previous experiences and to apply the knowledge to predict future values [1],[9], [11-12]. This process is known as memorization and gener- alization. The modeling presented here is based on a supervising SVM approach to the two-class classification problem, where a set of training data of the form S={(x;; y;j),--.(Xn° Yn)} is observed, and the input x; ©X CR‘ is a d-dimensional feature vector and the output y;& {+1,-1} is the class label of x;. The main goal is to train a discriminate function, which will be used to predict the labels for new inputs, minimizing the probability of classification errors. Generally, the support vector classifier is implemented in a two step process.
The SVM learning algorithm finds the optimal separating hyperplane (OSH) that maximizes the distance between the decision boundary between the two class groups and the closest point to the boundary, known as the margin, as illustrated in Fig. 4.7. The decision boundary points overlapping the margins are called support vectors. Support vectors are the most relevant in the decision process. The separat- ing hyperplane in the feature space can correspond to a nonlinear decision bound- ary in the original input space. A more extended background on SVM concepts, issues and formulation, is presented in Appendix D. SVMs belong to a class of supervised learning algorithms which are able to ac- quire knowledge from previous experiences and to apply the knowledge to predict future values [1],[9], [11-12]. This process is known as memorization and gener- alization. The modeling presented here is based on a supervising SVM approach to the two-class classification problem, where a set of training data of the form S={(x;; y;j),--.(Xn° Yn)} is observed, and the input x; ©X CR‘ is a d-dimensional feature vector and the output y;& {+1,-1} is the class label of x;. The main goal is to train a discriminate function, which will be used to predict the labels for new inputs, minimizing the probability of classification errors. Generally, the support vector classifier is implemented in a two step process.
yperating conditions and process variations [16]. A generalized view of the sizing rules methodology points to the use of ine- juality constraints on electrical parameters (voltages and currents) in order to en- sure the correct circuit operation. For example, [14],[17] introduces the concept of unctional constraints and applies this concept to a simple CMOS current mirror. functional constraints are a set of additional specifications defined analytically with a strong dependence on the application and the technology as illustrated in tig. 4.8. This approach can be extended to other sub-circuits in order to determine 1 set of functional constraints. DELIGHT.SPICE [18] and the FRIDGE [19] tools vere the first to take into account these concepts. In summary, the sizing rules methodology imposes some constraints not only in the design space, formed by the device sizes, but also in the functional space. In this context, the search space is decomposed in design space and functional space as illustrated in Fig. 4.9.
yperating conditions and process variations [16]. A generalized view of the sizing rules methodology points to the use of ine- juality constraints on electrical parameters (voltages and currents) in order to en- sure the correct circuit operation. For example, [14],[17] introduces the concept of unctional constraints and applies this concept to a simple CMOS current mirror. functional constraints are a set of additional specifications defined analytically with a strong dependence on the application and the technology as illustrated in tig. 4.8. This approach can be extended to other sub-circuits in order to determine 1 set of functional constraints. DELIGHT.SPICE [18] and the FRIDGE [19] tools vere the first to take into account these concepts. In summary, the sizing rules methodology imposes some constraints not only in the design space, formed by the device sizes, but also in the functional space. In this context, the search space is decomposed in design space and functional space as illustrated in Fig. 4.9.
proper operation of the analog circuits. 4.2.2 Methodology Overview
proper operation of the analog circuits. 4.2.2 Methodology Overview
Fig. 4.10 Optimization-Based methods architecture
Fig. 4.10 Optimization-Based methods architecture
Fig. 4.12 Estimated fitness function with SVM performance model
Fig. 4.12 Estimated fitness function with SVM performance model
Fig. 4.13 Ids-Vds characteristic of short channel NMOS transistor
Fig. 4.13 Ids-Vds characteristic of short channel NMOS transistor
Fig. 4.15 Expected balance effect in design space Unbalanced data problems impose some difficulties to 22]. The main pointed reasons are that most current c the classifier task [12], assifier systems like SVM tend to optimize the overall accuracy without considering the weight of re distribution of each class and they are designed to generalize from sample data to avoid the noise. The GENOM SVM kernel addresses t lems by automatically employing a novel 3-step samp he unbalanced design analog circuit design. First, it implements an over-sampling in the infeasib gion in order to increase the samples of the minority c [21- ative prob- ing mechanism adjusted to e re- ass, next refine the frontier between the feasible and infeasible region and finally in the third step, reduce the majority class, by removing those samples far away from the feasibility regions. The estimated effect is illustrated in Fig. 4.15.
Fig. 4.15 Expected balance effect in design space Unbalanced data problems impose some difficulties to 22]. The main pointed reasons are that most current c the classifier task [12], assifier systems like SVM tend to optimize the overall accuracy without considering the weight of re distribution of each class and they are designed to generalize from sample data to avoid the noise. The GENOM SVM kernel addresses t lems by automatically employing a novel 3-step samp he unbalanced design analog circuit design. First, it implements an over-sampling in the infeasib gion in order to increase the samples of the minority c [21- ative prob- ing mechanism adjusted to e re- ass, next refine the frontier between the feasible and infeasible region and finally in the third step, reduce the majority class, by removing those samples far away from the feasibility regions. The estimated effect is illustrated in Fig. 4.15.
Fig. 4.16 Stratified vision of the search space by feasibility regions Cal Gls diways Ule last sdlples OL WIE set. Then, in the third step, a balanced SVM two class classifier model is finally built with the train data set, Ts being the union of the three final sets Fs, Bs and Is (Ts = Fs U Bs UIs) where the set of positive samples is given by Fs+Bs and Is is associated with the negative set. After that, the model is used to further generate new interior points of the feasibility region and neighborhood. Only the samples classified as positives will be evaluated by the true fitness function. In the end, the model is updated for the last time and the job is returned to the main process where it will be used together with an evolutionary algorithm to find the solution to the analog circuit design problem.
Fig. 4.16 Stratified vision of the search space by feasibility regions Cal Gls diways Ule last sdlples OL WIE set. Then, in the third step, a balanced SVM two class classifier model is finally built with the train data set, Ts being the union of the three final sets Fs, Bs and Is (Ts = Fs U Bs UIs) where the set of positive samples is given by Fs+Bs and Is is associated with the negative set. After that, the model is used to further generate new interior points of the feasibility region and neighborhood. Only the samples classified as positives will be evaluated by the true fitness function. In the end, the model is updated for the last time and the job is returned to the main process where it will be used together with an evolutionary algorithm to find the solution to the analog circuit design problem.
AIDA Fig. 5.1 Conceptual view of AIDA environment architecture
AIDA Fig. 5.1 Conceptual view of AIDA environment architecture
Fig. 5.3 GUI facility implemented in AIDA
Fig. 5.3 GUI facility implemented in AIDA
The integration of the layout CAD tool in AIDA framework will allow the inclu- sion of extracted layout parasitics and circuit reliability design rules, to be taken into account during the design process. The design process now supports the com- pensation of layout parasitics implementing an iterative loop, involving circuit siz- ing and the layout generation. Hence, the conformity of analog design specification will be verified taken into account the parasitics of physical implementation.
The integration of the layout CAD tool in AIDA framework will allow the inclu- sion of extracted layout parasitics and circuit reliability design rules, to be taken into account during the design process. The design process now supports the com- pensation of layout parasitics implementing an iterative loop, involving circuit siz- ing and the layout generation. Hence, the conformity of analog design specification will be verified taken into account the parasitics of physical implementation.
Fig. 5.5 E-Design environment architecture
Fig. 5.5 E-Design environment architecture
Fig. 5.6 Conceptual view of the Input/Output from optimizer tool
Fig. 5.6 Conceptual view of the Input/Output from optimizer tool
Fig. 5.8 Topology Selection
Fig. 5.8 Topology Selection
Fig. 5.16 Progress reports
Fig. 5.16 Progress reports
Fig. 5.17 Performance reports from optimization Process info: This is the union of several statistical metrics gathered from opti- mization (Fig. 5.16). It includes a huge amount of statistics data about runs, yenerations, evaluations and time. This data is spread in several thematic files, in- cluding the evolution report file, corners file, bode plot file, etc. Optionally, the iser can dispatch this info to screen reports for “online” validation purpose as it will be discussed in the next section. Tasieas we: Tins [RSs Akiko eemmcela te: thee thea] sweeelen Dem eh wet netewm samme
Fig. 5.17 Performance reports from optimization Process info: This is the union of several statistical metrics gathered from opti- mization (Fig. 5.16). It includes a huge amount of statistics data about runs, yenerations, evaluations and time. This data is spread in several thematic files, in- cluding the evolution report file, corners file, bode plot file, etc. Optionally, the iser can dispatch this info to screen reports for “online” validation purpose as it will be discussed in the next section. Tasieas we: Tins [RSs Akiko eemmcela te: thee thea] sweeelen Dem eh wet netewm samme
Fig. 5.18 Progress reports provided by the automation prototype Interactive design is an extended capability introduced to GENOM framework that allows an experienced designer to incorporate some basic knowledge about a cir- cuit during the search process. With the feedback acquired from real-time progress reports, for example, comparing the initial specs against current measured results and taking into account the present context status of the optimization process (state of design variables, evolution curve, constraints violation and corners satis- faction, etc.), the designer can use his knowledge or intuition to change the dynamic ranges of design parameters, set fixed values to genes of the current population (affix some genes of chromosome), etc, which shifts the course of op- timization. Keeping constant values in some design variables has the effect of re- ducing the number of search variables. One equivalent variation of this approach is done by the matching of some strategic transistors such as, the differential pairs, current mirrors, etc., and in some non-sensitive transistors because they do not have much impact on the functionality of the circuit. Both measures result in the
Fig. 5.18 Progress reports provided by the automation prototype Interactive design is an extended capability introduced to GENOM framework that allows an experienced designer to incorporate some basic knowledge about a cir- cuit during the search process. With the feedback acquired from real-time progress reports, for example, comparing the initial specs against current measured results and taking into account the present context status of the optimization process (state of design variables, evolution curve, constraints violation and corners satis- faction, etc.), the designer can use his knowledge or intuition to change the dynamic ranges of design parameters, set fixed values to genes of the current population (affix some genes of chromosome), etc, which shifts the course of op- timization. Keeping constant values in some design variables has the effect of re- ducing the number of search variables. One equivalent variation of this approach is done by the matching of some strategic transistors such as, the differential pairs, current mirrors, etc., and in some non-sensitive transistors because they do not have much impact on the functionality of the circuit. Both measures result in the
Fig. 5.19 Local area multi-computer system implemented with LAM-MPI The MPI interface block illustrated in Fig. 3.24 is composed by two independent types of communications. The hierarchical level interface is dedicated to future in- tegration with LAYGEN tool. The network communication interface implements a local area multi-computer LAM-MPI interface (Fig. 5.19) used in the development of parallel applications over a network of heterogeneous computers as described in sub-Sect. 3.3.7.
Fig. 5.19 Local area multi-computer system implemented with LAM-MPI The MPI interface block illustrated in Fig. 3.24 is composed by two independent types of communications. The hierarchical level interface is dedicated to future in- tegration with LAYGEN tool. The network communication interface implements a local area multi-computer LAM-MPI interface (Fig. 5.19) used in the development of parallel applications over a network of heterogeneous computers as described in sub-Sect. 3.3.7.
Fig. 5.20 Testing GENOM distributed environment The latter script verifies if the optimization tool, as well as, the evaluation en- gine are available in a specified processing node by trying to execute an applica- tion, e.g.”genom” and “hspice”, on all nodes. The last test verifies if the secure “SSH” communications is configured to avoid passwords. If the test is successful, proceed with next sequence of commands to initiate the execution of parallel ap- plication, the “genom” in the example illustrated in Fig. 5.21.
Fig. 5.20 Testing GENOM distributed environment The latter script verifies if the optimization tool, as well as, the evaluation en- gine are available in a specified processing node by trying to execute an applica- tion, e.g.”genom” and “hspice”, on all nodes. The last test verifies if the secure “SSH” communications is configured to avoid passwords. If the test is successful, proceed with next sequence of commands to initiate the execution of parallel ap- plication, the “genom” in the example illustrated in Fig. 5.21.
Fig. 5.24 Interface between GENOM and AIDA design automation environment. target, allowing a much easier debugging as well as reading and exporting to other file formats. If the necessary software modules are developed, then the presented system can also be applied to different design environments or can even be inte- grated in wider industrial applications. Fig. 5.24 depicts an excerpt of the configu- ration interface file used by AIDA framework to setup some functionalities of the GENOM tool. The Fig. 5.25 demonstrates a communication interface example resultant fror the <update_reports> parameter specification defined in Fig. 5.24. At specific time intervals pre-defined by the user, it is carried out an update of the reports and the refresh of screen information. In the example above, <update_reports> is set to ‘1’ meaning an update in each generation (see Fig. 5.24 for other options). The infor- mation delivered from the optimization tool intended for visualization purposes is treated by a parser that identifies pairs of keywords or tags (fSpecs.out, fEvolu- tion_Curve.out, fCorners.out, fParameters.out). The information between those keywords is sent to the interface defined by the client (the entity that initiated the optimization order). Fig. 5.25 exemplifies one line of results sent from GENOM The word “fSpec.out’ is reserved and identifies the performance parameters anc the following values have a precise syntax. The first argument specifies the itera- tion of evolutionary algorithm and the next ones are the optimal values for the per- formance in the same order of appearance as in the specs file (“design.spc’’).
Fig. 5.24 Interface between GENOM and AIDA design automation environment. target, allowing a much easier debugging as well as reading and exporting to other file formats. If the necessary software modules are developed, then the presented system can also be applied to different design environments or can even be inte- grated in wider industrial applications. Fig. 5.24 depicts an excerpt of the configu- ration interface file used by AIDA framework to setup some functionalities of the GENOM tool. The Fig. 5.25 demonstrates a communication interface example resultant fror the <update_reports> parameter specification defined in Fig. 5.24. At specific time intervals pre-defined by the user, it is carried out an update of the reports and the refresh of screen information. In the example above, <update_reports> is set to ‘1’ meaning an update in each generation (see Fig. 5.24 for other options). The infor- mation delivered from the optimization tool intended for visualization purposes is treated by a parser that identifies pairs of keywords or tags (fSpecs.out, fEvolu- tion_Curve.out, fCorners.out, fParameters.out). The information between those keywords is sent to the interface defined by the client (the entity that initiated the optimization order). Fig. 5.25 exemplifies one line of results sent from GENOM The word “fSpec.out’ is reserved and identifies the performance parameters anc the following values have a precise syntax. The first argument specifies the itera- tion of evolutionary algorithm and the next ones are the optimal values for the per- formance in the same order of appearance as in the specs file (“design.spc’’).
Fig. 5.26 Optimization kernel configuration file
Fig. 5.26 Optimization kernel configuration file
“GA-SVM”. At least one line should be presented for the correct functioning of GENOM. The command to execute a single optimization in 5 runs and respective simulation result is showed in Fig. 5.27. Each line depicts the run number, #Run, the number of evaluations in each run, #nEvals, final fitness value, #Fitness, simulation time, #wTIME, existence of feasible solution, #FEAS, and existence of a solution, “#SOLUTION’, found at generation, “found_@”. A feasible solution satisfies all de- signer rules but may miss one performance requirement, on contrary, if a solution is found, all designer rules, as well as, all the performance specs are satisfied.
“GA-SVM”. At least one line should be presented for the correct functioning of GENOM. The command to execute a single optimization in 5 runs and respective simulation result is showed in Fig. 5.27. Each line depicts the run number, #Run, the number of evaluations in each run, #nEvals, final fitness value, #Fitness, simulation time, #wTIME, existence of feasible solution, #FEAS, and existence of a solution, “#SOLUTION’, found at generation, “found_@”. A feasible solution satisfies all de- signer rules but may miss one performance requirement, on contrary, if a solution is found, all designer rules, as well as, all the performance specs are satisfied.
Fig. 5.28 The circuit and the parameter tables filled with data from an elliptic filter The preferential method to input all the data specification is through a GUI, oth- erwise the required files have to be manually generated. The GENOM graphical user interface presented in Sect. 5.2.2 inherits some methods of AIDA framework, and, as a result, takes advantage of its technology, namely the data management and data structure used to create and maintain a circuit’s library. A multilayered architecture structure organized in tables with relational data, as illustrated in Fig. 5.28 and Fig. 5.29, is used to store the information concerning the circuits in- troduced through the graphical interface and the data provided by the optimization tool for data visualization. The next screenshots show the input data specification of the filter depicted in Fig. 5.29.
Fig. 5.28 The circuit and the parameter tables filled with data from an elliptic filter The preferential method to input all the data specification is through a GUI, oth- erwise the required files have to be manually generated. The GENOM graphical user interface presented in Sect. 5.2.2 inherits some methods of AIDA framework, and, as a result, takes advantage of its technology, namely the data management and data structure used to create and maintain a circuit’s library. A multilayered architecture structure organized in tables with relational data, as illustrated in Fig. 5.28 and Fig. 5.29, is used to store the information concerning the circuits in- troduced through the graphical interface and the data provided by the optimization tool for data visualization. The next screenshots show the input data specification of the filter depicted in Fig. 5.29.
Fig. 5.29 2nd order Elliptic filter section and performance specs. Essentially, the insertion of a new circuit requires the electrical schematic, a netlist, a technological file, the device parameters, the sub-circuits, the perform- ance parameters and the corresponding measure functions. There are a lot of pa- rameters with different nature associated to a circuit, so all information was arranged (split) in a meaningful storage of well-structured information. The first layer consists in the insertion of elementary data that defines a circuit. The table, at the top of Fig. 5.28, for example, stores the key of circuit identifier (221), the name (Elliptic Filter of 2th Order), the category (Filter, OpAmp, etc) of the cir- cuit, the type of circuit (Circuit, testbench, etc) and the behavior class (Low pass). The design parameter table, at the bottom of the Fig. 5.28, represents the parame- ters table that characterizes each component from the netlist. There is a unique key that identifies each parameter ($239) plus the remainder characteristics and it is associated to the circuit where it belongs (circuited=221). This table is composed by a long list of parameters which includes a field that marks this component for optimization, another one indicates if the component is matched with any other or not (matchComponent) and the correspondent matching value (matchRelation), above others.
Fig. 5.29 2nd order Elliptic filter section and performance specs. Essentially, the insertion of a new circuit requires the electrical schematic, a netlist, a technological file, the device parameters, the sub-circuits, the perform- ance parameters and the corresponding measure functions. There are a lot of pa- rameters with different nature associated to a circuit, so all information was arranged (split) in a meaningful storage of well-structured information. The first layer consists in the insertion of elementary data that defines a circuit. The table, at the top of Fig. 5.28, for example, stores the key of circuit identifier (221), the name (Elliptic Filter of 2th Order), the category (Filter, OpAmp, etc) of the cir- cuit, the type of circuit (Circuit, testbench, etc) and the behavior class (Low pass). The design parameter table, at the bottom of the Fig. 5.28, represents the parame- ters table that characterizes each component from the netlist. There is a unique key that identifies each parameter ($239) plus the remainder characteristics and it is associated to the circuit where it belongs (circuited=221). This table is composed by a long list of parameters which includes a field that marks this component for optimization, another one indicates if the component is matched with any other or not (matchComponent) and the correspondent matching value (matchRelation), above others.
Fig. 5.31 The simulation data management system overview ayout and allow the use of database techniques to query a text file. The principal method of data access involving optimization algorithm and cir- uit simulator take advantage of the plotting facilities generally found in most lectrical simulators. All output variables of interest can be printed in output files ising the command “.PRINT” or equivalent. The data format of the response is enerally organized in tabular form as depicted in Fig. 5.32. It shows the AC char- cteristics of the magnitude of voltage and phase in the output node of a filter for a ‘iven range of frequencies. aaa ice Maa aaa) aaa a In order to access the data in a file, a file parser is implemented (file process block in Fig. 5.31). The use of file parsing techniques allows the extraction of any necessary information and its employment for later processing. GENOM provides built in functions to view the data in graphic mode version (bode plot characteris- tics and the cost function evolution). In command mode version, only the
Fig. 5.31 The simulation data management system overview ayout and allow the use of database techniques to query a text file. The principal method of data access involving optimization algorithm and cir- uit simulator take advantage of the plotting facilities generally found in most lectrical simulators. All output variables of interest can be printed in output files ising the command “.PRINT” or equivalent. The data format of the response is enerally organized in tabular form as depicted in Fig. 5.32. It shows the AC char- cteristics of the magnitude of voltage and phase in the output node of a filter for a ‘iven range of frequencies. aaa ice Maa aaa) aaa a In order to access the data in a file, a file parser is implemented (file process block in Fig. 5.31). The use of file parsing techniques allows the extraction of any necessary information and its employment for later processing. GENOM provides built in functions to view the data in graphic mode version (bode plot characteris- tics and the cost function evolution). In command mode version, only the
Fig. 5.32 AC analysis in the output node of a filter xtracted plotting files are created, allowing its final treatment with external sraphical tools like Avanwaves® [5] or CosmosScope® [5]. The optimization with HSPICE simulator has an extra option that can be automatically invoked to visualize the waveforms in CosmosScope®. The processing of data employing ‘ircuit simulators with the purpose of performance estimation employs the same zeneral principle but will be explained next.
Fig. 5.32 AC analysis in the output node of a filter xtracted plotting files are created, allowing its final treatment with external sraphical tools like Avanwaves® [5] or CosmosScope® [5]. The optimization with HSPICE simulator has an extra option that can be automatically invoked to visualize the waveforms in CosmosScope®. The processing of data employing ‘ircuit simulators with the purpose of performance estimation employs the same zeneral principle but will be explained next.
Fig. 5.33 The performance evaluation data flow Step 3 - Next, a set of built in functions extracts the data information matrix stored in one or more output files and sends it to cache memory structures for fast manipulation. When the required information is not explicit stored, a new built in function is created to compute its value. At the end of this step, all necessary pa- rameters needed to compute the cost function, are organized in memory by the or- der they appeared in targets specs file. Cexnn A Tee Wiese: «hc oocee AasewmeSes: een Teac Sek tant alles aikieeeeeeewd <ecek +b,
Fig. 5.33 The performance evaluation data flow Step 3 - Next, a set of built in functions extracts the data information matrix stored in one or more output files and sends it to cache memory structures for fast manipulation. When the required information is not explicit stored, a new built in function is created to compute its value. At the end of this step, all necessary pa- rameters needed to compute the cost function, are organized in memory by the or- der they appeared in targets specs file. Cexnn A Tee Wiese: «hc oocee AasewmeSes: een Teac Sek tant alles aikieeeeeeewd <ecek +b,
aessaweeren wane, ew OE eR RR Fig. 5.35 gives a simplified macro view of the actions taken automatically by the parser machine to carry out a single performance parameter. When thi “cost_Calc()” function triggers the process, the first line of the design specifica tion file is ready for parser analysis. The expression “(gain_dc>70)” is evaluatec and the identifier “gain_dc” must be resolved first. Since “gain_dc’” expressio1 did not match any of the parser reserved word, it is interpreted as a performanc« parameter whose value should be read from memory with “get_Value_Cache()” Then, the obtained expression ’°90 > 70’ is resolved by executing a set of opera tions specified by the operator ‘>’. One of these operations performs a call to th membership functions that translate the impact of this measure in the overal performance. Then the process is repeated line by line until the end of the targe specification file.
aessaweeren wane, ew OE eR RR Fig. 5.35 gives a simplified macro view of the actions taken automatically by the parser machine to carry out a single performance parameter. When thi “cost_Calc()” function triggers the process, the first line of the design specifica tion file is ready for parser analysis. The expression “(gain_dc>70)” is evaluatec and the identifier “gain_dc” must be resolved first. Since “gain_dc’” expressio1 did not match any of the parser reserved word, it is interpreted as a performanc« parameter whose value should be read from memory with “get_Value_Cache()” Then, the obtained expression ’°90 > 70’ is resolved by executing a set of opera tions specified by the operator ‘>’. One of these operations performs a call to th membership functions that translate the impact of this measure in the overal performance. Then the process is repeated line by line until the end of the targe specification file.
Fig. 5.35 Processing of performance parameters
Fig. 5.35 Processing of performance parameters
Table 6.1 General comparison Simulation and testing of CMOS Opamps involve the measure of several per- formances parameters such as open-loop gain, open-loop frequency response (in- cluding phase margin), input-offset voltage, common-mode gain, common-mode rejection ratio (CMRR), power-supply rejection ratio (PSRR), output resistance, noise, output swing, power dissipation and transient response including slew rate. Operational amplifiers (OpAmps) are the fundamental building blocks of many analog and mixed-signal systems. OpAmps arranged in structures of different lev- els of complexity are used to realize functions ranging from dc bias generation to high speed amplification or filtering. Table 6.1 presents the general characteristics [1] of some of the OpAmps that will be covered in this chapter.
Table 6.1 General comparison Simulation and testing of CMOS Opamps involve the measure of several per- formances parameters such as open-loop gain, open-loop frequency response (in- cluding phase margin), input-offset voltage, common-mode gain, common-mode rejection ratio (CMRR), power-supply rejection ratio (PSRR), output resistance, noise, output swing, power dissipation and transient response including slew rate. Operational amplifiers (OpAmps) are the fundamental building blocks of many analog and mixed-signal systems. OpAmps arranged in structures of different lev- els of complexity are used to realize functions ranging from dc bias generation to high speed amplification or filtering. Table 6.1 presents the general characteristics [1] of some of the OpAmps that will be covered in this chapter.
Fig. 6.1 Testbenches to measure the performances values
Fig. 6.1 Testbenches to measure the performances values
Fig. 6.2 The suite of circuit schematics used in tests
Fig. 6.2 The suite of circuit schematics used in tests
Table 6.2 Class of circuits used in the tests
Table 6.2 Class of circuits used in the tests
(a) Note: all parameters ranges means [min, max, grid size] respectively Table 6.3 Design parameters range Table 6.4 Matching and technology constraints details
(a) Note: all parameters ranges means [min, max, grid size] respectively Table 6.3 Design parameters range Table 6.4 Matching and technology constraints details
Table 6.5 Specifications/requirements
Table 6.5 Specifications/requirements
Table 6.6 Optimization algorithm parameters Some of the common parameters include the initial population size population size (uU=32), elite size (8), initial mutation rate (5%), a 2-pairs tournament- crossover probability in 50% of ut and a normal distribution method for generating the initial population. The stop criterion was here defined as a maximum number of generations or as soon as it reaches the first solution. For this particularly experiments, the SVM meta-parameters were found for the first time model gen- eration and then fixed (regularization parameter C=4, variance o=1/n). A cross validation method [4-6] for optimal parameter selection will execute automatically for each model update.
Table 6.6 Optimization algorithm parameters Some of the common parameters include the initial population size population size (uU=32), elite size (8), initial mutation rate (5%), a 2-pairs tournament- crossover probability in 50% of ut and a normal distribution method for generating the initial population. The stop criterion was here defined as a maximum number of generations or as soon as it reaches the first solution. For this particularly experiments, the SVM meta-parameters were found for the first time model gen- eration and then fixed (regularization parameter C=4, variance o=1/n). A cross validation method [4-6] for optimal parameter selection will execute automatically for each model update.
Table 6.7 Overall performance measures The optimization process considering only typical conditions solved the prob- lem quickly, and spent only a very few generations (from 0 to 8) as seen in Fig. 5.3 to achieve the performance specs satisfying all design constraints (rules). However, in corer optimization the number of generations increases for around 15-20 generations. Since each candidate solution for corner analysis requires 9 SPICE simulations (one simulation for each corner point), a minimum of 2578 and a maximum of 3888 HSPICE simulations were performed taking into account all runs.
Table 6.7 Overall performance measures The optimization process considering only typical conditions solved the prob- lem quickly, and spent only a very few generations (from 0 to 8) as seen in Fig. 5.3 to achieve the performance specs satisfying all design constraints (rules). However, in corer optimization the number of generations increases for around 15-20 generations. Since each candidate solution for corner analysis requires 9 SPICE simulations (one simulation for each corner point), a minimum of 2578 and a maximum of 3888 HSPICE simulations were performed taking into account all runs.
Table 6.8 Output results for each run - Priority to the performance space
Table 6.8 Output results for each run - Priority to the performance space
Table 6.10 Output results for each run — Standard approach
Table 6.10 Output results for each run — Standard approach
In the standard approach, the best-ranked individual will always be the one with the lowest constraints and specs violation in each generation. From the analysis of these results it is verified that the standard ranking approach and the ranking strat- egy that gives priority to the solutions satisfying performances spaces produces the better results in terms of number of generations or computation time. In aver- age, both strategies have similar performances (e.g., the average number of gen- erations is 19.4 and 17.8 respectively), although the standard approach presents worse variances from run to run (13.1 against and 4.8 for the other strategy). For simple circuits like the one used in these experiments there is no apparent benefit in these two approaches.
In the standard approach, the best-ranked individual will always be the one with the lowest constraints and specs violation in each generation. From the analysis of these results it is verified that the standard ranking approach and the ranking strat- egy that gives priority to the solutions satisfying performances spaces produces the better results in terms of number of generations or computation time. In aver- age, both strategies have similar performances (e.g., the average number of gen- erations is 19.4 and 17.8 respectively), although the standard approach presents worse variances from run to run (13.1 against and 4.8 for the other strategy). For simple circuits like the one used in these experiments there is no apparent benefit in these two approaches.
Table 6.11 Output results for each run — Priority to the performance space Table 6.12 Output results for each run — Standard approach
Table 6.11 Output results for each run — Priority to the performance space Table 6.12 Output results for each run — Standard approach
Table 6.13 Performance specifications/requirements Table 6.14 Design parameter specifications (GA-SVM)
Table 6.13 Performance specifications/requirements Table 6.14 Design parameter specifications (GA-SVM)
* Tn a dual processor core AMD at 2400 MHz running Linux OS.
* Tn a dual processor core AMD at 2400 MHz running Linux OS.
Table 6.16 Comparison among different algorithms for Ckt2 Fig. 6.6 and Fig. 6.7 show the electrical characteristics of the final population and some of the output reports from the optimization tool, respectively.
Table 6.16 Comparison among different algorithms for Ckt2 Fig. 6.6 and Fig. 6.7 show the electrical characteristics of the final population and some of the output reports from the optimization tool, respectively.
Table 6.17 Comparison among different algorithms for Ckt4
Table 6.17 Comparison among different algorithms for Ckt4
in one run is presented as an example in Fig. 6.8. The experiments were executed on AMD X64 2.8 GHz dual core machine and used HSPICE to simulate the circuit and extract performance parameters and the public domain LIBSVM tool [7] as the learning engine. Each algorithm was exe- cuted 20 times to acquire the mean and the standard deviation for the evaluation performance. The convergence behavior for the “T'wo-Stage” OpAmp experiment in one run is presented as an example in Fig. 6.8. Analyzing this Fig. and the experimental data displayed in Table 6.16 and Ta- ble 6.17 and Fig. 6.9, it is noticeable the good accuracy and lower variance ob- tained by the GA-MOD and GA-SVM algorithms.
in one run is presented as an example in Fig. 6.8. The experiments were executed on AMD X64 2.8 GHz dual core machine and used HSPICE to simulate the circuit and extract performance parameters and the public domain LIBSVM tool [7] as the learning engine. Each algorithm was exe- cuted 20 times to acquire the mean and the standard deviation for the evaluation performance. The convergence behavior for the “T'wo-Stage” OpAmp experiment in one run is presented as an example in Fig. 6.8. Analyzing this Fig. and the experimental data displayed in Table 6.16 and Ta- ble 6.17 and Fig. 6.9, it is noticeable the good accuracy and lower variance ob- tained by the GA-MOD and GA-SVM algorithms.
Fig. 6.9 Comparative graph for the required number of evaluations
Fig. 6.9 Comparative graph for the required number of evaluations
Table 6.18 Experiments cases
Table 6.18 Experiments cases
Table 6.19 Algorithm specifications under test These experiments use exclusively the two-stage (Ckt4) ampop illustrated in Fig. 6.2, updated with appropriate test benches to allow the measures of the de- sired performances parameters. All experiments used the same computation re- sources, specifications and constraints as earlier and also used the same number of runs to extract the mean and the standard deviation for the evaluation perform- ance. The convergence behavior for the two-stage OpAmp experiment in one run is presented as an example in Fig. 6.10. From the experimental data, displayed from Table 6.20 and Fig. 6.10, it is clear ems senna oinmrrenenxs osnd fev «dEoiemdeewres schi@ndaed <ith obendiarccsac weankadilead «afl.
Table 6.19 Algorithm specifications under test These experiments use exclusively the two-stage (Ckt4) ampop illustrated in Fig. 6.2, updated with appropriate test benches to allow the measures of the de- sired performances parameters. All experiments used the same computation re- sources, specifications and constraints as earlier and also used the same number of runs to extract the mean and the standard deviation for the evaluation perform- ance. The convergence behavior for the two-stage OpAmp experiment in one run is presented as an example in Fig. 6.10. From the experimental data, displayed from Table 6.20 and Fig. 6.10, it is clear ems senna oinmrrenenxs osnd fev «dEoiemdeewres schi@ndaed <ith obendiarccsac weankadilead «afl.
Table 6.20 Comparison among different algorithms is presented as an example in Fig. 0.10. From the experimental data, displayed from Table 6.20 and Fig. 6.10, it is cleat the good accuracy and time efficiency obtained with strategies embedded with SVM models built in offline mode. However, the overhead time to build the static model can be problematic for more complex circuits. Here, the static algorithm takes about 90 seconds approx. to evaluate 3000 uniform samples but in more complex circuits, this number rises considerably. The means and variances to se- tup the models using static modeling were not included in the final statistics given at Table 6.20.
Table 6.20 Comparison among different algorithms is presented as an example in Fig. 0.10. From the experimental data, displayed from Table 6.20 and Fig. 6.10, it is cleat the good accuracy and time efficiency obtained with strategies embedded with SVM models built in offline mode. However, the overhead time to build the static model can be problematic for more complex circuits. Here, the static algorithm takes about 90 seconds approx. to evaluate 3000 uniform samples but in more complex circuits, this number rises considerably. The means and variances to se- tup the models using static modeling were not included in the final statistics given at Table 6.20.
Table 6.21 Performance parameter specifications
Table 6.21 Performance parameter specifications
Table 6.23 Matching and constraints details Table 6.24 Optimization algorithm parameters
Table 6.23 Matching and constraints details Table 6.24 Optimization algorithm parameters
Table 6.25 Performance parameter specifications
Table 6.25 Performance parameter specifications
Fig. 6.12 Testbench for (a) AC and (b) AC Common mode feedback specifications PAE UE LY UAE Ye The simulation results for the main amplifier and cmfb circuit sizing achieved ith the optimization module, and using the HSPICE simulator as the evaluation ngine are presented in Table 6.25 and satisfy all the design requirements. The fi- al transistor dimensions are displayed in Table 6.26. The proper biasing of al ‘MOS transistors are guaranteed once the final solution satisfies all the design pecs and functional constraints for each of the corner points. The computationa mes were included, in Table 6.27, to illustrate the effectiveness of the proposed vstem.
Fig. 6.12 Testbench for (a) AC and (b) AC Common mode feedback specifications PAE UE LY UAE Ye The simulation results for the main amplifier and cmfb circuit sizing achieved ith the optimization module, and using the HSPICE simulator as the evaluation ngine are presented in Table 6.25 and satisfy all the design requirements. The fi- al transistor dimensions are displayed in Table 6.26. The proper biasing of al ‘MOS transistors are guaranteed once the final solution satisfies all the design pecs and functional constraints for each of the corner points. The computationa mes were included, in Table 6.27, to illustrate the effectiveness of the proposed vstem.
Table 6.26 Final transistor dimensions Table 6.27 Runtime info*
Table 6.26 Final transistor dimensions Table 6.27 Runtime info*
Fig. 6.13 Gain magnitudes for corners analysis The next pages show all graphical and numerical results for the AC corner analysis. Fig. 6.13 shows all the gain magnitudes, it is interesting to observe the range of DC gain and GBW; all corner numerical results are reported in Table 6.28 while Table 6.29 shows minimum and maximum values.
Fig. 6.13 Gain magnitudes for corners analysis The next pages show all graphical and numerical results for the AC corner analysis. Fig. 6.13 shows all the gain magnitudes, it is interesting to observe the range of DC gain and GBW; all corner numerical results are reported in Table 6.28 while Table 6.29 shows minimum and maximum values.
Fig. 6.14 Output from simulation where all corners are satisfied
Fig. 6.14 Output from simulation where all corners are satisfied
Table 6.28 Results for corners analysis Table 6.29 Minimum and maximum values for AC corner analysis
Table 6.28 Results for corners analysis Table 6.29 Minimum and maximum values for AC corner analysis
Two critical corner points are pointed in Fig. 6.13. The corner in the bottom (magnitude 0) is achieved by Corner Slow, @125° and in the top by Corner Fast, @125°. To calculate the phase margin is not useful to plot all phases in the same graphic; Fig. 6.15 shows the gain magnitude and phase only for typical mean process and 50° conditions. The dot line depicts the gain magnitude and phase at the common mode output.
Two critical corner points are pointed in Fig. 6.13. The corner in the bottom (magnitude 0) is achieved by Corner Slow, @125° and in the top by Corner Fast, @125°. To calculate the phase margin is not useful to plot all phases in the same graphic; Fig. 6.15 shows the gain magnitude and phase only for typical mean process and 50° conditions. The dot line depicts the gain magnitude and phase at the common mode output.
Table 6.30 First feasible solution performance parameter specifications
Table 6.30 First feasible solution performance parameter specifications
Fig. 6.15 Gain magnitude and phase for typical conditions
Fig. 6.15 Gain magnitude and phase for typical conditions
Table 6.31 Best solution performance parameter specifications
Table 6.31 Best solution performance parameter specifications
Table 6.32 Performance parameter specifications
Table 6.32 Performance parameter specifications
Fig. 6.16 Telecopic OpAmp - Main amplifier and Bias circuitry
Fig. 6.16 Telecopic OpAmp - Main amplifier and Bias circuitry
Table 6.33 Matching and constraints details Table 6.34 explains the rationale behind the achieved constraints values used ir his experiment. In a fully differential amplifier, as the one shown in Fig. 6.16, the implifier can be designed in two symmetrical parts. When one transistor changes value, its mirror also changes. This principle is used for the input differential pair he cascode and load transistors. As for the overdrive voltage and margin, the con- straints are as follows:
Table 6.33 Matching and constraints details Table 6.34 explains the rationale behind the achieved constraints values used ir his experiment. In a fully differential amplifier, as the one shown in Fig. 6.16, the implifier can be designed in two symmetrical parts. When one transistor changes value, its mirror also changes. This principle is used for the input differential pair he cascode and load transistors. As for the overdrive voltage and margin, the con- straints are as follows:
Table 6.34 Matching and constraints details
Table 6.34 Matching and constraints details
Table 6.35 Optimization algorithm parameters Where, SF, TT and FS means the Slow/Fast, Typical/Typical and Fast/Slow rocess, respectively. Instead of using the typical fast and slow device models ets, where all devices are supposed to be fast or slow, a mixture of slow nMOS levices and fast pMOS is here considered, for example purposes, namely the >F, TT and FS meaning the Slow/Fast, Typical/Typical and Fast/Slow process, espectively.
Table 6.35 Optimization algorithm parameters Where, SF, TT and FS means the Slow/Fast, Typical/Typical and Fast/Slow rocess, respectively. Instead of using the typical fast and slow device models ets, where all devices are supposed to be fast or slow, a mixture of slow nMOS levices and fast pMOS is here considered, for example purposes, namely the >F, TT and FS meaning the Slow/Fast, Typical/Typical and Fast/Slow process, espectively.
Table 6.37 Performance parameter specifications Table 6.38 Final transistor dimensions
Table 6.37 Performance parameter specifications Table 6.38 Final transistor dimensions
Note: MOc belongs to Bias and have the same value that MOa and MOb.
Note: MOc belongs to Bias and have the same value that MOa and MOb.
Fig. 6.17 Telescopic OpAmp - Testbench for DC and AC specifications
Fig. 6.17 Telescopic OpAmp - Testbench for DC and AC specifications
Table 6.39 Numerical results for corner analysis Table 6.40 Minimum and maximum values for AC corner analysis
Table 6.39 Numerical results for corner analysis Table 6.40 Minimum and maximum values for AC corner analysis
Fig. 6.18 Gain magnitude and phase for typical conditions
Fig. 6.18 Gain magnitude and phase for typical conditions
The resolution for this problem was achieved using an iterative process very similar to the traditional analog design. In a first attempt to solve the problem, it was observed that one of the corners in particular was very difficult to satisfy. This corner was identified by the inspection of the run-time information returned from simulation and provided by the tool. This critical corner point (corner n°3) is pointed in Fig. 6.19. The simulation was interrupted and the static weight for that corner was changed as shown in Fig. 6.20, and the simulation was rerun again. Finally it was possible to obtain several solutions within the original time constraint. Taking into consideration the type of optimization evolved in this experiment the corner optimization of 16 optimization variables and 24 constraints, the op timization algorithm solves the problem with efficiency. In this experiment thi two step evolutionary algorithm was used, which increases the computation effi ciency as shown in Table 6.41, once the optimization algorithm achieves | promising solution using the typical optimization. After that, the optimizatio: follows the corner analysis process. The switch between these two steps is whe! five solutions are found by the typical process, in such a way that the populatio: is moderately populated with promising samples. This approach increases th computation efficiency once the same problem was not able to produce a feasi ble solution, within the same time constraint, when a single corner optimizatio! was considered. The first feasible solution satisfying all corners was achieved ii generation 102.
The resolution for this problem was achieved using an iterative process very similar to the traditional analog design. In a first attempt to solve the problem, it was observed that one of the corners in particular was very difficult to satisfy. This corner was identified by the inspection of the run-time information returned from simulation and provided by the tool. This critical corner point (corner n°3) is pointed in Fig. 6.19. The simulation was interrupted and the static weight for that corner was changed as shown in Fig. 6.20, and the simulation was rerun again. Finally it was possible to obtain several solutions within the original time constraint. Taking into consideration the type of optimization evolved in this experiment the corner optimization of 16 optimization variables and 24 constraints, the op timization algorithm solves the problem with efficiency. In this experiment thi two step evolutionary algorithm was used, which increases the computation effi ciency as shown in Table 6.41, once the optimization algorithm achieves | promising solution using the typical optimization. After that, the optimizatio: follows the corner analysis process. The switch between these two steps is whe! five solutions are found by the typical process, in such a way that the populatio: is moderately populated with promising samples. This approach increases th computation efficiency once the same problem was not able to produce a feasi ble solution, within the same time constraint, when a single corner optimizatio! was considered. The first feasible solution satisfying all corners was achieved ii generation 102.
Table 6.42 Performance parameter specifications
Table 6.42 Performance parameter specifications
Note: Evaluation Engine by HSPICE simulator. Table 6.45 Optimization algorithm parameters
Note: Evaluation Engine by HSPICE simulator. Table 6.45 Optimization algorithm parameters
Table 6.43 Matching and constraints details Table 6.44 Comers analysis data
Table 6.43 Matching and constraints details Table 6.44 Comers analysis data
Table 6.46 - Performance parameter specifications
Table 6.46 - Performance parameter specifications
Fig. 6.23 OpAmp testbench for DC and AC specifications
Fig. 6.23 OpAmp testbench for DC and AC specifications
Table 6.47 Final transistor dimensions Design Problem
Table 6.47 Final transistor dimensions Design Problem
* In a single processor Intel(R) Core(TM)2 Quad CPU Q6600 @ 2.40GHz PC running Linux.
* In a single processor Intel(R) Core(TM)2 Quad CPU Q6600 @ 2.40GHz PC running Linux.
Table 6.49 Numerical results for corners analysis
Table 6.49 Numerical results for corners analysis
Fig. 6.25 Gain magnitude and phase for typical conditions Fig. 6.26 shows the gain magnitude and phase only for typical mean process and 50° C conditions. Fig. 6.26 shows the graphical results for the AC corner analysis. As it can be noticed, this simulation design meets the required specs re- lated to DC gain, gain bandwidth and phase margin satisfying all corner points as reported in Table 6.49. Table 6.50 shows the maximum and minimum of the cor- ner points.
Fig. 6.25 Gain magnitude and phase for typical conditions Fig. 6.26 shows the gain magnitude and phase only for typical mean process and 50° C conditions. Fig. 6.26 shows the graphical results for the AC corner analysis. As it can be noticed, this simulation design meets the required specs re- lated to DC gain, gain bandwidth and phase margin satisfying all corner points as reported in Table 6.49. Table 6.50 shows the maximum and minimum of the cor- ner points.
Table 6.50 Minimum and maximum values for AC corners analysis
Table 6.50 Minimum and maximum values for AC corners analysis
Table 6.51 Optimization algorithm parameters
Table 6.51 Optimization algorithm parameters
Fig. 6.28 OpAmp testbench for DC and AC specifications
Fig. 6.28 OpAmp testbench for DC and AC specifications
Table 6.52 Design performance and final results The main performance spec gbw stands for gainbandwidth, gain means the dc gain, pm is the phase margin, sr is the slew rate and the optimization goal is to mi- nimize both the area (Area) and power dissipation (power). Both, the optimization soals and constraints used in the experiments were defined by the original bench- mark circuit. The electrical constraints, as defined by the original benchmark cir- cuit, are illustrated in HPSICE style in expression (6.3):
Table 6.52 Design performance and final results The main performance spec gbw stands for gainbandwidth, gain means the dc gain, pm is the phase margin, sr is the slew rate and the optimization goal is to mi- nimize both the area (Area) and power dissipation (power). Both, the optimization soals and constraints used in the experiments were defined by the original bench- mark circuit. The electrical constraints, as defined by the original benchmark cir- cuit, are illustrated in HPSICE style in expression (6.3):
Table 6.53 Ranges and Final Transistor Dimensions
Table 6.53 Ranges and Final Transistor Dimensions
Fig. 6.29 Gain magnitude and phase for typical conditions
Fig. 6.29 Gain magnitude and phase for typical conditions
Table 6.56 Design performance and final results for corners analysis
Table 6.56 Design performance and final results for corners analysis
Fig. A.1 Conceptual view of design spaces adopt in the terminology
Fig. A.1 Conceptual view of design spaces adopt in the terminology
In essence, they simply consist of selecting randomly potential solutions and evaluating them. They do not use any heuristics (or meta-heuristics) to guide the next potential solution, so the search is very slow. The best solution over a number of samples is the result of “pure” random search, p.e., the Monte Carlo (MC) me- thod. In spite of being considered the weakest of all optimization methods, random search methods have some visibility once they are often used as a reference tool. One of the first improvements to random search is given by the simple Hill Climber algorithm (Fig. B.1) and is applied to non-linear unconstrained problems.
In essence, they simply consist of selecting randomly potential solutions and evaluating them. They do not use any heuristics (or meta-heuristics) to guide the next potential solution, so the search is very slow. The best solution over a number of samples is the result of “pure” random search, p.e., the Monte Carlo (MC) me- thod. In spite of being considered the weakest of all optimization methods, random search methods have some visibility once they are often used as a reference tool. One of the first improvements to random search is given by the simple Hill Climber algorithm (Fig. B.1) and is applied to non-linear unconstrained problems.
of 4, and the direction g, can be determined by the Newton method as well as other methods. Each point in the generated sequence has a lower cost than its predecessor. The weakness of this method is that line minimization may be expen- sive and convergence can be too slow for ill-conditioned problems. Also, when the derivative (or an approximation to the derivative) can-not be determined these methods cannot be used.
of 4, and the direction g, can be determined by the Newton method as well as other methods. Each point in the generated sequence has a lower cost than its predecessor. The weakness of this method is that line minimization may be expen- sive and convergence can be too slow for ill-conditioned problems. Also, when the derivative (or an approximation to the derivative) can-not be determined these methods cannot be used.
Fig. B.3 Constraint optimization problem
Fig. B.3 Constraint optimization problem
Fig. B.4 General properties of Stochastic Search algorithms
Fig. B.4 General properties of Stochastic Search algorithms
Fig. B.6 Dominance, non-dominance and Pareto Front in MOO problems The Pareto optimal set is defined as [17]:
Fig. B.6 Dominance, non-dominance and Pareto Front in MOO problems The Pareto optimal set is defined as [17]:
Fig. C.1 illustrates a typical iterative cycle of evolutionary algorithms and the three main mechanisms used to drive evolution forward, namely, reproduction, mutation, and selection. The fundamentals of EAs are based on the existence of a population of individuals that will change dynamically in each generation (each loop cycle) through the influence of operators mimicking the biology cycle of life. The major task of EC techniques and in GA in particular is to compute artificial models simulating an evolutionary process. They differ from more traditional search algorithms in that they work with a population of candidate solutions that will evolve progressively towards a certain goal. Meanwhile the algorithm itera- tively applies probabilistic transformations to the population and uses a selection scheme to obtain an improved population. This goal is to find the best possible approximate solution of a given complex optimization and design problem. The artificial models mimic natural evolution in a simplified way. The three main me- chanisms used to drive evolution forward are depicted in Fig. C.1.
Fig. C.1 illustrates a typical iterative cycle of evolutionary algorithms and the three main mechanisms used to drive evolution forward, namely, reproduction, mutation, and selection. The fundamentals of EAs are based on the existence of a population of individuals that will change dynamically in each generation (each loop cycle) through the influence of operators mimicking the biology cycle of life. The major task of EC techniques and in GA in particular is to compute artificial models simulating an evolutionary process. They differ from more traditional search algorithms in that they work with a population of candidate solutions that will evolve progressively towards a certain goal. Meanwhile the algorithm itera- tively applies probabilistic transformations to the population and uses a selection scheme to obtain an improved population. This goal is to find the best possible approximate solution of a given complex optimization and design problem. The artificial models mimic natural evolution in a simplified way. The three main me- chanisms used to drive evolution forward are depicted in Fig. C.1.
Table C.2 Testbench functions for the GA optimization example A three-dimensional plot of objective functions is shown in Fig. C.3 (a). For these continuous functions, the chromosome is encoded as a vector of two real values x and y. When a new population is created, the next step is to calculate the fitness value of each member in the population. The evaluation of the fitness for each chromosome is performed by Eval(F(x,y)). After the evaluation of the last chromosome a new population is created. The two most fitted individuals are re- produced directly in the next population while the remaining ones will be submit- ted to the standard process variations, crossover and mutations. The chromosomes selected to crossover will be chosen according to the roulette wheel strategy. The
Table C.2 Testbench functions for the GA optimization example A three-dimensional plot of objective functions is shown in Fig. C.3 (a). For these continuous functions, the chromosome is encoded as a vector of two real values x and y. When a new population is created, the next step is to calculate the fitness value of each member in the population. The evaluation of the fitness for each chromosome is performed by Eval(F(x,y)). After the evaluation of the last chromosome a new population is created. The two most fitted individuals are re- produced directly in the next population while the remaining ones will be submit- ted to the standard process variations, crossover and mutations. The chromosomes selected to crossover will be chosen according to the roulette wheel strategy. The
Table C.3 Optimization control parameter configuration The results illustrated in Fig. C.3 b) and c) plots a two dimension view and the -ontour plot of the function under test with the initial population locations denoted dy circles and the final solutions with red stars. Fig. C.4 shows the evolution curve of the best and average fitness across 64 generations for 10 runs of the algorithm. In a typical application the best curve presents a monotonically decreasing shape with respect to generation numbers.
Table C.3 Optimization control parameter configuration The results illustrated in Fig. C.3 b) and c) plots a two dimension view and the -ontour plot of the function under test with the initial population locations denoted dy circles and the final solutions with red stars. Fig. C.4 shows the evolution curve of the best and average fitness across 64 generations for 10 runs of the algorithm. In a typical application the best curve presents a monotonically decreasing shape with respect to generation numbers.
Number generation =10 iterations Fig. C.3 3D, 2D view and the contour plot of the function under test
Number generation =10 iterations Fig. C.3 3D, 2D view and the contour plot of the function under test
Fig. C.4 Illustration of the evolutionary process
Fig. C.4 Illustration of the evolutionary process
Fig. C.6 Example of full and fractional design for three levels experiments
Fig. C.6 Example of full and fractional design for three levels experiments
Fig. C.7 A Latin Hypercube Sample with two variables and eight even intervals sampled using a square grid symmetrically arranged allowing only one sample in each row and each column. In two dimension variables this structure is called a Latin square, as illustrated in Fig. C.7. When extrapolated for multi-dimension spaces, it is called a Latin hypercube where only one sample is admitted in each axis, aligned with the hyper plane containing it.
Fig. C.7 A Latin Hypercube Sample with two variables and eight even intervals sampled using a square grid symmetrically arranged allowing only one sample in each row and each column. In two dimension variables this structure is called a Latin square, as illustrated in Fig. C.7. When extrapolated for multi-dimension spaces, it is called a Latin hypercube where only one sample is admitted in each axis, aligned with the hyper plane containing it.
Fig. D.2 Margin and hyperplane - Mathematical expressions
Fig. D.2 Margin and hyperplane - Mathematical expressions
elements labeled as belonging to the class (i.e. the sum of true positives and false positives, which are items incorrectly labeled as belonging to the class). In the same context, Recall is defined as the number of true positives divided by the total number of elements that actually belong to the class (i.e. the sum of true positives and false negatives).
elements labeled as belonging to the class (i.e. the sum of true positives and false positives, which are items incorrectly labeled as belonging to the class). In the same context, Recall is defined as the number of true positives divided by the total number of elements that actually belong to the class (i.e. the sum of true positives and false negatives).
Fig. D.5 Influence of the hyperparameters on SV regression [46]
Fig. D.5 Influence of the hyperparameters on SV regression [46]
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