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Outline

Title
Abstract
Introduction
Background and Motivation
Wcet Analysis Overview and Related Work
Main Components of Wcet Analysis
Program Flow Analysis
Flow Analysis
Global Low-Level Analysis
Local Low-Level Analysis
Low-Level Analysis
Ipet-Based Calculation Method
Path-Based Calculation Method
Validating Wcet Methods and Tools
Example Analysis Results
Conclusions and Future Work
References
All Topics
Computer Science
Embedded Systems

Worst-case execution-time analysis for embedded real-time systems

Profile image of Jan GustafssonJan Gustafsson

2003

Abstract

This paper gives an overview of the Worst-Case Execution Time (WCET) analysis research performed by the

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Modern Real Time Operating Systems require reducing computational costs even though the microprocessors become more powerful each day. It is usual that Real Time Operating Systems for embedded systems have advance features to administrate the resources of the applications that they support. In order to guarantee either the schedulability of the system or the schedulability of a new task in a dynamic Real Time System, it is necessary to know the Worst Case Response Time of the Real Time tasks during runtime. In this paper a reduced computational cost algorithm is proposed to determine the Worst Case Response Time of Real Time tasks.

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Thesis advisors Precise and Adaptable Worst-Case Execution Time Estimation in Hard Real-Time Systems
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Nowadays real-time systems are omnipresent and embedded systems thrive in a variety of application fields. When they are integrated into safety-critical systems, the verification of their properties becomes a crucial part. Dependability is a primary design goal in environments that use hard real-time systems, whereas general-use microprocessors were designed with a high performance goal. The average-throughput maximization design choice is intrinsically opposed to design goals such as dependability that benefit mostly from highly deterministic architectures without local optimizations. Besides the growth in complexity of the embedded systems, platforms are getting more and more heterogeneous. With regard to the respect of the timing constraints, real-time systems are classified in two categories: hard real-time systems (the non respect of a deadline can lead to catastrophic consequences) and soft real-time systems (missing a deadline can cause performance degradation and material loss). We analyze hard real-time systems that need precise and safe determination of the worst-case execution time bounds in order to be certified. The validation of their non-functional properties is a complex and resource consuming task. One of the main reasons is that currently available solutions focus on delivering precise estimations through tools that are highly dependent on the underlying platform (in order to provide precise and safe results, the architecture of the system must be taken into account). In this thesis we address the above issues by introducing a timing analysis method that maintains a good level of precision while being applicable to a variety of platforms. This adaptability is achieved through separating as much as possible the worst-case execution time (WCET) estimation from the model of the hardware. Our approach consists in the introduction of a new formal modeling language that captures the complex behaviour of modern hardware and is guided by the timing analysis in order to achieve the needed previi viii Abstract cision to scalability tradeoff. The analysis drives a conjoint symbolic execution of the program's binary and the processor model using a dynamic prediction module that decides what states to merge in order to limit the state space explosion. Several state merging algorithms are introduced and applied that can also give an estimation of the introduced precision loss.

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Embedded Real-Time Software (ERTS) must be verified for their timing correctness where knowledge about the Worst-Case Execution Time (WCET) is the building block of such verification. Traditionally, research on the WCET analysis of ERTS assumes sequential code running on single-core platforms. However, as computation is steadily moving towards using a combination of parallel programming and hardware designs, new challenges in WCET analysis need to be addressed. This work derives safe WCET estimates of parallel ERTS using a hybrid approach that combines the flow and timing information of the parallel software. The timing information is obtained via measurement-based analysis by using time-stamped execution traces. The applicability of the proposed method is demonstrated by calculating the WCET estimates of parallel embedded programs in the ParMiBench benchmark suite. The results showed less pessimism in the computed WCET estimates compared to the measured WCET estimates.

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Related topics

  • Computer Science
  • Real Time Embedded Systems
  • Real Time Systems
  • WCET analysis
  • Real Time system
  • Embedded System
  • Hard Real-Time
  • Worst Case Execution Time
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