Embedded Real-Time Software (ERTS) must be verified for their timing correctness where knowledge ... more Embedded Real-Time Software (ERTS) must be verified for their timing correctness where knowledge about the Worst-Case Execution Time (WCET) is the building block of such verification. Traditionally, research on the WCET analysis of ERTS assumes sequential code running on single-core platforms. However, as computation is steadily moving towards using a combination of parallel programming and hardware designs, new challenges in WCET analysis need to be addressed. This work derives safe WCET estimates of parallel ERTS using a hybrid approach that combines the flow and timing information of the parallel software. The timing information is obtained via measurement-based analysis by using time-stamped execution traces. The applicability of the proposed method is demonstrated by calculating the WCET estimates of parallel embedded programs in the ParMiBench benchmark suite. The results showed less pessimism in the computed WCET estimates compared to the measured WCET estimates.
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Papers by Hary Ch