Hard Real-Time

Several servers have been proposed to schedule streams of aperiodic jobs in the presence of other periodic tasks. Standard schedulability analysis has been extended to consider such servers. However, not much attention has been laid on computing the worst-case delay suffered by a given stream of jobs when scheduled via a server. Such analysis is essential for using servers to schedule hard real-time tasks. We illustrate, with examples, that well established resource models, such as supply bound function and models from Real-Time Calculus, do not tightly characterize servers. In this work, we analyze the server algorithm of the Constant Bandwidth Server and compute a provably tight resource model of the server. The approach used enables us to differentiate between the soft and hard variants of the server. A similar approach can be used to characterize other servers; the final results for which are presented.

This paper focuses on the problem of providing efficient run-time support to multimedia applications in a real-time system, where two types of tasks can coexist simultaneously: multimedia soft real-time tasks and hard real-time tasks. Hard tasks are guaranteed based on worst case execution times and minimum interarrival times, whereas multimedia and soft tasks are served based on mean parameters. The paper describes a server-based mechanism for scheduling soft and multimedia tasks without jeopardizing the a priori guarantee of hard real-time activities. The performance of the proposed method is compared with that of similar service mechanisms through extensive simulation experiments and several multimedia applications have been implemented on the HARTIK kernel.

Even though numerous applications use real-time and faster-than-real-time simulation (FRTS), there is no concrete formalism that focuses on planning and execution of the experiment. Having previously introduced a conceptual FRTS methodology, we adopt a widely used real-time system specification method and propose a consistent specification for FRTS systems. This involves the activities (processes) that have to be carried out, data and control flows transferred between processes and simulation experiment specifications. Due to the hard real-time constraints, it is also required to analytically examine timing issues concerning the execution of simulation activities. Based on the specification provided, development of FRTS systems can be realized for diverse domains, by both real-time system and simulation researchers.

We present an off-line methodology of analysis of real-time systems, composed of periodic, precedence and resource constrained real-time tasks. As there is no polynomial optimal scheduling technique for such tasks sets, we present an enumerative method based on the construction of the state graph of a Petri net. The time is modeled by the Petri net through the earliest firing rule.

We present an off-line methodology of analysis of real-time systems, composed of periodic, precedence and resource constrained real-time tasks. As there is no polynomial optimal scheduling technique for such tasks sets, we present an enumerative method based on the construction of the state graph of a Petri net. The time is modeled by the Petri net through the earliest firing rule.

In multicore processors, the execution environment is defined as the environment in which tasks run and it is determined by the hardware resources they get and the workload with which they are executed. Thus, different execution environments lead to different inter-task interferences accessing shared hardware resources due to conflicts with the other corunning tasks, making the WCET estimation of a task dependent on the execution environment in which it runs. Despite such dependency, current partitioned scheduling approaches use a single WCET estimation per task: typically the highest for all execution environments in which a task runs. In this paper we introduce IA 3 : an interference-aware allocation algorithm that considers not a single WCET estimation but a set of WCET estimations per task. IA 3 is based on two novel concepts: the WCET-matrix and the WCET-sensitivity. The former associates every WCET estimation with its corresponding execution environment. The latter measures the impact of changing the execution environment on the WCET estimation. This allows IA 3 to reduce the number of resources required to schedule a given taskset. In particular, our results show that in a four-core processor considering tasksets with a total utilization of 2.9, IA 3 is able to schedule 70% of the tasksets using 3-cores while a classical partitioned approach with a First-Fit Decreasing heuristic is able to schedule only 5% of the tasksets using 3-cores.

Multicore processors (CMPs) represent a good solution to provide the performance required by current and future hard real-time systems. However, it is difficult to compute a tight WCET estimation for CMPs due to interferences that tasks suffer when accessing shared hardware resources. We propose an analyzable JEDEC-compliant DDRx SDRAM memory controller (AMC) for hard real-time CMPs, that reduces the impact of memory interferences caused by other tasks on WCET estimation, providing a predictable memory access time and allowing the computation of tight WCET estimations.

Numerous technical and life cycle cost consideration trends have led to a large increase in the use of commercial, off the shelf (COTS) computing and networking infrastructure in military command and control (C2) applications. Object oriented (OO) real-time middleware, such as RT CORBA, provides the capabilities required for domain specific services and applications. However, it is unproven whether such commercial technologies can achieve the hard real time performance required by many C2 system. Our study reveals that DOC middleware is suitable for some real-time applications when appropriately coupled with operating system and network protocol quality of service (QoS) mechanismsareas in which further progress is still needed. We believe the following forces are accelerating the defense industry toward a new approach to developing high-performance mission-critical systems. In today's increasingly competitive U.S. Department of Defense (DoD) budget climate all programs are being pressured to leverage commercial information technologies to reduce total ownership costs. In parallel, the DoD also wants to improve operational performance, reliability and safety, as well as reduce manning via enhanced automation. These goals are leading to systems with increased functional and implementation complexity, along with increased expectations of predictability. Recent technological advances have increased the raw performance of networks and computing platforms considerably. These performance improvements are complemented by quality of service (QoS) enhancements in networks and computer operating systems and data communications protocols that will enable stricter resource allocation controls. Simultaneously, standardiza-tion efforts, such as CORBA [6] and the Real-time Specification for Java [7], are providing industry-wide, technology neutral architectures for developing objectoriented and/or component-based systems. Independent, standards-based products now exist at each element in the end-to-end distributed processing chain. Ideally, these products can be integrated together to provide an infrastructure for predictably performing software systems. Increasingly, DoD Command and Control (C2) systems are being planned and built upon such an infrastructure, an example of which is shown in Figure .

Industrial manufacturing today requires both an efficient production process and an appropriate quality standard of each produced unit. The number of industrial vision appli- cations, where real time vision systems are utilized, is con- tinuously rising due to the increasing automation. Assem- bly lines, where component parts are manipulated by robot grippers, require a fast and fault tolerant visual detection of objects. Standard computation hardware like PC-based platforms with frame grabber boards are often not appro- priate for such hard real time vision tasks in embedded sys- tems. This is because they meet their limits at frame rates of a few hundreds images per second and show comparatively long latency times of a few milliseconds. This is the result of the largely serial working and time consuming process- ing chain of these systems. In contrast to that we designed an application-specific instruction processor chip which ex- ploits massive parallelization of often used image...

Ad-hoc networks usually support best-effort traffic and occasionally some kind of Quality of Service (QoS). However, there are some applications, which generally involve cooperative control, with hard real-time traffic requirements where strict deadlines must be met. To meet deadlines, the communication network has to support the timely delivery of inter-task messages. This is the case, for example, of applications involving cooperative robot teams, such as those used for rescue tasks in hostile environments, emergencies or disaster recovery, where a wired backbone is infeasible or economically unviable. In this paper, we present RT-WMP, a novel protocol that allows wireless real-time traffic in relatively small mobile ad-hoc networks using the low-cost commercial 802.11 technology. The protocol is based on a token-passing approach and message exchange is priority based. Moreover, support for frequent topology changes is provided through the sharing of a matrix that describes link quality amongst the members of the network.

Failure of a safety-critical application on an embedded processor can lead to severe damage or even loss of life. Here we are concerned with two kinds of failure: stack overflow, which usually leads to runtime errors that are difficult to diagnose, and failure to ...

Fixed-priority scheduling with deferred preemption (FPDS) has been proposed in the literature as a viable alternative to fixed-priority pre-emptive scheduling (FPPS), that obviates the need for non-trivial resource access protocols and reduces the cost of arbitrary preemptions. This paper shows that existing worst-case response time analysis of hard real-time tasks under FPDS, arbitrary phasing and relative deadlines at most equal to periods is pessimistic and/or optimistic. The same problem also arises for fixedpriority non-pre-emptive scheduling (FPNS), being a special case of FPDS. This paper provides revised analysis, resolving the problems with the existing approaches. The analysis is based on known concepts of critical instant and busy period for FPPS. To accommodate for our scheduling model for FPDS, we need to slightly modify existing definitions of these concepts. The analysis assumes a continuous scheduling model, which is based on a partitioning of the timeline in a set of non-empty, right semi-open intervals. It is shown that the critical instant, longest busy period, and worst-case response time for a task are suprema rather than maxima for all tasks, except for the lowest priority task, i.e. that instant, period, and response time cannot be assumed. Moreover, it is shown that the analysis is not uniform for all tasks, i.e. the analysis for the lowest priority task differs from the analysis of the other tasks. To build on earlier work, the worst-case response time analysis for FPDS is expressed in terms of known worst-case analysis results for FPPS. The paper includes pessimistic variants of the analysis, which are uniform for all tasks.

In this paper we present a modification of the Dual Priority Scheduling Algorithm to work on shared memory multiprocessor systems improving the average-case schedulability. The proposal deals with global fixedpriority preemptive scheduling of periodic tasks on identical processors. The algorithm allows to schedule hard real-time periodic tasks using task migration between different processors. Using this approach we are able to schedule task sets that can not be scheduled via traditional partitioning methods. Extensive simulations show that the proposed algorithm gives higher success ratios than previous global scheduling schemes and traditional partitioning methods.

There exist certain systems which generate real-time data at high bandwidth, but do not necessarily require the long-term retention of that data in normal conditions. In some cases, the data may not actually be useful, and in others, there may be too much data to permanently retain in long-term storage whether it is useful or not. However, certain portions of the data may be identified as being vitally important from time to time, and must therefore be retained for further analysis or permanent storage without interrupting the ongoing collection of new data. We have developed a system, Mahanaxar, intended to address this problem. It provides quality of service guarantees for incoming real-time data streams and simultaneous access to already-recorded data on a best-effort basis utilizing any spare bandwidth. It has built in mechanisms for reliability and indexing, can scale upwards to meet increasing bandwidth requirements, and handles both small and large data elements equally well. We will show that a prototype version of this system provides better performance than a flat file (traditional filesystem) based version, particularly with regard to quality of service guarantees and hard real-time requirements.

In real-time task scheduling on multiprocessor systems, partitioning approach has received the attention of many researchers because of its higher least upper bound utilization of safe systems. Semi-partitioning allows some tasks to be split into subtasks and each subtask to be assigned to a different processor. Though task splitting improves the performance of systems, by counting each subtask as a separate task, it increases the effective number of tasks to be scheduled, which in turn, raises the execution overhead. This research is on semi-partitioning of tasks and assigning each partition to a separate processor to be scheduled by the well-known scheduler Rate-Monotonic (RM). Using our algorithm, we do not need to define release time for subtasks of a task to assure their nonconcurrent execution and the number of effective tasks, in turn, is reduced. It is theoretically proven that with the proposed semi-partitioning and RM scheduling algorithm, all processors may safely run their tasks according to their deadlines. Further, experimental results on 3000 randomly generated task-sets indicates that not only is utilization factor boosted, but the number of broken tasks also is decreased.

This paper considers the use of lock-free shared objects within hard r eal-time systems. As the name suggests, lock-free shared objects are distinguished by the fact that they are not locked. As such, they do not give rise to priority inversions, a key advantage over conventional, lock-based object-sharing approaches. Despite this advantage, it is not immediately apparent that lock-free shared objects can be employed if tasks must adhere to strict timing constraints. In particular, lock-free object implementations permit concurrent operations to interfere with each other, and repeated interferences can cause a given operation to take an arbitrarily long time to complete. The main contribution of this paper is to show that such interferences can be b ounded by judicious scheduling. This work pertains to periodic, hard r eal-time tasks that share l o ck-free objects on a uniprocessor. In the rst part of the paper, scheduling conditions are derived for such tasks, for both static and dynamic priority schemes. Based on these conditions, it is formally shown that lock-free object-sharing approaches can be expected to incur much less overhead than approaches based on wait-free objects or lock-based schemes. In the last part of the paper, this conclusion is validated experimentally through work involving a realtime desktop videoconferencing system.

Roll-call polling mechanisms are considered for fieldbus networks. Based on a producer/consumer communication model, two different protocols are presented, namely the standardized FIP (Factory Instrumentation Protocol) and a modified FIP protocol that we propose here. The modified protocol uses redundancy to eliminate local timers used by the FIP protocol. The two protocols are analyzed for efficiency, jitter and robustness. We compare the two protocols based on implementation and analytical results. Practical aspects concerning: clock precision; computing time; and hard real-time constraints are also discussed. The results show that: (1) the original FIP protocol is fractionally more efficient with respect to its execution time than the modified one; (2) the modifications proposed, however, reduce the jitter and improve the robustness considerably; (3) the slot time of the original FIP protocol has theoretical upper bound but the modified protocol has no such limitations.

We present an approach to bus access optimization and schedulability analysis for the synthesis of hard real-time distributed embedded systems. The communication model is based on a time-triggered protocol. We have developed an analysis for the communication delays proposing four different message scheduling policies over a time-triggered communication channel. Optimization strategies for the bus access scheme are developed, and the four approaches to message scheduling are compared using extensive experiments. Static non-preemptive scheduling of a set of processes on a multiprocessor architecture has been discussed in [4, 5]. Several approaches consider architectures consisting of a single programmable processor and an ASIC. Under such circumstances deriving a static schedule for the software component practically means the linearization of the dataflow graph [3]. Although different scheduling strategies have been adapted to accommodate distributed architectures, researchers have often ignored or very much simplified aspects concerning the communication infrastructure. One typical solution is to consider communication tasks as processes with a given execution time (depending on the amount of information transferred) and to schedule them as any other process [4, 20], without considering issues like communication protocol, bus arbitration, packaging of messages, and clock synchronization. Previous works related to communication synthesis, like [1, 2, 6, 10, 11], are dealing with lower level aspects of hardwaresoftware communication and are not addressing problems specific to distributed real-time embedded systems, based on particular communication protocols. Currently, more and more real-time systems are used in physically distributed environments and have to be implemented on distributed architectures in order to meet reliability, functional, and performance constraints. Thus, in order to guarantee that real-time requirements are fulfilled, schedulability analysis has 2. System Architecture 2.1 Hardware Architecture We consider architectures consisting of nodes connected by a broadcast communication channel. Every node consists of a TTP controller, a CPU, a RAM, a ROM and an I/O interface to sensors and actuators. A node can also have an ASIC in order to accelerate parts of its functionality. Communication between nodes is based on the TTP [7]. TTP was designed for distributed real-time applications that require predictability and reliability (e.g, drive-by-wire). It integrates all the services necessary for fault-tolerant real-time systems. The communication channel is a broadcast channel, so a message sent by a node is received by all the other nodes. The bus access scheme is time-division multiple-access (TDMA) (Figure 1). Each node N i can transmit only during a predetermined time interval, the so called TDMA slot S i. In such a slot, a node can send several messages packaged in a frame. A

This paper considers the use of lock-free shared objects within hard r eal-time systems. As the name suggests, lock-free shared objects are distinguished by the fact that they are not locked. As such, they do not give rise to priority inversions, a key advantage over conventional, lock-based object-sharing approaches. Despite this advantage, it is not immediately apparent that lock-free shared objects can be employed if tasks must adhere to strict timing constraints. In particular, lock-free object implementations permit concurrent operations to interfere with each other, and repeated interferences can cause a given operation to take an arbitrarily long time to complete. The main contribution of this paper is to show that such interferences can be b ounded by judicious scheduling. This work pertains to periodic, hard r eal-time tasks that share l o ck-free objects on a uniprocessor. In the rst part of the paper, scheduling conditions are derived for such tasks, for both static and dynamic priority schemes. Based on these conditions, it is formally shown that lock-free object-sharing approaches can be expected to incur much less overhead than approaches based on wait-free objects or lock-based schemes. In the last part of the paper, this conclusion is validated experimentally through work involving a realtime desktop videoconferencing system.

In this paper, we derive bounds on performance guarantees of online algorithms for real-time preemptive scheduling of jobs with deadlines on K machines when jobs are characterized in terms of their minimum stretch factor α (or, equivalently, their maximum execution rate r = 1/α). We consider two well known preemptive models that are of interest from practical applications: the hard real-time scheduling model in which a job must be completed if it was admitted for execution by the online scheduler, and the firm real-time scheduling model in which the scheduler is allowed not to complete a job even if it was admitted for execution by the online scheduler. In both models, the objective is to maximize the sum of execution times of the jobs that were executed to completion, preemption is allowed, and the online scheduler must immediately decide, whenever a job arrives, whether to admit it for execution or reject it. We measure the competitive ratio of any online algorithm as the ratio of the value of the objective function obtained by this algorithm to that of the best possible offline algorithm. We show that no online algorithm can have a competitive ratio greater than 1 − (1/α) + ε for hard real-time scheduling with K ≥ 1 machines and greater than 1 − (3/(4 α)) + ε for firm real-time scheduling on a single machine, where ε > 0 may be arbitrarily small, even if the algorithm is allowed to know the value of α in advance. On the other hand, we exhibit a simple online scheduler that achieves a competitive ratio of at least 1 − (1/α) in either of these models with K machines. The performance guarantee of our simple scheduler shows that it is in fact an optimal scheduler for hard real-time scheduling with K machines. We also describe an alternative scheduler for firm real-time scheduling on a single machine in which the competitive ratio does not go to zero as α approaches 1. Both of our schedulers do not know the value of α in advance.

Fault tolerance has become more and more important in the development of autonomous systems with the aim to help the system to recover its normal activities even when some failures happen. Yet, one of the concerns is how to analyze the reliability of a fault tolerance mechanism with regards to the collaboration of multiple agents to complete a complicated task. To do so, an approach of fault tolerance analysis with the colored time Petri net framework is proposed in this work, where a task can be represented by a tree of different concurrent and dependent subtasks to assign to agents. Different subtasks and agents are modeled by color tokens in Petri network. The time values are added to evaluate the processing performance of the whole system with respect to its ability to solve a task with fault tolerance ability. The colored time Petri nets are then tested with simulation of centralized and distributed systems. Finally the experiments are performed to show the feasibility of the proposed approach. From the basics of this study, a generalized framework in the future can be developed to address the fault tolerance analysis for a set of agents working with a sophisticated plan to achieve a common target.

Rapid Prototyping has been proposed as a means to reduce development time and costs of real-time systems. Our approach uses a heterogeneous, tightly coupled multiprocessor system based on off-the-shelf components as target architecture for an executable prototype, which is generatedfrom the specification in an automated design process. Here, too, we aim to use existing tools and languages. But interface and communication synthesis, while being the key requirement of an automated translation of a abstract specification to a distributed system, is not yet state-of-the-art. The sensitivity of the overall performance of multiprocessor systems to overhead and latency introduced by communication on the other hand calls for an efficient interprocess communication (IPC). This paper presents concept and implementation of IPC functions which, implementing the message queue semantics of the specification language SDL, links the standard components of our multiprocessor system in an efficient manner, while at the same time providing the interface synthesis needed by the automated generation of a rapid prototype. The experiences gained when implementing a non-trivial, real-world CAN controller and monitor application on our rapid prototyping environment, are described as a first proof of concept.

Rapid Prototyping has been proposed as a means to reduce development time and costs of real-time systems. Our approach uses a heterogeneous, tightly coupled multiprocessor system based on off-the-shelf components as target architecture for an executable prototype, which is generatedfrom the specification in an automated design process. Here, too, we aim to use existing tools and languages. But interface and communication synthesis, while being the key requirement of an automated translation of a abstract specification to a distributed system, is not yet state-of-the-art. The sensitivity of the overall performance of multiprocessor systems to overhead and latency introduced by communication on the other hand calls for an efficient interprocess communication (IPC). This paper presents concept and implementation of IPC functions which, implementing the message queue semantics of the specification language SDL, links the standard components of our multiprocessor system in an efficient manner, while at the same time providing the interface synthesis needed by the automated generation of a rapid prototype. The experiences gained when implementing a non-trivial, real-world CAN controller and monitor application on our rapid prototyping environment, are described as a first proof of concept.

This paper describes real-time volumetric haptic and visual algorithms developed to simulate burrhole creation for a Virtual Realitybased craniotomy surgical simulator. A modified Voxmap pointshell algorithm [4, 7] is created to simulate haptic interactions between bone cutting tools and voxel-based bone. New surface boundary detection and force feedback calculation methods help reduce "force discontinuities" of the original Voxmap point-shell algorithm. To maintain stable haptic update rates, new forces are calculated outside the haptics rendering loop. A multi-rate haptic solution [2] is used to introduce calculated forces into the haptics loop and to interpolate forces between updates. A bone erosion method is also created to simulate bone drilling capabilities of different tools. 3D texture-based volume rendering is used to display the bone and to visually remove bone material due to drilling in real-time. Volumetric shading is computed by the GPU of the video card. The algorithms described make it possible to simulate several tools typically used for a craniotomy. Realistic 3D models are also created from real surgical tools and controlled by the haptic device.

Multi-core platforms represent the answer of the industry to the increasing demand for computational capabilities. From a real-time perspective, however, the inherent sharing of resources, such as memory subsystem and I/O channels, creates inter-core timing interference among critical tasks and applications deployed on different cores. As a result, modular per-core certification cannot be performed, meaning that: (1) current industrial engineering processes cannot be reused; (2) software developed and certified for single-core chips cannot be deployed on multi-core platforms as is. In this work, we propose the Single Core Equivalence (SCE) technology: a framework of OS-level techniques designed for commercial (COTS) architectures that exports a set of equivalent single-core virtual machines from a multi-core platform. This allows per-core schedulability results to be calculated in isolation and to hold when all the cores of the system are composed together. Thus, SCE allows each core of a multi-core chip to be considered as a conventional single-core chip, ultimately enabling industries to reuse existing software, schedulability analysis methodologies and engineering processes.

ITER Plant Systems I&C will be connected to CODAC System via Plant System Host (PSH) and High Performance Networks (HPN). Some functions of CODAC require deterministic, hard real-time communication and synchronization between distributed nodes. These requirements are addressed by the CODAC High Performance Networks. The CODAC network infrastructure is being defined including space allocation for backbone cable termination as well as housing network equipments in different ITER plant buildings, cable trenches, network topology and backbone. The ITER building design is in final stage so the activities in this direction are quite well in advance. Many prototyping and market survey activities leading to technology decisions for High Performance Networks (HPN) have been launched in late 2008. These activities are evaluating different commercial off-the-shelf (COTS) technologies as well as technologies being used in existing fusion and non-fusion experiments. In this paper we provide the current status of activities which are ongoing to define CODAC network infrastructure as well as a report on technology decisions. Finally we provide a plan and roadmap to complete this task of defining CODAC networks and network infrastructure.

Many tasks in safety-critical embedded systems have hard real-time characteristics. AbsInt's worst-case execution time analyzer aiT can estimate precise and safe upper bounds for the WCETs of program tasks, thus providing the basic input for verifying the real-time behavior of embedded applications.

We propose two novel heuristic search techniques to address the problem of scheduling tasks under hard timing constraints on a single processor architecture. The underlying problem is NP-hard in the strong sense and it is a fundamental challenge in feedback-control theory and automated cybernetics. The proposed techniques are a learning-based approaches and they take much less memory space. A partial feasible schedule is maintained and extended over a repeated problem solving trials, previously assigned priorities are refined according to the gained information about the problem to lead the convergence to a complete feasible schedule if one exists. First, we present the learning in hard-real-time with single learning (LHRTS-SL) algorithm where a single learning function is utilized, then we discuss its drawback and we propose the LHRTS with double learning algorithm in which a second learning function is integrated to cope up with LHRTS-SL drawback. Experimental results show the efficiency of the proposed techniques in terms of success ratio when used to schedule randomly generated problem instances.

This essay is to point out some of the basic differences between conventional and real-time applications of AI and to provoke discussion on whether or not a new paradigm would facilitate better understanding of these differences. Some of the listed differences are illustrated by examples from references. An attempt has been made to project existing AI methods onto the deduction-induction axis so as to find an analogy with human behaviour under hard real-time constraints, e.g. reflexes. The conclusion is that the developers of real-time AI methods might benefit by using a "reflex based" paradigm. Kevwords. Reasoning under hard real-time constraints; deduction and induction based approaches; reflex baaed paradigm of reasoning

This paper presents the PRIDE research project, developed by Intecs and co-funded by the Italian Space Agency. The project aims at providing an integrated software development environment for dependable systems based on UML, which integrates design activities with selected methods for formal verification and validation (V&V) and quantitative dependability attributes assessment, supported by appropriate tools. The PRIDE environment is built as an extension of the already existing environment for the modeling of Hard Real Time systems, HRT-UML, based on the Unified Modeling Language (UML) notation. The outcome is an advanced and integrated methodological solution for the design of complex embedded real-time systems and for their evaluation and verification, according to rigorous techniques based on formal theories, such as formal verification, model based dependability evaluation and schedulability analysis.

In this report we study hard real-time systems composed of dependent strictly periodic preemptive tasks in the monoprocessor case. Although preemptive scheduling algorithms are able to successfully schedule some systems that cannot be scheduled by any non preemptive scheduling algorithm, the cost of preemption may not be negligible. Therefore, its exact cost has to be explicitly considered in the schedulability conditions in order to avoid wasting resources and provide safety in terms of guaranteeing the right behavior of the system at run-time. Because we are interested in hard real-time systems with precedence and strict periodicity constraints where it is mandatory to satisfy these constraints, we have already shown in a previous work how to tackle this problem for systems composed of harmonic tasks. Two main contributions are presented in this report. First, we generalize our previous results to the case of systems with periods that are not necessarily harmonic. Second, we provide a necessary and sufficient schedulability condition which takes into account the exact number of preemptions for a system with such constraints when no idle time is allowed.

A challenging research issue of analyzing a real-time system is to model the tasks composing the system and the resource provided to the system. In this paper, we propose a probabilistic component-based model which abstracts in the interfaces both the functional and non-functional requirements of such systems. This approach allows designers to unify in the same framework probabilistic scheduling techniques and compositional guarantees that go from soft to hard real-time. We provide sufficient schedulability tests for task systems using such framework when the scheduler is either preemptive Fixed-Priority or Earliest Deadline First.

Algorithms based on semi-partitioned scheduling have been proposed as a viable alternative between the two extreme ones based on global and partitioned scheduling. In particular, allowing migration to occur only for few tasks which cannot be assigned to any individual processor, while most tasks are assigned to specific processors, considerably reduces the runtime overhead compared to global scheduling on the one hand, and improve both the schedulability and the system utilization factor compared to partitioned scheduling on the other hand. In this paper, we address the preemptive scheduling problem of hard real-time systems composed of sporadic constrained-deadline tasks upon identical multiprocessor platforms. We propose a new algorithm and a scheduling paradigm based on the concept of semi-partitioned scheduling with restricted migrations in which jobs are not allowed to migrate, but two subsequent jobs of a task can be assigned to different processors by following a periodic strategy.

This paper is a synthesis of different works [12, 9, 8, 13]. Problems addressed in this paper consist in assigning periodic tasks to distributed processors in the context of fixed priority preemptive scheduling. A cooperative technique using an accurate management of constraint programming is presented to solve these problems. The approach breaks down a problem into two subproblems: allocation and schedulability. Allocation problem is tackled with dynamic constraint programming whereas schedulability is analyzed with classical real-time techniques. Decomposition is used as a way of learning when the allocation subproblem yields a valid solution while the schedulability analysis of the allocation does not. The rationale of this approach is to learn from the failures of the schedulability analysis to reduce the search space. Additionally, different search strategies are proposed to increase efficiency of the resolution.

In this 25th year anniversary paper for the IEEE Real Time Systems Symposium, we review the key results in real-time scheduling theory and the historical events that led to the establishment of the current realtime computing infrastructure. We conclude this paper by looking at the challenges ahead of us.

Mobile robots are physical agents that move and interact continuously while embedded in a dynamic environment. Communications can be one of the most difficult parts of building robot architecture because of the increasing complexity of sensor and actuator hardware, and the interaction between intelligent features and real-time constraints. Currently, hybrid architectures offer the most widespread solutions for controlling intelligent mobile robots. This paper deals with the communications framework necessary to design and implement these architectures. The main goal of this work 1 is to design a modular and portable architecture that allows the development of robot control systems. A multi-level and distributed architecture based on the reactive/deliberative paradigm is presented. Its main components are mobile software agents that interact through a distributed blackboard communications framework. These agents can be run on onboard processors, as well as on fixed workstations depending on their real-time restrictions. The presented control architecture has been tested in a real mobile robot and results demonstrate the effectiveness of distributing software agents to guarantee hard real-time execution.

Department of Computer Science and Engineering of Computer Science and Engineering, NIT, Rourkela for introducing the present topic and for his inspiring intellectual guidance, constructive criticism and valuable suggestion throughout the project work. Finally, I would like to thank my parents for their support and motivation to complete this project.

Department of Computer Science and Engineering of Computer Science and Engineering, NIT, Rourkela for introducing the present topic and for his inspiring intellectual guidance, constructive criticism and valuable suggestion throughout the project work. Finally, I would like to thank my parents for their support and motivation to complete this project.

This presentation was held at the 14th International Workshop on Parallel and Distributed Real-Time Systems (WPDRTS 2006), a satellite workshop of IEEE 20th International Parallel & Distributed Processing Symposium (IPDPS 2006), April 25–29, 2006. Rhodes Island, Greece. It was made by Santiago Urueña Pascual, PhD Student working at the real-time research group (Sistemas de Tiempo Real y Arquitectura de Servicios Telemáticos, STRAST) of the UPM, Spain (Spanish: Universidad Politécnica de Madrid, Technical University of Madrid). Our research group is mainly working on hard real-time and embedded systems, especially critical ones. This was a 20 min. presentation, held at 15:30h, at the general session called “Real-Time Communication II”, session chaired by Giuseppe Lipari.

Functional size measurement has been widely used as the effort prediction method for software project over the past decades. Despite the success in predicting the cost, time requirement, and staff resources utilizing the amount of functionality delivered by a system, the method still needs to be improved further especially in dealing with mobile application characteristics. In the domain of mobile game application, the functional features can be challenging to identify wholly due to various application platforms, diversity of game genre, and complex game scenario. This paper presents a literature review concerning the functional requirements of the mobile game. The review includes the process of defining the research question, search strategy, and selection of study. Fifty-three articles were found in the academic libraries, and only 30 relevant studies were selected for the review. This literature review aims to provide researchers and practitioners in software measurement and gami...

This paper addresses a control allocation method in order to compensate for the effect of thrusters' dead-zones, on the actuation system of an underwater vehicle. This solution concurrently considers dead-zone effect and actuation limitation, in order to increase system reactivity. Moreover the impact on energy consumption is also considered. Experimental results are given to demonstrate the effectiveness and correctness of the proposed method.

Fault tolerance has become more and more important in the development of autonomous systems with the aim to help the system to recover its normal activities even when some failures happen. Yet, one of the concerns is how to analyze the reliability of a fault tolerance mechanism with regards to the collaboration of multiple agents to complete a complicated task. To do so, an approach of fault tolerance analysis with the colored time Petri net framework is proposed in this work, where a task can be represented by a tree of different concurrent and dependent subtasks to assign to agents. Different subtasks and agents are modeled by color tokens in Petri network. The time values are added to evaluate the processing performance of the whole system with respect to its ability to solve a task with fault tolerance ability. The colored time Petri nets are then tested with simulation of centralized and distributed systems. Finally the experiments are performed to show the feasibility of the proposed approach. From the basics of this study, a generalized framework in the future can be developed to address the fault tolerance analysis for a set of agents working with a sophisticated plan to achieve a common target.

This paper aims at providing a multi-objective real-time scheduling algorithm suitable for scheduling of real-time tasks in multiprocessor system with multi-objective criteria. In this proposed Mo-QIGA, scheduling of multi-objective realtime tasks have been targeted for minimizing completion time and total tardiness of each real-time task simultaneously. The exploration of quantum computation in the suggested Mo-QIGA mimics the principles and basic concepts of quantum mechanics. Variable length chromosomes are used in Mo-QIGA and in order to exhibit full Hilbert hyperspace, qubits representation is preferred. In addition, Quantum rotation gate is employed to update the schedules and it obviates classical genetic operators. In order to obtain Pareto-optimal solutions, a random key distribution has been adopted to convert the qubits particles to valid schedule solutions. Moreover, permutation based trimming technique has been introduced for population diversification which leads to good quality schedules. The experiments have been carried out using number of processors varying with real-time tasks priority and processing time. It has been found that the suggested multi-objective quantum inspired genetic algorithm outperforms its classical counterpart in terms of scheduling accuracy and time in multi-objective sense.

With the end of Moore's law and the breakdown of Dennard scaling, multicore processors are the standard way to continue improving performance while reducing Size, Weight and Power (SWaP). However, this performance is typically achieved at the cost of repeatability and predictability. Precision-timed (PRET) architectures have been shown to deliver high performance without sacrificing predictability. In this paper, we introduce InterPRET: an architecture consisting of FlexPRET cores interconnected via the S4NOC network-on-chip. Both the processor cores and the network-onchip are time-predictable, yielding an end-to-end time-predictable architecture suitable for real-time systems. CCS CONCEPTS • Computer systems organization → Multicore architectures; Real-time system architecture.

Several years before the popularization of the Internet, Mark Weiser proposed the concept of ubiquitous computing with the purpose of enhancing the use of computers by making many computers available throughout the physical environment, but making them effectively invisible to the user. Nowadays, such idea affects all areas of computing science, including both hardware and software. In this paper, a formal model for ubiquitous systems based on Petri nets is introduced and motivated with examples and applications. This simple model allows the definition of two-level ubiquitous systems, composed of a collection of processor nets providing services, and a collection of process nets requesting those services. The modeled systems abstract from middleware details, such as service discovery protocols, and security infrastructures, such as PKI's or trust policies, but not from mobility or component compatibility.