Fast and long retention-time nano-crystal memory

Journal of Applied Physics, 2003

We demonstrate a nonvolatile electrically erasable programmable read-only memory device using gold nanoparticles as charge storage elements deposited at room temperature by chemical processing. The nanoparticles are deposited over a thermal silicon dioxide layer that insulates them from the device silicon channel. An organic insulator deposited by the Langmuir-Blodget technique at room temperature separates the aluminum gate electrode from the nanoparticles. The device exhibits significant threshold voltage shifts after application of low-voltage pulses (рϮ6 V) to the gate and has nonvolatile retention time characteristics.

Journal of Applied Physics, 2013

Journal of Applied Physics, 2004

In silicon nanocrystal based metal-oxide-semiconductor memory structures, tuning of the electron tunneling distance between the Si substrate and Si nanocrystals located in the gate oxide is a crucial requirement for the pinpointing of optimal device architectures. In this work it is demonstrated that this tuning of the ''injection distance'' can be achieved by varying the Si ϩ ion energy or the oxide thickness during the fabrication of Si nanocrystals by ultralow-energy silicon implantation. Using an accurate cross-section transmission electron microscopy ͑XTEM͒ method, it is demonstrated that two-dimensional arrays of Si nanocrystals cannot be positioned closer than 5 nm to the channel by increasing the implantation energy. It is shown that injection distances down to much smaller values ͑2 nm͒ can be achieved only by decreasing the nominal thickness of the gate oxide. Depth profiles of excess silicon measured by time-of-flight secondary ion mass spectroscopy and Si nanocrystal locations determined by XTEM are compared with Monte-Carlo simulations of the implanted Si profiles taking into account dynamic target changes due to ion implantation, ion erosion, and ion beam mixing. This combination of experimental and theoretical studies gives a safe explanation regarding the unique technological route of obtaining Si nanocrystals at distances smaller than 5 nm from the channel: the formation of nanocrystals requires that the interface mixing due to collisional damage does not overlap with the range profile to the extent that there is no more a local maximum of Si excess buried in the SiO 2 layer.

Applied Physics Letters, 2003

Metal-insulator-semiconductor structures with a layer of silicon nanocrystals embedded within the SiO 2 layer at a tunneling distance from a p-type silicon substrate and fabricated using chemical vapor deposition, oxidation, and annealing, exhibited charge trapping, determined from the capacitance-voltage (C -V) characteristics, which abruptly increased at fields above 2.5 MV/cm. Electrons or holes are trapped when biasing the structure into inversion or accumulation, respectively, and retention of trapped charge is demonstrated. The I -V characteristics exhibit an N-shaped form, indicating screening effects due to charging; an initial current spike, attributed to transient charging of nanocrystals, occurs at the same voltage causing abrupt C -V shift increase, with Fowler-Nordheim current rising at higher voltages. These structures are promising for memory device applications.

physica status solidi (a), 2013

In this paper, we review the fabrication and the electrical characteristics of metal-insulator-semiconductor (MIS) devices with semiconductor quantum dots (QD) embedded into the gate dielectric. Our results originate from experiments performed the last decade and cover Si QDs realized by low-energy ion-beam synthesis (IBS) as well as GaN QDs formed by molecular beam deposition (MBD). Besides the basic capacitance-to-voltage (C-V) and current-to-voltage (I-V) characterization, the memory properties of the fabricated MIS devices were investigated in terms of memory window under pulse operation and charge retention. The optimization of Si-QD memory cells is reviewed and a methodology for both the extraction of various device parameters and the identification of mechanisms governing the charge loss process are presented. GaN QDs, which exhibit negative conduction band-offset with respect to the Si conduction band, offer an interesting alternative to Si QDs as discussed herein based on our investigations of GaN-QD capacitors fabricated by a complementary-metal-oxide-semiconductor (CMOS) compatible process.

MRS Proceedings, 2004

... co-implanted atoms (eg fluorine atoms) on the structural evolution of Si-implanted oxides ... IDS-VG characteristics and ∆Vth as a function of the programming pulse (PP) voltage for ... windows, strongly depend on the source-drain current (IDS) used for threshold voltage extraction. ...

Applied Physics Letters, 2002

We investigated the dependence of implantation dose on the charge storage characteristics of large-area n-channel metal-oxide-semiconductor field-effect transistors with 1-keV Si ϩ -implanted gate oxides. Gate bias and time-dependent source-drain current measurements are reported. Devices implanted with 1ϫ10 16 cm Ϫ2 Si dose exhibit a continuous ͑trap-like͒ charge storage process under both static and dynamic conditions. In contrast, for 2ϫ10 16 cm Ϫ2 implanted devices, electrons are stored in Si nanocrystals in discrete units at low gate voltages, as revealed by a periodic staircase plateau of the source-drain current with a low gate voltage sweep rate, and the step-like decrease of the time-dependent monitoring of the channel current. These observations of room-temperature single-electron storage effects support the pursuit of large-area devices operating on the basis of Coulomb blockade phenomena.

Journal of Applied Physics, 2004

We report Raman spectra of a single layer of silicon nanoparticles, spatially ordered in SiO 2 at a tunneling distance from a silicon substrate. This is achieved by exploiting effects which enhance the nanocrystal signal, while suppressing the substrate one. The method is applied to investigate the structure of ion-implantation-produced Si nanoparticles annealed under different conditions. The results, which are in good agreement with transmission electron microscopy data, are used to explain photoluminescence measurements.

Journal of Applied Physics, 2013

Ultrathin InP passivated GaAs non-volatile memory devices were fabricated with chemically synthesized 5 nm ZnO quantum dots embedded into ZrO 2 high-k oxide matrix deposited through metal organic chemical vapor deposition. In these memory devices, the memory window was found to be 6.10 V and the obtained charge loss was only 15.20% after 10 5 s. The superior retention characteristics and a wide memory window are achieved due to presence of ZnO quantum dots between tunneling and control oxide layers. Room temperature Coulomb blockade effect was found in these devices and it was ascertained to be the main reason for low leakage. Electronic band diagram with program and erase operations were described on the basis of electrical characterizations. V C 2013 AIP Publishing LLC. [http://dx.

Journal of Nanoparticle Research, 2011

We have grown Ge nanocrystals (NCs) (4.0-9.0 nm in diameter) embedded in high-k HfO 2 matrix for applications in floating gate memory devices. X-ray photoelectron spectroscopy has been used to probe the local chemical bonding of Ge NCs. The analysis of Ge-Ge phonon vibration using Raman spectroscopy has shown the formation of compressively stressed Ge NCs in HfO 2 matrix. Frequency dependent electrical properties of HfO 2 /Ge-NCs in HfO 2 /HfO 2 sandwich structures have been studied. An anticlockwise hysteresis in the capacitance-voltage characteristics suggests electron injection and trapping in embedded Ge NCs. The role of interface states and deep traps in the devices has been thoroughly examined and has been shown to be negligible on the overall device performance.

Journal of Applied Physics, 2007

Arrays of Ru nanocrystals 1-4 nm in diameter are deposited via a hybrid chemical vapor deposition/atomic layer deposition reaction. The nanocrystal density is found to depend sensitively on the nucleating surface. A maximum density of ͑7-8͒ ϫ 10 12 cm −2 is achieved on Al 2 O 3. Incorporation of these nanocrystals in floating-gate memory cells results in C-V curves that exhibit large, counterclockwise hysteresis. Leakage current analysis reveals Coulomb blockade phenomena, Frenkel-Poole emission, and space-charge-limited conduction. This analysis allows for the determination of nanocrystal size and connectivity. Charge storage converges to approximately 50% of the maximum value after two days. The corresponding loss mechanisms are discussed.

Applied Physics Letters

Journal of Applied Physics, 2004

The effect of oxidation on charge transport and retention within a sheet of silicon ͑Si͒ nanocrystals was investigated with an electrostatic force microscope. Single layers of nanocrystals with smooth and abrupt Si/SiO 2 interfaces were prepared by thermal crystallization of thin amorphous Si layers, followed by an oxidation treatment for isolating the nanocrystals. Controlled amounts of charge were injected into the nanocrystals and their in-plane diffusion was monitored in real time. Rapid transport of the injected charge occurred for the nonoxidized nanocrystals. Oxidation of the nanocrystal layer resulted in suppression of lateral transport. The nanocrystals oxidized for 30 min retained the injected charge in a well-defined, localized region with retention times of the order of several days. These long-term charge retention characteristics indicate that nanocrystals prepared by this process could be attractive candidates for nonvolatile memory applications.

Journal of Materials Science, 2008

In this study, Si-nanoparticle(NP)/Si-nanowire-(NW)-based field-effect transistors (FETs) with a top-gate geometry were fabricated and characterized. In these FETs, Si NPs were embedded as localized trap sites in Al 2 O 3 topgate layers coated on Si NW channels. Drain current versus drain voltage (I DS-V DS) and drain current versus gate voltage (I DS-V GS) were measured for the Si NP/Si NW-based FETs to investigate their electrical and memory characteristics. The Si NW channels were depleted at V GS = 9 V, indicating that the devices functioned as p-type depletionmode FETs. The top-gate Si NW-based FETs decorated with Si NPs show counterclockwise hysteresis loops in the I DS-V GS curves, revealing their significant charge storage effect.

physica status solidi (a), 2015

A memory structure containing ultra-small 2-nm lasersynthesized silicon nanoparticles is demonstrated. The Sinanoparticles are embedded between an atomic layer deposited high-k dielectric Al 2 O 3 layer and a sputtered SiO 2 layer. A memory effect due to charging of the Si nanoparticles is observed using high frequency C-V measurements. The shift of the threshold voltage obtained from the hysteresis measurements is around 3.3 V at 10/À10 V gate voltage sweeping. The analysis of the energy band diagram of the memory structure and the negative shift of the programmed C-V curve indicate that holes are tunneling from p-type Si via Fowler-Nordheim tunneling and are being trapped in the Si nanoparticles. In addition, the structures show good endurance characteristic (>10 5 program/erase cycles) and long retention time (>10 years), which make them promising for applications in non-volatile memory devices.

Applied Physics Letters, 2008

A nonvolatile memory is demonstrated using a solution-processed sol-gel ZnO thin-film transistor ͑TFT͒ in which Ag nanoparticles are embedded as charge storage nodes at the insulator-ZnO interface. Its TFT transfer characteristics exhibit a large clockwise hysteresis that is proportional to the gate bias sweep range. Measurement of the threshold voltage shift versus the pulse width of gate bias reveals that the device can be programed or erased at a time scale of as short as 10 −4 s. Retention of the initial memory window is measured to be 27% after 10 5 s and projected to last until 10 7 s.

Applied Physics Letters, 2007

An oxygen-incorporated Mo silicide layer was explored to form the Mo nanocrystals after rapid thermal annealing. Transmission electron microscopy showed the nanocrystals embedded in SiO x . Charge-storage characteristics of Mo nanocrystals influenced by Mo oxide and its surrounding oxide were investigated through X-ray photoelectron spectroscopy and electrical measurement. X-ray photoelectron spectral analyses revealed a redox reaction in the oxygen-incorporated Mo silicide layer after rapid thermal annealing at a critical temperature. The memory window and retention were improved because of the reduction of Mo oxide. Furthermore, the double-layer nanocrystal structure was fabricated through the annealed stacked oxygen incorporated Mo silicide layer. A larger memory window and long retention were found for the double-layer nanocrystal structure. We used an energy band diagram to explain the difference in retention characteristics between single-and double-layer structures.

Semiconductor Science and Technology, 2009

In this work, gate stacks in metal nanocrystal (NC) memories, as promising next generation storage devices and their systems, are extensively investigated. A comparative analysis and characterization of the program/erase (P/E) speed, retention and the process margin of cobalt NC memories including high-k and bandgap engineering technologies are performed by using the technology computer-aided design (TCAD) simulation. It is shown that NC memory with high-k dielectric (HfO 2) has better performance in P/E speed and retention when the diameter of NC is below 5 nm. When the diameter is beyond 5 nm, on the other hand, the bandgap-engineered bottom oxide gate structure shows improved performance in P/E speed and retention. From the process margin perspective, as the permittivity of the dielectric gets larger, the limits of the diameter and the density of NCs allow the degree of freedom to become larger.

Journal of Nanomaterials, 2013

Charge storage nonvolatile memory (NVM) is one of the main driving forces in the evolution of IT handheld devices. Technology scaling of charge storage NVM has always been the strategy to achieve higher density NVM with lower cost per bit in order to meet the persistent consumer demand for larger storage space. However, conventional technology scaling of charge storage NVM has run into many critical reliability challenges related to fundamental device characteristics. Therefore, further technology scaling has to be supplemented with novel approaches in order to surmount these reliability issues to achieve desired reliability performance. This paper is focused on reviewing critical research findings on major reliability challenges and technical solutions to mitigate technology scaling challenges of charge storage NVM. Most of these technical solutions are still in research phase while a few of them are more mature and ready for production phase. Three of the mature technical solutions will be reviewed in detail, that is, tunnel oxide top/bottom nitridation, nanocrystal, and phase change memory (PCM). Key advantages and reported reliability challenges of these approaches are thoroughly reviewed in this paper. This paper will serve as a good reference to understand the future trend of innovative technical solutions to overcome the reliability challenges of charge storage NVM due to technology scaling.

MRS Proceedings, 2004

ABSTRACTExperimental characterization of nanocrystal formation in gate trenches were performed, which includes the analyses of number fluctuation, the size distribution, and the correlation of the size and number density in gate patterns with various feature sizes from 50nm to 150nm. The gate regions with 51nm oxide wall are defined by e-beam lithography and reactive ion etching (RIE). By using direct-deposit self-assembly (i.e., evaporation and post-annealing), Au, Ag, and Pt nanocrystals are formed on the gate tunneling oxide. From the statistical evaluation by scanning electron microscopy (SEM) observation, the number fluctuation of nanocrystals in a gate trench could be always controlled under 12%, while it follows the Poisson distribution in the unconstrained self-assembly. This is mainly due to the confinement effect by the trench sidewalls, corners, and edges. The current study demonstrated that the direct-deposit self-assembly process could be successfully adapted beyond 90n...

Journal of Physics D: Applied Physics, 2013

Nanocrystals (NCs), representing a zero-dimensional system, are an ideal platform for exploring quantum phenomena on the nanoscale, and are expected to play a major role in future electronic and photonic devices. Here we review recent progress in the growth, characterization and utilization of some group-IV semiconductors (Si and Ge), metal and high-k NCs for silicon planar technology compatible light-emitting and floating gate memory devices. We first introduce the size-dependent electrical and optical properties of Si and Ge NCs. We outline some of the schemes to achieve light emission from indirect band gap Si and Ge NCs embedded in different high band gap oxide matrices. In particular, special emphasis is given on the review of the advances in Ge NCs because of some of their intriguing electronic and optical properties. We then describe the use of semiconductor and metal NCs as floating gates for non-volatile memory devices to achieve high data retention and faster program/erase speeds. The exploitation of high-k oxides with tunable and variable injection barriers for improved charge storage devices is discussed. Finally, the integration of single and multilayer metallic NCs and multilayer high-k oxides as floating gates is explored by the fabrication and testing of memory transistors.

Journal of Applied Physics, 2007

A layer of Ge nanocrystals ͑nc-Ge͒ distributed in the gate oxide near the gate of a metal-oxide-semiconductor structure is synthesized with low-energy Ge ion implantation followed by thermal annealing at 800°C. The behaviors of charge trapping and charge retention in the nc-Ge have been studied. For a positive charging voltage, only electron trapping occurs, and the trapped electrons show a long retention time. However, for a negative charging voltage, both the hole trapping and electron trapping occur simultaneously, and the hole trapping is dominant if the magnitude of the charging voltage is small or the charging time is short. Due to the relatively easier loss of the trapped holes, the net charge trapping in the nc-Ge exhibits a continuous shift toward a more negative value with the waiting time.

JOM, 2004

Silicon Nanoelectronics Overview Films consisting of nanometer-scale silicon crystals with narrow size distribution can be fabricated using a variety of techniques and are of technological interest for nonvolatile semiconductor memory applications. One fabrication technique based on the crystallization of thin amorphous silicon fi lms also shows potential for large-scale production of single isolated nanocrystals for future single-electron transistor and memory applications. A review of the most promising nanocrystalline silicon fabrication techniques and a discussion of current research in the area of crystallized thin-fi lm amorphous silicon are presented in this article.

Nanoscale Research Letters, 2015

In this work, we demonstrate a non-volatile metal-oxide semiconductor (MOS) memory with Quattro-layer graphene nanoplatelets as charge storage layer with asymmetric Al 2 O 3 /HfO 2 tunnel oxide and we compare it to the same memory structure with 2.85-nm Si nanoparticles charge trapping layer. The results show that graphene nanoplatelets with Al 2 O 3 /HfO 2 tunnel oxide allow for larger memory windows at the same operating voltages, enhanced retention, and endurance characteristics. The measurements are further confirmed by plotting the energy band diagram of the structures, calculating the quantum tunneling probabilities, and analyzing the charge transport mechanism. Also, the required program time of the memory with ultra-thin asymmetric Al 2 O 3 /HfO 2 tunnel oxide with graphene nanoplatelets storage layer is calculated under Fowler-Nordheim tunneling regime and found to be 4.1 ns making it the fastest fully programmed MOS memory due to the observed pure electrons storage in the graphene nanoplatelets. With Si nanoparticles, however, the program time is larger due to the mixed charge storage. The results confirm that band-engineering of both tunnel oxide and charge trapping layer is required to enhance the current non-volatile memory characteristics.

MRS Proceedings, 2003

A method to liberate germanium (Ge) nanocrystals from silicon dioxide (SiO 2 ) thin films by hydrofluoric acid (HF) vapor etching is presented. Multi-energy implantation of mass separated Ge ions into 500-nm-thick wet oxide layers on silicon (Si) substrates followed by thermal annealing produces nanocrystals that are 2 to 8 nm in diameter. Raman spectra exhibit the expected asymmetric line shapes due to the phonon confinement effect, but with a higher peak frequency than predicted. To free the nanocrystals, samples are etched in HF vapor to selectively remove the SiO 2 matrix and expose the nanocrystal surfaces. Raman spectra of etched samples display peak frequencies consistent with relief of compressive stress. The liberated nanocrystals show long-term stability under ambient atmospheric conditions. Ge nanocrystals can be removed from etched surfaces using an ultrasonic methanol cleaning procedure. The nanocrystal-containing solution is applied to a TEM grid and the solvent is evaporated. Subsequently obtained electron diffraction patterns confirm that the nanocrystals survive this transfer step. Thus, liberated Ge nanocrystals are expected to be accessible for a wide range of manipulation processes and direct characterization techniques.