Non‐volatile memory devices based on Ge nanocrystals

Communications - Scientific letters of the University of Zilina

Nanoscale Research Letters, 2011

Ge nanocrystals (Ge-NCs) embedded in SiN dielectrics with HfO 2 /SiO 2 stack tunnel dielectrics were synthesized by utilizing low-energy (≤5 keV) ion implantation method followed by conventional thermal annealing at 800°C, the key variable being Ge + ion implantation energy. Two different energies (3 and 5 keV) have been chosen for the evolution of Ge-NCs, which have been found to possess significant changes in structural and chemical properties of the Ge + -implanted dielectric films, and well reflected in the charge storage properties of the Al/SiN/Ge-NC + SiN/HfO 2 /SiO 2 /Si metal-insulator-semiconductor (MIS) memory structures. No Ge-NC was detected with a lower implantation energy of 3 keV at a dose of 1.5 × 10 16 cm -2 , whereas a well-defined 2D-array of nearly spherical and well-separated Ge-NCs within the SiN matrix was observed for the higher-energy-implanted (5 keV) sample for the same implanted dose. The MIS memory structures implanted with 5 keV exhibits better charge storage and retention characteristics compared to the low-energy-implanted sample, indicating that the charge storage is predominantly in Ge-NCs in the memory capacitor. A significant memory window of 3.95 V has been observed under the low operating voltage of ± 6 V with good retention properties, indicating the feasibility of these stack structures for low operating voltage, non-volatile memory devices.

IEEE Transactions On Nanotechnology, 2006

MRS Proceedings, 2003

In this work, we present an extensive study of the oxidation process of Si/Ge nanocrystals (nc-Ge)/Si samples using SIMS (Second Ion Mass Spectroscopy), Transmission Electron Micrscopy (TEM), Atomic Force Microscopy (AFM) and electrical characterization of Metal/Oxide/Semiconductor capacitors (MOS). Various samples with different oxidation times have been studied and it is demonstrated that Silicon dry oxidation kinetics is not influenced by the presence of Ge. As shown by SIMS measurements, a pure SiO2 layer is formed on the top of the structure, while the Ge atoms are intermixed with the silicon substrate. The TEM and AFM analysis show that the nc-Ge height is drastically reduced during the oxidation process. The fabrication of MOS capacitors on the structures allowed to study electron and hole trapping in the Ge dots. From our analysis we have shown that the Ge nanostructures which covered by SiO2 are not isolated from the Si substrate.

International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217)

In this work, we propose a novel technique of fabricating germanium nanocrystal quasi-nonvolatile memory device. The device consists of a MOSFET with Ge charge-traps embedded within the gate dielectric. This trap-formation method provides for precise control of the thicknesses of the oxide layers which sandwich the charge-traps, via thermal oxidation. Memory devices with write/erase speed/voltage and retention time superior to previously reported nanocrystal memory devices were demonstrated.

Microelectronics Journal, 2003

The characteristics of p-channel Ge/Si hetero-nanocrystal based MOSFET memory have been investigated numerically considering mainly hole-tunneling process. Owing to the advantages of a compound potential well and a higher band offset at the valence band compared with the p-channel Si nanocrystal based MOSFET memory and n-channel Ge/Si hetero-nanocrystal based MOSFET memory, the present structure shows that the holes have a longer retention time. Moreover, this kind of device keeps on having high-speed writing/erasing in the direct-tunneling ultrathin oxide regime. It would be expected to solve the contradictory problem between high-speed programming and long retention, therefore, the performance would be substantially improved. q

ECS Transactions, 2015

2007

This thesis explores the commercialization of germanium-based nanocrystal memories. Demand for smaller and faster electronics and embedded systems supports the development of high-density, low-power non-volatile electronic memory devices. Flash memory cells designed for ten years of data retention require the use of a thick tunneling oxide. This compromises writing and reading speed as well as endurance. A smaller device size can be achieved and speed and can be improved by decreasing the oxide thickness. However, significant charge leakage will occur if the oxide is too thin, which will reduce the data retention time dramatically. This imposes a limit to the amount by which the oxide thickness can be decreased in conventional devices. Research has shown that by incorporating nanocrystals in the tunnel oxide, charge traps are created which reduce charge leakage and improve endurance through charge-storage redundancy. By replacing the conventional floating gate memory with one using Si or Ge nanocrystals, the nonvolatile memory exhibits high programming speed with low programming voltage and superior retention time, and yet is compatible with conventional silicon technology. This thesis provides an analysis of competing technologies, an intellectual property analysis, costs modeling as well as ways to improve nanocrystal memories in order to compete with other forms of emerging technologies to replace conventional Flash memories.

Journal of Non-Crystalline Solids, 2008

Nanocomposite SiO 2 (Si) films containing Si nanocrystals (NCs) in a SiO 2 dielectric matrix obtained through (i) plasma enhanced chemical vapor deposition (PE CVD) or (ii) pulse laser deposition (PLD) have been investigated as a medium for charge storage. The C-V method was used to characterize charging effects in the MIS structure (capacitor) with a nanocomposite SiO 2 (Si) film as an insulator. The obtained results indicate (i) the capture of small negative charge at the positive gate voltage in the nanocomposite SiO 2 (Si) film, (ii) significant capture of positive charge at the negative gate voltage, and that (iii) the difference between the positive and negative charge captured in both cases cannot be explained by dropping a part of the positive gate voltage in the semiconductor's depletion region. A model of charge transport and capture in nanocrystals of nanocomposite SiO 2 (Si) film is proposed to explain the experimental results.

MRS Proceedings, 2004

ABSTRACTA method of forming a sheet of Ge nanocrystals in a SiO2 layer based on molecular beam epitaxy (MBE) and rapid thermal processing (RTP) is presented. The method takes advantage of the very high precision by which a very thin Ge layer can be deposited by MBE. With proper choice of process parameters the nanocrystal size can be varied between ∼3 and ∼8 nm and the area-density between ∼1×1011 and ∼1×1012 dots/cm2. The tunneling oxide thickness is determined by the thickness of a thermally grown SiO2 layer, and is typically 4 nm. C-V measurements of MOS capacitors reveal hole and electron injection from the substrate into the nanocrystals. Memory windows of about 0.2 and 0.5 V for gate-voltage sweeps of 3 and 6 V, respectively, are achieved.