C-based Interactive RTL Design Methodology

This article gives a design overview of the new hardware synthesis tool ConPro used for development of applicationspecific digital logic systems providing a high-level approach with imperative programming features filling the gap between hardware and software level. It is an experimental platform for studying different hybrid scheduling strategies, too. The ConPro development tool and programming language guides the user from an algorithmic programmer software view to RTL hardware architecture. Concurrency is explicitly modelled with communicating processes and interprocess communication primitives known from traditional and well-known parallel software development using leight weight processes (threads), like semaphores or mutexes. The process modell provides only a single control path resulting in strict sequential instruction scheduling. Concurrency inside processes is limited to the data path. Beneath explicitly modelled concurrency, automatic exploitation of inherent concurrency is provided by the synthesis compiler using a multi-pass hybrid scheduler.

2005

Nowadays, Architecture Description Languages (ADLs) are getting popular to speed up the development of complex SoC design, by performing the design space exploration in a higher level of abstraction. This increase in the abstraction level traditionally comes at the cost of low performance of the final Application Specific Instructionset Processor (ASIP) implementation, which is generated automatically from the ADL. There is a pressing need of novel optimization techniques for high level synthesis from ADLs, to compensate for this loss of performance. Two important aspects of these optimizations are the efficient usage of available structural information in the high level architecture descriptions and prudent pruning of overhead, introduced by mapping from ADL to Register Transfer Level (RTL). In this paper, we present two high level optimization techniques, path sharing and decision minimization. These optimization techniques are shown to be of lower complexity, by at least two orders, compared to similar optimization during gate-level synthesis. The optimizations are tested for a RISC architecture, a VLIW architecture and two industrial embedded processors, Motorola M68HC11 and Infineon ICORE. The results indicate a significant improvement in overall performance.

Proc. 9th VLSI Design …, 2005

Today's VLSI technology allows us to construct large, complex systems with million transistors on a single chip. Most of the existing high level synthesis systems give more priority to optimization of area, power, resource and time steps compared to interconnection cost, whereas the later becomes predominant with the technology scaling and increase in complexity. Further, field programmable gate arrays (FPGA) are now becoming attractive platform for prototyping. Programmable devices tend to have limited wiring resources between the data path elements. This work is concerned with the development of a CAD tool for HLS named, "Structured Architecture Synthesis Tool (SAST)", which incorporates structured architecture generation with special emphasis on optimization of interconnect area. The too takes a behavioral description written in 3-address form and generates synthesizable RTL codes with scripts for compliance with standard design tools like Synopsys, Magma etc.

2011

The complexity of the contemporary digital circuits and systems, determines the need for higher specification abstraction and automatic circuit synthesis techniques to be adopted. A prototype high level synthesis framework is presented here, that automatically generates synthesizable RTL code from unaltered, high level programs. The framework is developed using compiler-generator and logic programming (thus formal) techniques, and it utilizes a patented intermediate compilation format to retain the algorithmic semantics of the source programs and allow for compiler transformations. The synthesis framework is evaluated via statistics from a number of real-life applications. The performance optimization of the compiled applications, including an MPEG engine, underlines the quality of the prototype design framework.

Proceedings of the 34th Design Automation Conference, 1997

In recent years, logic emulation has been widely used as a key design veri cation methodology in many complex CPU, telecom, and multimedia design projects. When using logic emulation for design veri cation, designers often need t o p erform engineering changes as a r esult of design debugging of a design speci cation modi cation. One of the essential issues to engineering changes is the turnaround time. Ideally, after designers modify their designs, they resume their debugging and veri cation tasks immediately. However, converting a design from its Register-Transfer-Level RTL description to a target emulator is a time-consuming procedure which may take hours. Such long engineeringchange turnaround times are unacceptable by the designers. In this paper, we present a real-time RTL engineering-change method supporting on-line debugging for logic-emulation applications. We propose a novel design method which is able to link design data generated at di erent design stages in a uni ed way. Using this method, the users can immediately locate the portion of the circuit design a ected by the design modi cation from its RTL speci cation. This feature p r ovides users with a fast time-to-debug environment by signi cantly improving the e ciency of the engineering-change process. We have developed a p r ototype system Quick ECO supporting interactive on-line RTL engineering changes. Experimental results on a number of industrial designs are reported to demonstrate the e ectiveness of the proposed method.

12th IEEE International Conference and Workshops on the Engineering of Computer-Based Systems (ECBS'05), 2005

The functional validation of a state-of-the-art reconfigurable computing system design is usually a laborious, ad hoc and open-ended task. It can be accomplished through two basic approaches: simulation and formal verification. In validation using a formal verification approach, it attempts to establish that the Register Transfer Level (RTL) design synthesized from the algorithmic behavioral specification is mathematically correct. Therefore, finding the verification methods to provide accurate and fast validation easily would be very useful. In this paper, we develop a semantics based on a Partial Order Based Model (POM) for RTL and, through this semantics, propose a formal verification method to prove the correctness of the RTL synthesis result. This method can be used to achieve the following. On one hand, it can accurately verify an RTL description with respect to a behavioral specification of the system; on the other hand, it can decide whether two processes, which are supposed to implement the same function, have the same interactive behaviors so that one can be replaced by the other.

[1992] Proceedings 29th ACM/IEEE Design Automation Conference

In this paper, we describe an approach to data-path synthesis from a partitioned behavioral-level description into a multiple-chip pipelined RTL design. The problem is divided into interchip connection determination and scheduling. A heuristic search technique is described for interchip connection determination. Synthesis results are presented.

Proceedings of the 1989 26th ACM/IEEE conference on Design automation conference - DAC '89

Synthesis of digital systems, involves a number of tasks ranging from scheduling to generating interconnections.

The ConPro programming language, an new enhanced imperative programming language is mapped to Register-Transfer-Logic using a higher-level-synthesis approach performed by the synthesis tool ConPro. In contrast to other approaches using modified existing software languages likeC, this language is designed from scratch providing a consistent model for both hardware design and software programming. The programming model and the language provide parallelism on control path level using a multi-process model with communicating sequential processes (CSP), and on data path level using bounded program blocks. Each process is mapped to a Finite-State-Machine and is executed concurrently. Additionally, program blocks can be parameterized and can control the synthesis process (scheduling and allocation). Synthesis is based on a noniterative, multi-level and constraint selective rule-set based approach, rather than on a traditional constrained iterative scheduling and allocation approach. Required interprocess communication is provided by a set of primitives, entirely mapped to hardware, already established in concurrent softwareprogramming (multi-threading), implemented with an abstract data type object model and method-based access. It is demonstrated that this synthesis approach is efficient and stable enough to create complex circuits reaching themillion gates boundary.

Proceedings of the 31st annual conference on Design automation conference - DAC '94, 1994

We address the problem of long cycle time associated with the basic method of optimizing VLSI circuits. We are developing a system which makes it possible to carry out arbitrary changes to Register Transfer Level (RTL) source description of the circuit after a gatelevel implementation has been synthesized. The system incrementally updates the gate-level implementation. For typical changes this updation produces comparable results but requires only a small fraction of the time for a complete resynthesis. The system makes use of two object representations. We describe these representations, the maintenance of consistency between them and the incremental synthesis and reoptimization process. Status of the ongoing research on this system is presented. 1 A pre-optimized block is treated by the system as a black