ACM Transactions on Design Automation of Electronic Systems
To meet application-specific performance demands, recent embedded platforms often involve the use... more To meet application-specific performance demands, recent embedded platforms often involve the use of intricate micro-architectural designs and very small feature sizes leading to complex chips with multi-million gates. Such ultra-high gate densities often make these chips susceptible to inappropriate surges in core temperatures. Temperature surges above a specific threshold may throttle processor performance, enhance cooling costs, and reduce processor life expectancy. This work proposes a generic temperature management strategy that can be easily employed to adapt existing state-of-the-art task graph schedulers so that schedules generated by them never violate stipulated thermal bounds. The overall temperature-aware task graph scheduling problem has first been formally modeled as a constraint optimization formulation whose solution is shown to be prohibitively expensive in terms of computational overheads. Based on insights obtained through the formal model, a new fast and efficien...
Application of behavioural transformations for obtaining optimal performance, energy and/or area ... more Application of behavioural transformations for obtaining optimal performance, energy and/or area on a given platform during embedded system design is now a common practice. Verifying correctness of these transformations is an important step in ensuring dependability of embedded systems. This thesis addresses verification methodologies, primarily by way of equivalence checking, for six behavioural transformations that are applied during embedded system design. The transformations considered cover code motion, generation of register transfer level (RTL) design after carrying high-level optimizations and also RTL transformations, loop and arithmetic transformations on array based programs, transformations on array based programs leading to the generations of Kahn process networks (KPN) to achieve high degree of parallelism and also transformations applied at the KPN level. Verification methods for the first three transformations on programs not involving arrays employ the model of fini...
2011 IEEE Computer Society Annual Symposium on VLSI, 2011
An automated framework for verification of low power transformations in register transfer level (... more An automated framework for verification of low power transformations in register transfer level (RTL) designs is presented in this paper. Our verification method consists in two steps. In the first step, the datapath interconnection and the controller finite state machine of both the input RTL and the transformed RTL are analyzed by a rewriting based method to obtain the finite state machine with data paths (FSMDs). In the second step, an FSMD based equivalence checking method is deployed to establish equivalence between the RTLs. Our method is is strong enough to handle most of the RTL low power transformations.
2011 IEEE Computer Society Annual Symposium on VLSI, 2011
An equivalence checking method for ensuring correctness of loop and arithmetic transformations in... more An equivalence checking method for ensuring correctness of loop and arithmetic transformations in array intensive programs is presented here. The array data dependence graphs (ADDGs) are used to represent both the input and the transformed behaviours and the correctness of the transformations is ensured by proving equivalence of two ADDGs. In contrast to the existing path based one, we formalize a slice based equivalence of ADDGs. Moreover, normalization of arithmetic expressions and some simplification rules are incorporated to handle arithmetic transformations. Experimental results on several test cases demonstrate the effectiveness of our method.
Fairness of transitions in diagnosability analysis of hybrid systems
2006 American Control Conference, 2006
Page 1. Fairness of Transitions in Diagnosability Analysis of Hybrid Systems S Biswas, C Karfa, H... more Page 1. Fairness of Transitions in Diagnosability Analysis of Hybrid Systems S Biswas, C Karfa, H Kanwar , D Sarkar, S Mukhopadhyay and A Patra Indian Institute of Technology, Kharagpur - 721 302, INDIA. Abstract—Requirement ...
Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques
2010 IEEE Computer Society Annual Symposium on VLSI, 2010
Abstract Code motion techniques are extensively used in the pre-synthesis optimization and the sc... more Abstract Code motion techniques are extensively used in the pre-synthesis optimization and the scheduling phases of high-level synthesis (HLS) of digital circuits for control intensive behaviours. A formal verification method for checking correctness of code motion ...
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Papers by Chandan karfa