Circuit optimization for minimisation of power consumption under delay constraint
We address the problem of optimization of VLSI circuits to minimize power consumption while meeti... more We address the problem of optimization of VLSI circuits to minimize power consumption while meeting performance goals. We present a method of estimating power consumption of a basic or complex CMOS gate which takes the internal capacitances of the gate into account. This method is used to select an ordering of series-connected transistors found in CMOS gates to achieve lower power consumption. We describe a multipass algorithm which makes use of transistor reordering to optimize performance and power consumption of circuits and which has a linear time complexity per pass. The algorithm has been benchmarked on several large examples and the results are presented
European Design Automation Conference, Sep 23, 1994
Designing reliable CMOS chips involve careful circuit design with attention directed to some of t... more Designing reliable CMOS chips involve careful circuit design with attention directed to some of the potential reliability problems such as electromigration and hot carrier eects. This paper considers logic synthesis to handle electromigration and hot carrier degradation early in the design phase. The electromigration and the hot carier eects are estimated at the gate level using signal activity measure, which is the average number of transitions at circuit nodes. Logic can be optimally synthesized suited for dierent applications r equiring dierent types of inputs for higher reliability and low silicon area. Results have been obtained for MCNC synthesis benchmark examples.
Abst rac t . In this paper we address the problem of FPGA place and route for low power dissipati... more Abst rac t . In this paper we address the problem of FPGA place and route for low power dissipation with critical path delay constraints. The presence of a large number of unprogrammed antifuses in the routing architecture adds to the capacitive loading of each net. Hence, a considerable amount of power is dissipated in the routing architecture due to signal transitions occurring at the output of logic modules. Based on primary input signal distributions, signal activities at the internal nodes of a circuit are estimated. Placement and routing are then carried out based on the signal activity measure so as to achieve routability with low power dissipation and required timing. Results show that more than 40% reduction in power dissipation due to routing capacitances can be achieved compared to layout based only on area and timing.
Proceedings of the 31st annual conference on Design automation conference - DAC '94, 1994
We address the problem of long cycle time associated with the basic method of optimizing VLSI cir... more We address the problem of long cycle time associated with the basic method of optimizing VLSI circuits. We are developing a system which makes it possible to carry out arbitrary changes to Register Transfer Level (RTL) source description of the circuit after a gatelevel implementation has been synthesized. The system incrementally updates the gate-level implementation. For typical changes this updation produces comparable results but requires only a small fraction of the time for a complete resynthesis. The system makes use of two object representations. We describe these representations, the maintenance of consistency between them and the incremental synthesis and reoptimization process. Status of the ongoing research on this system is presented. 1 A pre-optimized block is treated by the system as a black
Efficient floorplan enumeration using dynamic programming
1993 IEEE International Symposium on Circuits and Systems
The problem of determining floorplans with optimum area utilization is addressed. To enable the a... more The problem of determining floorplans with optimum area utilization is addressed. To enable the application of dynamic programming, the problem is first transformed into that of determining all floorplans within a specified tolerance of the perfect floorplan. It is shown that for slicing floorplans the problem of enumerating floorplans is related to enumerating two-partitions. Tests to identify redundant partial floorplans are derived, and it is shown that abandoning them does not violate the principle of optimality of dynamic programming. A novel ordering of two-partitions is derived, which enables determination of the wire length cost of successive two-partitions in constant time. Results for a set of benchmark circuits are presented.<<ETX>>
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1993
Circuit activity or the average number of transitions at a node is a measure of power dissipation... more Circuit activity or the average number of transitions at a node is a measure of power dissipation in digital CMOS circuits. Circuit activity is also related to electromigration, and hot electron effects which can degrade reliability. In this paper, we address the problem of both finite state machine and combinational logic synthesis to minimize the average number of transitions at CMOS circuit nodes for battery-operated, low-power operations and increased reliability, while minimizing area at the same time. Logic can be optimally synthesized suited for different applications requiring different types of inputs. Results have been obtained for a wide range of MCNC benchmark examples.
Switch algorithms and architectures for flow control of the available bit rate ATM service
Congestion and the need for congestion control in best-effort packet networks is an inviolate fac... more Congestion and the need for congestion control in best-effort packet networks is an inviolate fact. The Available Bit Rate best-effort ATM service includes congestion control mechanisms. More recently, with continued growth of use of the best-effort Internet, adequacy of TCP congestion control has been investigated. Investigations have pointed to the need for inclusion of additional congestion management specific elements in host and router behavior. To support congestion control of best-effort service, the switches in the ATM (routers in IP) networks need to employ a switch algorithm. Ideally an algorithm must ensure a fair rate allocation, short queues, stability, low complexity of implementation and integrate into real switches. Most algorithms reported to date are found lacking in several regards. We have developed the algorithms SLAPLUS and LAPLUS. The critical path of per cell processing of SLAPLUS and LAPLUS comprises of a number of comparisons and additions, respectively, equal to 1 and the order of logarithm to a large base, e.g. 32, of range of rates. At the memory cost of 4 bits per flow they are free from the errors in measurement suffered by most other algorithms. They drain transient queue build-up and are proven to be locally stable with a large region of attraction and to be globally stable. The performance of the algorithms has been verified through extensive simulation. Supporting the ABR service in Input-Queued Switches presents additional considerations. We have developed solutions and designed the LAPLUS ABR controller for a 320 Gbps Input-Queued Bufferless Crossbar Switch.
In this paper we address the problem of optimization of VLSI circuits to minimize power consumpti... more In this paper we address the problem of optimization of VLSI circuits to minimize power consumptioin while meeting performance goals. We present a method of estimating power consumptioin of a basic or complex CMOS gate which takes the internal cap,acitances of the gate into account. This method is used to select an ordering of series-connected transistors found in CMOS gates to achieve lower power consumption. The method is very efficient when used by library based design styles. We describe a multi-pass algorithm which makes use of transisto1 reordering to optimize performance and power consumption of circuits, which has a linear time complexity per pass and which converges to a solution in ,X small number of passes. Transformations besides transistor reordering can be used by the algorithm. The algorithm h i~s been benchmarked on several large examples and the results are presented.
ACM Transactions on Design Automation of Electronic Systems, 1996
In this article we address the problem of optimization of VLSI circuits to minimize power consump... more In this article we address the problem of optimization of VLSI circuits to minimize power consumption while meeting performance goals. We present a method of estimating power consumption of a basic or complex CMOS gate which takes the internal capacitances of the gate into account. This method is used to select an ordering of series-connected transistors found in CMOS gates to achieve lower power consumption. The method is very efficient when used by library-based design styles. We describe a multipass algorithm that makes use of transistor reordering to optimize performance and power consumption of circuits, has a linear time complexity per pass, and converges to a solution in a small number of passes. Transformations in addition to transistor reordering can be used by the algorithm. The algorithm has been benchmarked on several large examples and the results are presented.
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Papers by Sharat Prasad