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Electrical and Electronic Engineering

The future of microelectronics

Profile image of Robert DoeringRobert Doering

1998, Proceedings of the IEEE

https://doi.org/10.1109/5.658769
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Abstract
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The paper discusses the future of microelectronics, focusing on the semiconductor industry's potential to continue its longstanding productivity improvements driven by technological advancements and market expansion. It analyzes the challenges and opportunities presented by the industry's reliance on Moore's Law and the complexity of coordinating R&D investments within the supply chain. The authors emphasize the importance of roadmaps in predicting technology developments and facilitating collaboration among technologists to sustain growth in microelectronics.

Figures (7)
Fig. 1. The “IC productivity engine.” every 1.5 years (equivalent to the well-established qua- drupling of the number of bits in dynamic random-access memory (DRAM) every three years. The primary enabler of this trend has generally been regarded as our ability to keep shrinking the feature sizes used in building integrated circuits (IC’s) at approximately a rate of 0.7x (equivalent to about 0.5x in area) every three years, corresponding to each “technology generation.” There has been an approximately equal contribution from the rate of increase in chip size, however, also about 2x every three years. PALLAB K. CHATTERJEE, FELLOW, IEEE, AND ROBERT R. DOERING, MEMBER, IEEE
Fig. 1. The “IC productivity engine.” every 1.5 years (equivalent to the well-established qua- drupling of the number of bits in dynamic random-access memory (DRAM) every three years. The primary enabler of this trend has generally been regarded as our ability to keep shrinking the feature sizes used in building integrated circuits (IC’s) at approximately a rate of 0.7x (equivalent to about 0.5x in area) every three years, corresponding to each “technology generation.” There has been an approximately equal contribution from the rate of increase in chip size, however, also about 2x every three years. PALLAB K. CHATTERJEE, FELLOW, IEEE, AND ROBERT R. DOERING, MEMBER, IEEE
Fig. 2. The process uniformity challenge. (1990 JEIDA Report on 150 = 200 mm.) Table 1 Manufacturing-Related IC Characteristics Circa 2005 1) General Characteristics of Process Equipment: By 2005, manufacturing with 300-mm wafers should be at the results of a Japan E ectronic Industry Deve east as mature as for 200 mm today. This is consistent with Semiconductor Equipment and Materials International SEMI)’s 300-mm technology roadmap, which changed significantly since it was first presented at the SEMI Large-Wafer Summit Meeting in Tokyo, Japan, in ovember 1994. The biggest issues in scaling- equipment for larger wafer sizes are usually re uniformity, defect density, and thermal stress. Fig. 2 shows has not process ated to opment Association (JEIDA) survey of device and equipment manufacturers on the degree of difficulty for achieving good process uniformity d uring the scaling from 50-mm wafers. The relative difficulty is expected to be about the same for the 200-300-mm transition, with the exception of oxidation/difi possible fusion, which may undergo the most significant changes in equipment design.
Fig. 2. The process uniformity challenge. (1990 JEIDA Report on 150 = 200 mm.) Table 1 Manufacturing-Related IC Characteristics Circa 2005 1) General Characteristics of Process Equipment: By 2005, manufacturing with 300-mm wafers should be at the results of a Japan E ectronic Industry Deve east as mature as for 200 mm today. This is consistent with Semiconductor Equipment and Materials International SEMI)’s 300-mm technology roadmap, which changed significantly since it was first presented at the SEMI Large-Wafer Summit Meeting in Tokyo, Japan, in ovember 1994. The biggest issues in scaling- equipment for larger wafer sizes are usually re uniformity, defect density, and thermal stress. Fig. 2 shows has not process ated to opment Association (JEIDA) survey of device and equipment manufacturers on the degree of difficulty for achieving good process uniformity d uring the scaling from 50-mm wafers. The relative difficulty is expected to be about the same for the 200-300-mm transition, with the exception of oxidation/difi possible fusion, which may undergo the most significant changes in equipment design.
Table 2. Manufacturing-Related IC Characteristics Circa 2010 3) Etch: Many types of low-pressure but high-density ion sources are currently under development for dry etching at ever increasing aspect ratios. One of these (e.g., helicon, inductively coupled plasma, or electron cyclotron reso- nance) will probably evolve into the preferred technology for most patterned etch applications by the 2000-2005 period.
Table 2. Manufacturing-Related IC Characteristics Circa 2010 3) Etch: Many types of low-pressure but high-density ion sources are currently under development for dry etching at ever increasing aspect ratios. One of these (e.g., helicon, inductively coupled plasma, or electron cyclotron reso- nance) will probably evolve into the preferred technology for most patterned etch applications by the 2000-2005 period.
Fig. 3. Components of theoretical cycle time for single-wafer processing.
Fig. 3. Components of theoretical cycle time for single-wafer processing.
Fig. 4. Sequential processing through evolution of tool configu- rations.
Fig. 4. Sequential processing through evolution of tool configu- rations.
Fig. 5. The manufacturing cost challenge.
Fig. 5. The manufacturing cost challenge.

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References (13)

  1. "National technology roadmap for semiconductors," Semicon- ductor Industry Association, Dec. 1994.
  2. R. R. Doering, "Chickens, eggs, and roadmaps," Solid State Technol., vol. 38, no. 1, pp. 60-61 Jan. 1995.
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  13. E. Regis, "Hacking the mother code," Wired, pp. 136-142, Sept. 1995.

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