Explaining Temporal Differences to Create Useful Concepts for Evaluating States
... G. Barto Department of Computer and Information Science University of Massachusetts, Amherst,... more ... G. Barto Department of Computer and Information Science University of Massachusetts, Amherst, MA 01003 yee@cs.umass ... For example, a board b leading to a win in one step will be recognized only as a ... A useful perspective is that all of the non-null con-cepts de ne groups of ...
Transient effects and characterization methodology of negative bias temperature instability in pMOS transistors
We report a new effect - relaxation of pMOSFET degradation due to negative bias temperature insta... more We report a new effect - relaxation of pMOSFET degradation due to negative bias temperature instability (NBTI). "Apparent" NBTI degradation is reduced ("recovered") by as much as 30-50% after stress interruption, which can increase device lifetime by a factor of 10-30. Some problems associated with extrapolation of degradation with respect to time and stress voltage are also discussed.
IEEE Transactions on Semiconductor Manufacturing, 2000
In this paper, we analyze the impact of process variations on the clock skew of VLSI circuits des... more In this paper, we analyze the impact of process variations on the clock skew of VLSI circuits designed in deep submicrometer technologies. With smaller feature size, the utilization of a dense buffering scheme has been proposed in order to realize efficient and noise-immune clock distribution networks. However, the local variance of MOSFET electrical parameters, such as and DSS , increases with scaling of device dimensions, thus causing large intradie variability of the timing properties of clock buffers. As a consequence, we expect process variations to be a significant source of clock skew in deep submicrometer technologies. In order to accurately verify this hypothesis, we applied advanced statistical simulation techniques and accurate mismatch measurement data in order to thoroughly characterize the impact of intradie variations on industrial clock distribution networks. The comparison with Monte Carlo simulations performed by neglecting the effect of mismatch confirmed that local device variations play a crucial role in the design and sizing of the clock distribution network.
CMOS technology scaling increases the sensitivity of many common circuit blocks to within die var... more CMOS technology scaling increases the sensitivity of many common circuit blocks to within die variation and local mismatch. Accurate assessment of the impact of mismatch on these circuits requires extremely precise estimates of mismatch. This paper analyzes the inaccuracies that occur in mismatch estimation methods that rely on combining measurements from a different die and wafers. Use of device arrays to overcome this limitation is described. Measurements from device arrays on a 0.13 µm CMOS technology suggest that for technologies with good control of device dimensions, 1/sqrt(WL) relationship of mismatch holds over a very large range of device dimensions.
The performance and variability of transistors with nanometer-scale feature sizes is sensitive to... more The performance and variability of transistors with nanometer-scale feature sizes is sensitive to their layout style and environment. This paper describes the use of an enhanced MOS array test structure to provide accurate and precise estimates of the impact of layout on transistor characteristics for an advanced 130nm CMOS technology. Enhanced MOS arrays, combined with statistical analysis of the measurements, provide reliable information on the impact of layout on the transistor characteristics. This can then form the basis for technology development, design rule development and modeling.
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2005
Integrated circuits have to be robust to manufacturing variations. This paper presents a new stat... more Integrated circuits have to be robust to manufacturing variations. This paper presents a new statistical methodology to determine the worst-case corners for a set of circuit performances. Our methodology first estimates response surfaces for circuit performances as quadratic functions of the process parameters with known statistical distributions. These response surface models are then used to extract the worst-case corners in the process parameter space as the points where the circuit performances are at their min/max values corresponding to a specified statistical level. Corners in the process parameter space close to each other are clustered to reduce their number, which reduces the number of simulations required for design verification. We introduce the novel concept of relaxation coefficient to ensure that the corners capture the min/max values of all the circuit performances at the desired statistical level. The corners are realistic since they track the multivariate statistical distribution of the process parameters. Expected worstcase circuit performances can thus be extracted with a small number of simulations suitable for subsequent design verifications. The methodology is demonstrated with examples showing extraction of corners from digital standard cells and also the corners for analog/RF blocks found in typical communication ICs.
Integrated circuits have to be robust to manufacturing variations. This paper presents a new stat... more Integrated circuits have to be robust to manufacturing variations. This paper presents a new statistical methodology to determine the worst-case corners for a set of circuit performances. Our methodology first estimates response surfaces for circuit performances as quadratic functions of the process parameters with known statistical distributions. These response surface models are then used to extract the worst-case corners in the process parameter space as the points where the circuit performances are at their min/max values corresponding to a specified statistical level. Corners in the process parameter space close to each other are clustered to reduce their number, which reduces the number of simulations required for design verification. We introduce the novel concept of relaxation coefficient to ensure that the corners capture the min/max values of all the circuit performances at the desired statistical level. The corners are realistic since they track the multivariate statistical distribution of the process parameters. Expected worstcase circuit performances can thus be extracted with a small number of simulations suitable for subsequent design verifications. The methodology is demonstrated with examples showing extraction of corners from digital standard cells and also the corners for analog/RF blocks found in typical communication ICs.
This article describes several deficiencies with traditional assessments of negative bias tempera... more This article describes several deficiencies with traditional assessments of negative bias temperature instability (NBTI) in pMOS transistors and proposes methods for handling them. These effects include: (a) a decrease in the rate of degradation over time, (b) a deviation of the stress bias dependence of NBTI lifetime from simple analytical models, (c) partial dynamic recovery of apparent NBTI degradation after interruption of stress, and (d) errors well beyond what might naively be expected in lifetime extrapolation due to uncertainties in measurement and modeling of NBTI. These errors can even be several orders of magnitude. If these effects are not adequately considered in NBTI characterization, assessment, benchmarking, and optimization, they could lead excessive expense in product reliability evaluation or, worse, to unanticipated, costly field reliability problems.
Variation in transistor characteristics is increasing as CMOS transistors are scaled to nanometer... more Variation in transistor characteristics is increasing as CMOS transistors are scaled to nanometer feature sizes. This increase in transistor variability poses a serious challenge to the cost-effective utilization of scaled technologies. Meeting this challenge requires comprehensive and efficient approaches for variability characterization, minimization, and mitigation. This paper describes an efficient infrastructure for characterizing the various types of variation in transistor characteristics. A sample of results obtained from applying this infrastructure to a number of technologies at the 90-, 65-, and 45-nm nodes is presented. This paper then illustrates the impact of the observed variability on SRAM, analog and digital circuit blocks used in system-on-chip designs. Different approaches for minimizing transistor variation and mitigating its impact on product performance and yield are also described.
This paper presents a new statistical methodology to simulate the effect of both inter-die and in... more This paper presents a new statistical methodology to simulate the effect of both inter-die and intra-die variation on the electrical performance of analog integrated circuits. The main feature of this methodology is that it accounts for device mismatch by using a number of variables that is asymptotically constant in the limit of perfectly matching devices, and is typically close to the number of independent process factors normally used to account for inter-die process variations only. A unified model of process variation allows the effects of each source of variation and their joint impact to be estimated, thus providing designers more accurate analysis and variance optimization capability. State-of-the-art application examples demonstrate the accuracy and efficiency of this approach.
This paper presents a new statistical methodology to simulate the effect of both inter-die and in... more This paper presents a new statistical methodology to simulate the effect of both inter-die and intra-die variation on the electrical performance of analog integrated circuits. The main feature of this methodology is that it accounts for device mismatch by using a number of variables that is asymptotically constant in the limit of perfectly matching devices, and is typically close to the number of independent process factors normally used to account for inter-die process variations only. A unified model of process variation allows the effects of each source of variation and their joint impact to be estimated, thus providing designers more accurate analysis and variance optimization capability. State-of-the-art application examples demonstrate the accuracy and efficiency of this approach.
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Papers by SHARAD SAXENA