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ture up to the gate deposition step using the Synopsys Sentaurus 2005.12 process simulator.! We make three observations.

Figure 2 ture up to the gate deposition step using the Synopsys Sentaurus 2005.12 process simulator.! We make three observations.

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IMPACT OF STI WIDTH ON THE PERFORMANCE OF SEVERAL STANDARD CELLS B. Stress Modeling Techniques now. STI usually exerts compressive stress along the channel (i.e., the current flow direction), which improves PMOS de- vice mobility. The opposite type of stress, i.e., tensile stress, degrades the PMOS performance in this direction. NMOS is, in general, complementary to PMOS in terms of how it is affected by stress, and its mobility degrades because of STI stress.
IMPACT OF STI WIDTH ON THE PERFORMANCE OF SEVERAL STANDARD CELLS B. Stress Modeling Techniques now. STI usually exerts compressive stress along the channel (i.e., the current flow direction), which improves PMOS de- vice mobility. The opposite type of stress, i.e., tensile stress, degrades the PMOS performance in this direction. NMOS is, in general, complementary to PMOS in terms of how it is affected by stress, and its mobility degrades because of STI stress.
Fig. 1. Change in STIW on increasing the intercell spacing from 0 to 5 jum. Fig. 2. Stress components on a unit volume.
Fig. 1. Change in STIW on increasing the intercell spacing from 0 to 5 jum. Fig. 2. Stress components on a unit volume.
Fig. 3. STIW parameter. LOD is accounted for in BSIM models. The STIW impact is not modeled. Parallel and orthogonal distances with respect to a transistor is also indicated in the figure.
Fig. 3. STIW parameter. LOD is accounted for in BSIM models. The STIW impact is not modeled. Parallel and orthogonal distances with respect to a transistor is also indicated in the figure.
Fig. 4. Model versus data. Plot with crosses corresponding to the data. Each data point corresponds to a DOE instance.
Fig. 4. Model versus data. Plot with crosses corresponding to the data. Each data point corresponds to a DOE instance.
LINER STRESS ANALYSIS DOE PARAMETERS
LINER STRESS ANALYSIS DOE PARAMETERS
Fig. 7. Critical paths instantiate cell-level netlists, which instantiate device- level models. Our modifications to the traditional flow to model STIW- dependent stress are shown in bold. Fig. 6. Instantiation of device-level models in a standard cell SPICE netlist. The parameters added in BSIM 4.3.0 to partially model stress are shown in bold.
Fig. 7. Critical paths instantiate cell-level netlists, which instantiate device- level models. Our modifications to the traditional flow to model STIW- dependent stress are shown in bold. Fig. 6. Instantiation of device-level models in a standard cell SPICE netlist. The parameters added in BSIM 4.3.0 to partially model stress are shown in bold.
Fig. 8. Calculation of parameters PL, PR, NL, and NR from intercell spacings and active-to-cell-boundary spacings.
Fig. 8. Calculation of parameters PL, PR, NL, and NR from intercell spacings and active-to-cell-boundary spacings.
Fig. 9. Generic standard cell, with polysilicon positive active regions (PRX), negative active regions (NRX), and cell boundary shown.
Fig. 9. Generic standard cell, with polysilicon positive active regions (PRX), negative active regions (NRX), and cell boundary shown.
Fig. 10. Generic cell of Fig. 9 optimized with fill insertion for setup-time criticality. Fig. 11. Row of standard cells after active-layer fill insertion for setup-time improvement. The cells patterned with diagonal lines are the setup-critical cells, and the filled rectangles are the inserted active-layer fills.
Fig. 10. Generic cell of Fig. 9 optimized with fill insertion for setup-time criticality. Fig. 11. Row of standard cells after active-layer fill insertion for setup-time improvement. The cells patterned with diagonal lines are the setup-critical cells, and the filled rectangles are the inserted active-layer fills.
Input: Placed design; set of timing critical cells, T; set of fixed cells, F; maximum spacing to create, $ Output: New placement with altered inter-cell Fig. 12. Pseudocode for intrarow placement optimization.
Input: Placed design; set of timing critical cells, T; set of fixed cells, F; maximum spacing to create, $ Output: New placement with altered inter-cell Fig. 12. Pseudocode for intrarow placement optimization.
Fig. 13. Placement change and fill insertion for setup-time optimization. A standard cell row is shown before optimization, after placement perturbation, and after fill insertion. The cells patterned by diagonal lines are the setup- critical cells for which timing is optimized. Fixed cells are patterned with the brick pattern, and their placement cannot be changed.
Fig. 13. Placement change and fill insertion for setup-time optimization. A standard cell row is shown before optimization, after placement perturbation, and after fill insertion. The cells patterned by diagonal lines are the setup- critical cells for which timing is optimized. Fixed cells are patterned with the brick pattern, and their placement cannot be changed.
TEST CASES USED IN EXPERIMENTAL VALIDATION. MCT Is THE MINIMUM CYCLE TIME TABLE VI
TEST CASES USED IN EXPERIMENTAL VALIDATION. MCT Is THE MINIMUM CYCLE TIME TABLE VI
impact 1s attected when stress liners are used for mobility improvement. Through TCAD simulations, we observe the impact of stress liner intrinsic stress and stress liner height on STI stress. Furthermore, STI height is a process parameter that can change the stress levels transferred to the channel. Hence, we also provide additional simulation results for STI height impact on stress. On the circuit-level optimization side, we have enhanced our optimization and repeated the experimentation with the improved models and realistically implemented test cases. Additionally, we compare the proposed stress-aware timing analysis with traditional corner-based timing analysis by turning on and off our stress modeling on top of BSIM models. This analysis quantifies the accuracy lost on not considering STI stress impact in the timing analysis. The improvements described in this paper thus provide a more complete stress optimization framework based on an extensive set of analyses.
impact 1s attected when stress liners are used for mobility improvement. Through TCAD simulations, we observe the impact of stress liner intrinsic stress and stress liner height on STI stress. Furthermore, STI height is a process parameter that can change the stress levels transferred to the channel. Hence, we also provide additional simulation results for STI height impact on stress. On the circuit-level optimization side, we have enhanced our optimization and repeated the experimentation with the improved models and realistically implemented test cases. Additionally, we compare the proposed stress-aware timing analysis with traditional corner-based timing analysis by turning on and off our stress modeling on top of BSIM models. This analysis quantifies the accuracy lost on not considering STI stress impact in the timing analysis. The improvements described in this paper thus provide a more complete stress optimization framework based on an extensive set of analyses.
TRADITIONAL VERSUS STRESS- AWARE TIMING ANALYSIS AfAdiits Vail TIMING OPTIMIZATION RESULTS WITH FILL INSERTION. MCT IS THE MINIMUM CYCLE TIME. WL IS THE WIRE LENGTH TPD STANDS FOR TOP PATHS DELAY AND IS THE SUM OF THE DELAYS OF THE TOP 100 CRITICAL PATHS
TRADITIONAL VERSUS STRESS- AWARE TIMING ANALYSIS AfAdiits Vail TIMING OPTIMIZATION RESULTS WITH FILL INSERTION. MCT IS THE MINIMUM CYCLE TIME. WL IS THE WIRE LENGTH TPD STANDS FOR TOP PATHS DELAY AND IS THE SUM OF THE DELAYS OF THE TOP 100 CRITICAL PATHS
Fig. 14. Path delay histograms for the top 200 critical paths of test case AES before and after optimization. TIMING OPTIMIZATION RESULTS WITH PLACEMENT AND FILL INSERTION. MCT IS THE MINIMUM CYCLE TIME. WL IS THE WIRE LENGTH TPD STANDS FOR TOP PATHS DELAY AND IS THE SUM OF THE DELAYS OF THE TOP 100 CRITICAL PATHS
Fig. 14. Path delay histograms for the top 200 critical paths of test case AES before and after optimization. TIMING OPTIMIZATION RESULTS WITH PLACEMENT AND FILL INSERTION. MCT IS THE MINIMUM CYCLE TIME. WL IS THE WIRE LENGTH TPD STANDS FOR TOP PATHS DELAY AND IS THE SUM OF THE DELAYS OF THE TOP 100 CRITICAL PATHS
Related topics:
Timing AnalysisComputer HardwareWorst-Case Execution Time AnalysisProcess SimulationStress EngineeringDesign for ManufactureCritical Path MethodElectrical and Electronic EngineeringPlace and RouteActive Layer
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