Place and Route

Rivest-Shamir-Adleman (RSA) cryptosystem uses modular multiplication for encryption and decryption. So, performance of RSA can be drastically improved by optimizing modular multiplication. This paper proposes a new parallel, high-radix Montgomery multiplier for 1024 bits multi-core RSA processor. Each computation step operates in radix 4. The computation speed is increased by more than 4 times. We also implement a True Random Number Generator based resilience block to protect the coprocessor against power attacks.

Excess delay that each component of a design can tolerate under a given timing constraint is referred to as delay budget. Delay budgeting has been widely exploited to improve the design quality in VLSI CAD flow. The objective of the delay budgeting problem investigated in this paper is to maximize the total delay budget assigned to each node in a directed acyclic graph under a given timing constraint. Due to discreteness of the timing of the components in the libraries during design optimization flow, discrete solution for delay budgeting is essential. We present an optimal integer delay budgeting algorithm. We prove that the problem can be solved optimally in polynomial time. In addition, we look at different extensions of the delay budgeting problem, such as maximization of weighted summation of delay budgets assigned to the nodes with constraints on lower bound and upper bound on the delay budget allocated to each node. We prove that for both aforementioned extensions, our algorithm can produce an optimal integer solution in polynomial time. Our algorithm is generic and can be applied in different design tasks at different levels of abstraction. We applied our proposed optimal delay budgeting algorithm in library mapping during datapath synthesis on an FPGA platform ,using pre-optimized cores of FPGA libraries. For each application, we go through synthesis and place and route stages in order to obtain accurate results. Our optimal algorithm outperforms ZSA algorithm [4] in terms of area by ½¼± on average for all applications. In some applications, optimal delay budgeting can speedup runtime of place and route up to ¾ times.

Delay budget is an excess delay each component of a design can tolerate under a given timing constraint. Delay budgeting has been widely exploited to improve the design quality. We present an optimal integer delay budgeting algorithm. Due to numerical instability and discreteness of libraries of components during library mapping in design optimization flow, integer solution for delay budgeting is essential. We prove that integer budgeting problem -a 20-year old open problem in design optimization [7]-can be solved optimally in polynomial time. We applied optimal delay budgeting in mapping applications on FPGA platform using pre-optimized cores of FPGA libraries. For each application we go through synthesis and place and route stages in order to obtain accurate results. Our optimal algorithm outperforms ZSA algorithm in terms of area by 10% on average for all applications. In some applications, optimal delay budgeting can speedup runtime of place and route up to 2 times.

Partial dynamic reconfiguration is an emerging area in FPGA designs which is used for saving device area and cost. In order to reduce the reconfiguration overhead, two consecutive similar sub-designs should be placed in the same locations to get the maximum reuse of common components. This requires that all the future designs be considered while floorplanning for any given design. In this work, we introduce a new multi-layer sequence pair representation based floorplanner that allows overlap of static and non-static components of multiple designs and guarantees a feasible overlapping floorplan with minimal area packing. The multi-layer sequence pair is an efficient representation that helps in reducing the total floorplan runtime significantly. It also improves the design quality of the whole sequence as floorplans of all the designs are simultaneously computed. In our experiments, compared to a traditional sequential floorplanner, our floorplanner removes infeasibility in many designs, achieves an improvement of clock period by 12% on average and reduces the place and route time by as much as 3 times. It also reduces the average wirelength by 50% in the designs. Our proposed floorplanner could be used for finding high quality floorplans for applications that use partial reconfiguration.

Excess delay that each component of a design can tolerate under a given timing constraint is referred to as delay budget. Delay budgeting has been widely exploited to improve the design quality in VLSI CAD flow. The objective of the delay budgeting problem investigated in this paper is to maximize the total delay budget assigned to each node in a directed acyclic graph under a given timing constraint. Due to discreteness of the timing of the components in the libraries during design optimization flow, discrete solution for delay budgeting is essential. We present an optimal integer delay budgeting algorithm. We prove that the problem can be solved optimally in polynomial time. In addition, we look at different extensions of the delay budgeting problem, such as maximization of weighted summation of delay budgets assigned to the nodes with constraints on lower bound and upper bound on the delay budget allocated to each node. We prove that for both aforementioned extensions, our algorithm can produce an optimal integer solution in polynomial time. Our algorithm is generic and can be applied in different design tasks at different levels of abstraction. We applied our proposed optimal delay budgeting algorithm in library mapping during datapath synthesis on an FPGA platform ,using pre-optimized cores of FPGA libraries. For each application, we go through synthesis and place and route stages in order to obtain accurate results. Our optimal algorithm outperforms ZSA algorithm [4] in terms of area by ½¼± on average for all applications. In some applications, optimal delay budgeting can speedup runtime of place and route up to ¾ times.

Delay budget is an excess delay that each component of a design can tolerate under a given timing constraint. Delay budgeting has been widely exploited to improve the design quality. This paper presents the idea of incrementally re-assigning the delay budgets allotted to different components of a design, which leads to avoiding the re-execution of the intensive budget assignment procedure in each iteration of the tools. Given a budgeting solution and a local change, our approach can re-assign the budget values such that the timing constraints are met. More importantly, it only explores the components locally, which preserves its incremental nature. General sufficient conditions have been presented under which, our approach is provably effective. Experimental results on converting non-integral budgeting assignments to integral ones, advocate our technique's efficiency. The budget assignments have been used to map a number of applications to an FPGA platform. The results have been compared to other existing methods. Our approach exhibits ¿¾± improvement over other similar techniques in terms of total delay budget assigned to design components. This can be exploited to significantly improve other design metrics such as area and tool runtime. Our experimental results have verified that.

In order to take into account physical design effects, a designer needs a feedback mechanism during interactive data path synthesis. In this paper, we propose a hypergraph model and a back-annotation algorithm which provide a feedback mechanism for back-annotation from physical designs to behavioral descriptions. Given a control-data flow graph and its structural design, this back-annotation technique can not only evaluate the design quality but can also feedback the delay to each edge and node in the graph. Therefore, a designer can identify the critical paths and improve the design. The hypergraph model and the back-annotation algorithm allow us to bridge the gap between the behavioral description and the physical design.

This paper examines the use of a switch based architecture to implement a Radix-2 decimation in frequency Fast Fourier Transform Engine. The architecture interconnects M processing elements with 2*M memories. An algorithm to detect and resolve memory access contention is presented. The implementation of 1024-point FFTs with 2 processing elements is discussed in detail, including timing and place-and-route results. The switch based architecture provides a factor of M speedup over a single processing element realization.

In order to prevent the SPA (Simple Power Analysis) attack against modular exponentiation algorithms, a multiply-always implementation is generally used. Witteman et al. introduced in [14] a new cross-correlation power analysis attack against the multiplyalways implementation. We suggest two new algorithms, resistant to this attack and also to other known attacks. The first algorithm is an alternative approach to exponentiation algorithms used in cryptography, which usually receive as an input some representation (e.g. binary) of the exponent. In our approach both the exponent and the result are functions (not necessarily easily invertible) of the exponentiation algorithm input. We show that this approach can have a good performance and that it is also resistant to several known attacks, especially to the cross-correlation power analysis and also to the attack described in [9]. It is particularly relevant for cryptographic schemes in which the private exponent can be chosen arbitrar...

Internet of Things (IoT) is marked by resource-constrained devices. Information security is the main challenge that arises due to the wireless transmission of data by ubiquitous sensors. In this work, we have presented a lightweight advance encryption scheme (AES) that can be used in small IoT devices. Galois field arithmetic has been used to minimize the size of the S-box. Slice consumption and throughput are two contradictory parameters in AES design. The design tries to achieve a tradeoff between these two parameters. With a separate S-box for the key expansion, a high throughput in the range of 52-163 Mbps has been achieved on different FPGAs. In terms of throughput, it matches the latest lightweight designs and outperforms older ones. It occupies 73 slices on an Artix-7 FPGA. When compared to existing AES designs, the design achieves area savings in the range of 4%-78.33%. In slice consumption, it is on par with most of the lightweight ciphers designed for IoT. The most remarkable feature of the design is its efficiency. It outperforms existing lightweight AES variants with a typical throughput per slice of 210 kbps/slice to 1.409 Mbps/slice. On Virtex-5, AES-8 has outperformed lightweight ciphers like Shadow-64, LEA-128, DULBC-80/128, and QARMA. A 24%-67% resource reduction has been achieved from these ciphers. It makes the proposed cipher suitable for application in IoT security.

During the last decade, the complexity and size of circuits have been rapidly increasing, placing a stressing demand on industry for faster and more efficient CAD tools for VLSI design. One major problem is the computational requirements for optimizing the place and route operations of a VLSI circuit. Thus, this paper investigates the feasibility of using Reconfigurable Computing platforms to improve the perforinance of CAD optimization algorithms for the VLSI circuit partitioning problem. The proposed Reconfigiirable Computing Genetic Algorithm architecture achieved a five times speedup over conventional software implementation while maintaining 88% solution quality. Furthcrniore, a Reconfigurable computing based Hybrid Algorithm improved upon this solution while using a fraction of the execution Lime required by the conventional software based approaches.

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Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip power. This paper proposes to deploy sleep transistor insertion (STI) in the clock tree of datapaths in ASICs or in general-purpose processors in order to reduce leakage power. It characterizes the effect of sleep transistor sharing and sizing on clock tree wakeup time, leakage power, and propagation delay. It then uses these characteristics during leakage power optimization. It describes a post synthesis sleep transistor insertion (PSSTI), a heuristic clustering algorithm for sleep transistor insertion with the objective of total power minimization in a given clock tree. Sleep transistor sharing and sizing are deployed in order to meet the clock skew and wakeup delay constraints. The potential benefits of STI in ASIC design are evaluated using a standard industrial VLSI-CAD flow including sleep-transistor insertion and routing after the clock synthesis and place-and-route of the benchmark circuits. The results show that the clock tree leakage power is reduced by 19-32% depending on the topology of the synthesized clock tree. We also apply PSSTI in the clock tree of the datapaths in general-purpose processors using architectural control of the sleep mode. This achieves a reduction in the leakage power and the dynamic power of the clock tree within different datapath components (adder, multiplier, etc.) of as much as 80%. This approach is also applicable to other on-chip structure where inverters are large in size and commonly used, e.g. SRAMs or networks-on-a-chip, which combined with the clock tree savings will significantly reduce processor or ASIC overall power consumption.

Modern FPGA architectures provide ample routing resources so that designs can be routed successfully. The routing architecture is designed to handle versatile connection configurations. However, providing such great flexibility comes at a high cost in terms of area, delay and power. We propose a new FPGA routing architecture that utilizes a mixture of hardwired and traditional flexible switches. The result is about 30% reduction in leakage power consumption, 5% smaller area and 20% shorter delays, which translates to 25% increase in clock frequency. Despite the increase in clock speeds, the overall power consumption is reduced.

Routing of the nets in Field Programmable Gate Array (FPGA) design flow is one of the most time consuming steps. Although Versatile Place and Route (VPR), which is a commonly used algorithm for this purpose, routes effectively, it is slow in execution. One way to accelerate this design flow is to use parallelization. Since VPR is intrinsically sequential, a set of parallel algorithms have been recently proposed for this purpose (ParaLaR and ParaLarPD). These algorithms formulate the routing process as a Linear Program (LP) and solve it using the Lagrange relaxation, the sub-gradient method, and the Steiner tree algorithm. Out of the many metrics available to check the effectiveness of routing, ParaLarPD, which is an improved version of ParaLaR, suffers from large violations in the constraints of the LP problem (which is related to the minimum channel width metric) as well as an easily measurable critical path delay metric that can be improved further. In this paper, we introduce a set of novel Lagrange heuristics that improve the Lagrange relaxation process. When tested on the MCNC benchmark circuits, on an average, this leads to halving of the constraints violation, up to 10% improvement in the minimum channel width, and up to 8% reduction in the critical path delay as obtained from ParaLarPD. We term our new algorithm as ParaLarH. Due to the increased work in the Lagrange relaxation process, as compared to ParaLarPD, ParaLarH does slightly deteriorate the speedup obtained because of parallelization, however, this aspect is easily compensated by using more number of threads.

This paper presents an interleaver / deinterleaver architecture that meets all the requirements for complex SDR applications, basically, it offers enough flexibility to implement about any interleaving method. This architecture allows to run several interleaving processes concurrently, either with the same method or with different ones, enabling high performance multi-radio applications with the same hardware. This architecture integrates the interleaving altogether with the rate matching and the frame equalization - two closely related processing -, improving the overall system's performance. While the reconfigurable interleaver can be shared among several steps of the communications process, it would be very inefficient to use it for the internal interleaving of turbo coding or decoding. It would require a large communication bandwidth between the interleaver and the channel coder / decoder. This paper also discusses the implementation of two highly optimized interleaver archi...

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Place and Route Techniques for FPGA Architecture Advancement Akshay Sharma Chair of the Supervisory Committee: Associate Professor Scott Hauck Electrical Engineering Efficient placement and routing algorithms play an important role in FPGA architecture research. Together, the place-and-route algorithms are responsible for producing a physical implementation of an application circuit on the FPGA hardware. The quality of the place-and-route algorithms has a direct bearing on the usefulness of the target FPGA architecture. The benefits of including powerful new features on an FPGA might be lost due to the inability of the place-and-route algorithms to fully exploit these features. Thus, the advancement of FPGA architectures relies heavily on the development of efficient place-and-route algorithms. The subject of this dissertation is the development of place and route techniques that could play an important role in FPGA architecture advancement. The work presented in this dissertation is divided into two topics: Architecture-Adaptive FPGA Placement-The first topic deals with the development of a universal placement algorithm (Independence) that adapts to the target FPGA architecture. We have successfully demonstrated Independence's adaptability to three different architectures. Our results also show that Independence is able to adapt to a class of routing-poor FPGA architectures. Pipelined Routing-The second topic focuses on the development of a routing algorithm (PipeRoute) that can be used to route application circuits on high-speed, pipelined FPGA architectures. In our experiments, PipeRoute was able to successfully route netlists on a coarse-grained pipelined architecture. The algorithm incurred a 20% overhead when compared to a realistic lower bound. We also used PipeRoute in an exploratory flow to find an architecture that was up to 19% better than a hand-architected pipelined architecture. i

This work describes a novel system for device development that automates and fully integrates the workflow from test chip construction, from placement and routing to electrical test program generation. In addition to accelerating test chip and test program development, this system facilitates parameterized data analysis, thereby providing a framework that finally allows the user to realize the full benefits of complex and elegant experimental device designs. By utilizing a centralized database and eliminating parameter re-entry, the automation provided by this integrated approach eliminates many of the sources for human error while maximizing reuse between technologies.

En éste artículo se presenta una herramienta para la generación automática de multiplicadores paralelos en VHDL para síntesis. Se intenta asistir al diseñador de DSP a medida sobre plataformas FIPSOC (de Sidsa) o Virtex (de Xilinx). Se generan los siete multiplicadores: McCanny -McWhirter, De Mori, Hatamian y Cash, Ripple Carry, Carry Save, Guild y De Mori -Guild; con y sin pipelining. CLAVES: generación automática de circuitos, síntesis de circuitos, CAE, multiplicación. Como contrapartida a la programación de aplicaciones sobre una computadora de uso general, mediante la adaptación del conjunto de instrucciones a la aplicación (programación de arquitectura de Von Neumann), se puede considerar el desarrollar una aplicación con un circuito digital totalmente a medida de la aplicación. Hace unos años eso era impensable para volúmenes pequeños o medianos, pero la FPGA ha producido una reducción de costos que hacen posible diseñar máquinas de cálculo totalmente a medida de la aplicación, aún para series muy pequeñas con costos bajos. En el desarrollo de sistemas empotrados (embedded) y sistemas digitales de tratamiento de señales hay necesidad de módulos tales como: máquinas de estado, multiplicadores, divisores, cálculos trigonométricos, operaciones con matrices, microcontroladores, módulos de comunicación, interfaces para buses estándar, controladores de vídeo, etc.. Por otro lado, la disponibilidad de FPGAs de tamaños medianos (de más de 20.000 puertas) y grandes (de entre 200.000 y 1.000.000 de puertas) ha permitido aplicaciones con diseños basados en lenguajes de descripción de hardware (VHDL, Verilog, Hardware-C, Handel-C, Abel, etc.) con síntesis automática. Utilizando estas herramientas se ha extendido el desarrollo y comercialización de módulos IP (de Propiedad Intelectual), normalmente para microcontroladores, procesadores, DSP, entre otras aplicaciónes. Esta alternativa permite al diseñador comprar los diseños de productos de funcionamiento ya comprobado, que puedan ser incorporados al proyecto como un componente más. Para el desarrollo de aplicaciones hardware a medida de las aplicaciones normalmente se debe comprar un módulo IP con las características fijadas al momento de la compra y que son inamovibles (lo que no permite la actualización sin costo del producto).

La estimación de consumo medio en circuitos CMOS es un problema aun no resuelto completamente debido a la dificultad en la estimación de la actividad de conmutación. Cuando se trabaja con FPGAs comerciales, a este problema se añade la falta de información sobre las capacidades físicas de los nodos del circuito, que se necesita también para estimar el consumo de potencia. En este trabajo se presenta una técnica general para estimar la capacidad de los nodos en un diseño implementado en una FPGA comercial basada en la relación entre capacidad, retardo medio y fan out del nodo. Los resultados preliminares indican que esta solución para estimar capacidades físicas es aplicable con un error tolerable.

In this work, we parameterize and explore the interconnect structure of pipelined FPGAs. Specifically, we explore the effects of interconnect register population, length of registered routing track segments, registered IO terminals of logic units, and the flexibility of the interconnect structure on the performance of a pipelined FPGA. Our experiments with the RaPiD [4] architecture identify tradeoffs that must be made while designing the interconnect structure of a pipelined FPGA. The post-exploration architecture that we found shows a 19% improvement over RaPiD, while the area overhead incurred in placing and routing benchmarks netlists on the post-exploration architecture is 18%.

This paper describes a new detailed routing algorithm, speciffically designed for those types of architecturesthat are found on the most recent generations of Field-Programmable Gate Arrays (FP-GAs). The algorithm, called RAISE, can be applied to a broad range of optimizations problems and has been used for detailed routing of symmetrical FPGAs, whose routing architecture consists of rows and columns of logic cells interconnected by routing channels. RAISE (Router using AadaptIve Simulated Evolution) searches not only for a possible solution, but tries to find the one with minimum delay. Excelent routing results have been obtained over a set of several benchmark circuits getting solutions close to the minimum number of tracks.

Reverse body biasing (RBB) is often used to reduce the leakage power of a device. However, recent research has shown that if this applied RBB is too high, the leakage power can actually increase due to the contribution of Band-to-Band Tunneling (BTBT) currents. Hence, there exists an optimal RBB value at which the leakage is minimum. This optimum point can vary with temperature and process variations. In this paper we show that it is desirable to operate at the optimal RBB point which minimizes total leakage. We present a scheme that monitors the total leakage current (the sum of the sub-threshold, BTBT and gate leakage) of an IC with a representative leaking device and, using this monitored value, automatically finds the optimum RBB value across temperature and process corners, using a self-adjusting circuit. Our approach has a modest placed-and-routed area utilization, and a low power consumption.

For the implementation of error-correcting codes, cryptographic algorithms, and the construction of homomorphic methods for privacy-preserving, there is a need for methods of performing operations on elements GF(2m) that have low computational complexity. This paper analyzes the existing methods of performing operations on the elements GF(2m) and proposes a new method based on the use of a sparse table of elements of this field. The object of research is the processes of operations in information security systems. The subject of research is methods and algorithms for performing operations on elements GF(2m). The purpose of this research is to develop and improve methods and algorithms for performing operations on elements GF(2m) to reduce their computational complexity. Empirical methods and methods of mathematical and software modeling are used in the research. Existing and proposed algorithms are implemented using the C# programming language in the Visual Studio 2015 development environment. Experimental research of existing and developed algorithms was carried out according to the proposed method, which allows to level the influence of additional parameters on the results of the research. The conducted research on methods for performing operations on the elements GF(2m) shows the expediency of using a sparse table of field elements. This approach makes it possible to reduce the amount of RAM required for the software and hardware implementation of the developed method compared to the classical tabular method, which requires storage of a full table of correspondence of the polynomial and index representation of the field elements. In addition, the proposed method gives an increase in speed of more than 4 times for the operations of calculating the multiplicative inverse element and exponentiation. As a result, the proposed method allows to reduce the computational complexity of error-correcting codes, cryptographic algorithms, and the homomorphic methods for privacy-preserving.

In this paper we present a new synthesis and layout approach that avoids the normal iterations between synthesis, technology mapping and layout, and increases routing by abutment. It produces shorter and more predictable delays, and sometimes even layouts with reduced areas. This scheme equalizes delays along different paths, which makes low granularity pipelining a reality, and hence we can clock these circuits at much higher frequencies, compared to what is possible in a conventionally designed circuit. Since any circuit can be clocked at a fixed rate, this method does not require timingdriven synthesis. We propose the logic and layout synthesis schemes and algorithms, discuss the physical layout part of the process, and support our methodology with simulation results.

Networks-on-Chip is a recent solution paradigm adopted to increase the performance of Multi-core designs. The key idea is to interconnect various computation modules (IP cores) in a network fashion and transport packets simultaneously across them, thereby gaining performance. In addition to improving performance by having multiple packets in flight, NoCs also present a host of other advantages including scalability, power efficiency, and component re-use through modular design. This work focuses on design and development of high performance communication architectures for FPGAs using NoCs Once completely developed, the above methodology could be used to augment the current FPGA design flow for implementing multi-core SoC applications. We design and implement an NoC framework for FPGAs, Multi-Clock On-Chip Network for Reconfigurable Systems (MoCReS).We propose a novel micro-architecture for a hybrid two-layer router that supports both packet-switched communications, across its local and directional ports, as well as, time multiplexed circuitswitched communications among the multiple IP cores directly connected to it. Results from place and route VHDL models of the advanced router architecture show an average improvement of 20.4% in NoC bandwidth (maximum of 24% compared to a traditional NoC). We parameterize the hybrid router model over the number of ports, channel width and bRAM depth and develop a library of network components (MoClib Library). For your paper to be published in the conference proceedings, you must use this document as both an instruction set and as a template into which you can type your own text. If your paper does not conform to the required format, you will be asked to fix it.

We have developed a design flow from Verilog/VHDL to layout that mitigates the timing closure problem, while requiring no timing driven placement or routing tools. Timing issues are confined to the cell sizer, allowing the placement algorithm to focus solely on net lengths, resulting in superior layout densities and much lower power. The primary enablers to this new technology are: 1) gridded transistor sizing, 2) variable die routing that allows each net to be routed in the shortest possible length, 3) simultaneous cell placement, routing, gate sizing, and clock tree insertion, and 4) an effective incremental (ECO) placement that preserves net lengths from one iteration to the next. The variable die router is the key enabler. Superior placement and routing densities result from this new variable die approach. In addition, each net is routed at or near minimum length, and thus minor placement changes or cell size changes do not materially impact net lengths.

In the recent years, Xilinx devices, like the XC6200, were the preferred solutions for evolving digital systems. In this paper, we present a new System-On-Chip, the POEtic chip, an alternative for evolvable hardware. This chip has been specifically designed to ease the implementation of bio-inspired systems. It is composed of a microprocessor, and a programmable part, containing basic elements, like every standard Field Programmable Gate Array, on top of which sits a special layer implementing a dynamic routing algorithm. Online on-chip evolution can then be processed, as every configuration bit of the programmable array can be accessed by the microprocessor. This new platform can therefore replace the Xilinx XC6200, with the advantage of having a processor inside.

W hether one looks outside the window or stands in front of a mirror, nature's work is evident in all its glory. Be it a pine tree, a flea, or a human being, nature has designed highly complex machines, the construction of which is still well beyond our current engineering capabilities. Nature is the grandest engineer known to man-though a blind one at that: her designs come into existence through the slow process, over millions of years, known as evolution by natural selection [2]. As put forward by Charles Darwin in his 1859 masterpiece, On the Origin of Species, evolution is based on "...one general law, leading to the advancement of all organic beings, namely, multiply, vary, let the strongest live and the weakest die.'' [1].

This paper examines the use of a switch based architecture to implement a Radix-2 decimation in frequency Fast Fourier Transform Engine. The architecture interconnects M processing elements with 2*M memories. An algorithm to detect and resolve memory access contention is presented. The implementation of 1024-point FFTs with 2 processing elements is discussed in detail, including timing and place-and-route results. The switch based architecture provides a factor of M speedup over a single processing element realization.

A synthesis methodology for multiple scan trees that considers output pin limitation, scan chain routing length, test application time, and test data compression rate simultaneously is proposed in this paper. Multiple scan trees, also known as a scan forest, greatly reduce test data volume and test application time in system-on-chip testing. However, previous research on scan tree synthesis rarely considered issues such as, routing length and output port limitation, and hence created scan trees with a large number of scan output ports and excessively long routing paths. The proposed algorithm provides a mechanism that effectively reduces test time and test data volume, and routing length under output port constraint. As a result, very few or no output compressors are required, which significantly reduces the hardware overhead.

The arithmetic Product-of-Sum (POS) is a frequently used datapath operation in modern integrated circuit designs, especially in Digital Signal Processing (DSP) and Graphics applications. Since POS blocks typically incur a significant amount of delay, these blocks often become critical in determining the performance of the entire chip. Hence, to improve the efficiency of this operation, it is desirable to use an architecture with good performance characteristics. This paper presents an architectural optimization approach to synthesize a faster POS block, which can be very useful in reducing the delay of the design without significantly impacting its area. Our architecture for the Product-of-Sum (POS) block is primarily based on the analysis of the corresponding Sum-of-Products (SOP) expression or a hybrid combination of the POS and the SOP expressions. In our technique, we extensively use arrival-times of the input signals of the Product-of-Sum block to determine the suitable architecture of the block. We have tested our approach using a variety of POS blocks implemented under varying timing constraints and technology libraries. Experimental results demonstrate that our proposed solution is 10.92% faster (and 3.54% larger) than the corresponding block generated by a commercially available best-in-class datapath synthesis tool. These improvements were verified on placed-and-routed designs as well.

Modern three-dimensional (3D) designs, in which the active devices are placed in multiple layers using 3D integration technologies, are helping to maintain the validity of Moore's law in today's nano era. However, progress in commercial 3D ICs has been slow due to multiple reasons. One of them is the lack of appropriate physical design (layout) tools that take the new constraints arising from the third dimension into account. In this paper, an overview of physical design's challenges in the new 3-dimensional context are presented. Specifically, we investigate the physical design steps of floorplanning, placement, routability prediction and routing. New 3D-tailored design methodologies are presented that are capable of addressing 3D-specific design challenges.

The present paper describes an Electronic System Level (ESL) design methodology which was established and employed in the creation of a H.264/AVC baseline decoder. The methodology involves the synthesis of the algorithmic description of the functional blocks that comprise the decoder, using a high level synthesis tool. Optimization and design space exploration is carried out at the algorithmic level before performing logic synthesis. Final, post-place and route implementation results show that the decoder can operate at the target frequency of 100 MHz and meet real time requirements for QCIF frames.

Physical synthesis is a relatively young field in Electronic Design Automation. Many published optimizations for physical synthesis end up hurting the quality of the final design, often because they neglect important physical aspects of the layout, such as long wires or routing congestion. Our work defines and explores the concept of physical safeness and evaluates empirically its impact on route length, via count and timing. In addition, we propose a new physically safe and logically sound optimization, called SafeResynth, which provides immediately-measurable improvements without altering the design's functionality. SafeResynth can enhance circuit timing without detrimental effects on route length and congestion. We achieve these improvements by performing a series of netlist transformations and replacements that are individually evaluated for logical soundness (that is, they do not alter the logic functionality) and for physical safeness. When used alone, SafeResynth improves circuit delay of IWLS'05 benchmarks by 11% on average after routing, while increasing route length by less than 0.2%. Since transistors are not affected by SafeResynth, it can also be applied to post-silicon debugging, where only metal fixes are possible. 1

Highly-optimized placements may lead to irreparable routing congestion due to inadequate models of modern interconnect stacks and the impact of partial routing obstacles. Additional challenges in routability-driven placement include scalability to large netlists and limiting the complexity of software integration. Addressing these challenges, we develop lookahead routing to give the placer advance, firsthand knowledge of trouble spots, not distorted by crude congestion models. We also extend global placement to (i) spread cells apart in congested areas, and (ii) move cells together in less-congested areas to ensure short, routable interconnects and moderate runtime. While previous work adds isolated steps to global placement, our SIMultaneous PLace-and-Route tool SimPLR integrates a layer-and via-aware global router into a leading-edge, force-directed placer. The complexity of integration is mitigated by careful design of simple yet effective optimizations. On the ISPD 2011 Contest Benchmark Suite, with the official evaluation protocol, SimPLR outperforms every contestant on every benchmark.

In order to prevent the SPA (Simple Power Analysis) attack against modular exponentiation algorithms, a multiply-always implementation is generally used. Witteman et al. introduced in [14] a new cross-correlation power analysis attack against the multiplyalways implementation. We suggest two new algorithms, resistant to this attack and also to other known attacks. The first algorithm is an alternative approach to exponentiation algorithms used in cryptography, which usually receive as an input some representation (e.g. binary) of the exponent. In our approach both the exponent and the result are functions (not necessarily easily invertible) of the exponentiation algorithm input. We show that this approach can have a good performance and that it is also resistant to several known attacks, especially to the cross-correlation power analysis and also to the attack described in [9]. It is particularly relevant for cryptographic schemes in which the private exponent can be chosen arbitrarily. Another exponentiation algorithm that we present here may be preferable for use with RSA in certain settings. It is resistant to the cross-correlation power analysis attack, C safe error attack, and other attacks; although it involves squaring operations.

In order to prevent the SPA (Simple Power Analysis) attack against modular exponentiation algorithms, a multiply-always implementation is generally used. Witteman et al. introduced in [14] a new cross-correlation power analysis attack against the multiplyalways implementation. We suggest two new algorithms, resistant to this attack and also to other known attacks. The first algorithm is an alternative approach to exponentiation algorithms used in cryptography, which usually receive as an input some representation (e.g. binary) of the exponent. In our approach both the exponent and the result are functions (not necessarily easily invertible) of the exponentiation algorithm input. We show that this approach can have a good performance and that it is also resistant to several known attacks, especially to the cross-correlation power analysis and also to the attack described in [9]. It is particularly relevant for cryptographic schemes in which the private exponent can be chosen arbitrar...

Field-Programmable Gate Arrays (FPGAs) are widely used to implement logic without going through an expensive fabrication process. Current-generation FPGAs still suffer from area and power overheads, making them unsuitable for mainstream adoption for large volume systems. FPGA companies constantly design new architectures to provide higher density, lower power consumption, and faster implementation.

To optimize performance and power of a processor's cache, a multiple-divided module (MDM) cache architecture is proposed to save power at memory peripherals as well as the bit array. For a MxB-divided MDM cache, latency is equivalent to that of the smallest module and power consumption is only 1/MxB of the regular, non-divided cache. Based on the architecture and given transistor budgets for onchip processor caches, this paper extends investigation to analyze energy effects from cache parameters in a multi-level cache design. The analysis is based on execution of SPECint92 benchmark programs with miss ratios of a RISC processor.

In this paper, we employ gridded model for channel routing and place the terminals which are horizontally aligned. We have developed a two-layer channel router that can eliminate the constraints due to overlap. The proposed approach is suitable for cell/IP-based channel-less circuit with a few channels. Our developed tool can route the nets in nearly linear time achieving to the advantage of time to market, and lead to the area overhead of 6.34% increase in average. The area overhead results from the space insertion, and we also have shown that the proposed algorithm can achieve 100% routing on most ISCAS'85 benchmarks. In addition, the number of channel tracks can be minimized by our algorithm. We proposed the star-routing algorithm for three layers channel routing using Manhattan-Diagonal Model to solve the channel routing problem. We drew up the smaller grid-model, and in order to avoid violating the DRC, so the algorithm has a restriction for the third metal-layer in routing...

This paper proposes ‘CIRPART’ – architecture for implementing Hybrid Genetic Algorithm (GA) used for circuit Multiway Partitioning in VLSI physical design automation. CIRPART applies Hybrid Genetic Algorithm to considerably reduce the number of generations required. CIRPART provides flexibility and also achieves speedups over software based GA. CIRPART achieves more than 100x improvement in processing speed as compared to the software implementation.

VLSI physical design algorithms are generally nonpolynomial algorithms with very long runtime. In this paper, we parallelize the Pathfinder global routing algorithm-a widely used FPGA routing algorithm-for running on multi-core systems to improve runtime of routing process. Our experimental results show that the runtime of proposed multi-threaded global routing reduces by 47.8% and 70.9% (on average) with 2 and 4 concurrent threads, respectively on a quad-core processor without any quality degradation.

this paper deals with the practical aspects of the mirror equivalence concept of convolutional codes and turbo-codes (TCs), already defined in a companion paper entitled first part. According to this new concept, the codes for which the code words are identical through transposition (reversal) are considered as equivalent (from the point of view of BER performance). In this paper we built the mirror equivalent TCs for two of the TCs used in the communication standards and we verify the mirror equivalence by simulations. The simulations performed prove that the pairs formed by the TCs from standards and their mirror equivalents have similar performance. The identification of some pairs of equivalent TCs simplifies the design of turbo-coding systems. There are large classes of sub-systems used in the design of a TC such as the component convolutional codes or the interleavers from where the best elements must be chosen. This is an exhaustive search. The idea of design based on exhaust...

This chapter presents the design and development of a hardware based architecture of Evolutionary Algorithm for solving both the unimodal and multimodal fixed point real parameter optimization problems. Here a modular architecture has been proposed to provide a tradeoff between real time performance and flexibility and to work as a resource efficient reconfigurable device. The evolutionary algorithm used here is Genetic Algorithm. Prototype implementation of the algorithm has been performed on a system-on-chip field programmable gate array. The notable feature of the architecture is the capability of optimizing a wide class of functions with minimum or no change in the synthesized hardware. The architecture has been tested with ten benchmark problems and it has been observed that for different optimization problems the synthesized target requires maximum of 5% logic slice utilization, 2% of the available block RAMs and 2% of the DSP48 utilization in Xilinx Virtex IV (ML401, XC4VLX25) board.