Worst-Case Execution Time Analysis

where energy imposes a major constraint. We focus on frame-based real-time systems that execute variable workloads with the goal of minimizing expected energy consumption in the system while still meeting the deadlines. In our separate publication, we proposed a new DVS scheme that incorporates the dynamic behavior of the tasks into the speed schedule and aims to minimize the expected energy consumption in the system. The new DVS scheme was derived based on the assumption of unrestricted continuous frequency. However, it remains unknown how the new DVS scheme performs in practical situations. In this paper, we first give a simple example through which we demonstrate the new DVS scheme and compare it with the existing DVS schemes. Then we present evaluation results to show that the new DVS scheme achieves significant energy savings over the existing schemes.

We present an on-line investment algorithm which a c hieves almost the same wealth as the best constant-rebalanced portfolio determined in hindsight from the actual market outcomes. The algorithm employs a multiplicative update rule derived using a framework introduced by Kivinen and Warmuth. Our algorithm is very simple to implement and requires only constant storage and computing time per stock i n e a c h trading period. We tested the performance of our algorithm on real stock data from the New York Stock Exchange accumulated during a 22-year period. On this data, our algorithm clearly outperforms the best single stock a s w ell as Cover's universal portfolio selection algorithm. We also present results for the situation in which the investor has access to additional side information.

Distributions for returns are used to compute the capital charge for portfolios in investment banks. The mainstream definition of returns is based on closing prices and neglects the important effects of intraday trading activity on the losses . In this paper we introduce "minimal returns", a definition of returns that accounts for intraday trading and gives a worst-case approach on losses. We suggest an appropriate distribution for minimal returns that can be used to compute Value at Risk and coherent risk measures, as suggested by .

IP address lookup at the router is a complex problem. This has been primarily due to the increasing table sizes, growth in traffic rate and high link capacities. In this work we have proposed an algorithm for fast routing lookup with reduced memory utilization and access time. This approach shows significant performance improvement in the average case and optimizes the overall time taken for packet routing. Since storage requirement, processing time and number of lookups performed are reduced, power consumption by the router is also reduced. Our simulation result indicates that the proposed technique works approximately 4.11 times better than the standard LC Trie approach in the average case.

This paper presents new algorithms for the maximum flow problem, the Hitchcock t r a n s p o r t a t i o n problem, and the general minimum-cost flow problem. Upper bounds on the numbers of steps in these algorithms are derived, and are shown to compale favorably with upper bounds on the numbers of steps required by earlier algorithms. First, the paper states the maximum flow problem, gives the Ford-Fulkerson labeling method for its solution, and points out t h a t an improper choice of flow augmenting paths can lead to severe computational difficulties. Then rules of choice t h a t avoid these difficulties are given. We show that, if each flow augmentation is made along an augmenting p a t h having a minimum number of arcs, then a maximum flow in an n-node network will be obtained after no more than ~(n a -n) augmentations; and then we show t h a t if each flow change is chosen to produce a maximum increase in the flow value then, provided the capacities are integral, a maximum flow will be determined within at most 1 + logM/(M--1) if(t, S) augmentations, wheref*(t, s) is the value of the maximum flow and M is the maximum number of arcs across a cut. Next a new algorithm is given for the minimum-cost flow problem, in which all shortest-path computations are performed on networks with all weights nonnegative. In particular, this algorithm solves the n X n assigmnent problem in O(n 3) steps. Following t h a t we explore a "scaling" technique for solving a minimum-cost flow problem by treating a sequence of derived problems with "scaled down" capacities. It is shown that, using this technique, the solution of a Iiitchcock transportation problem with m sources and n sinks, m ~ n, and maximum flow B, requires at most (n + 2) log2 (B/n) flow augmentations. Similar results are also given for the general minimum-cost flow problem. An abstract stating the main results of the present paper was presented at the Calgary International Conference on Combinatorial Structures and Their Applications, J u n e 1969. In a paper by l)inic (1970) a result closely related to the main result of Section 1.2 is obtained. Dinic shows that, in a network with n nodes and p arcs, a maximum flow can be computed in 0 (n2p) primitive operations by an algorithm which augments along shortest augmenting paths.

The increasing gap between the speed of the processor and the memory makes the role played by the memory hierarchy essential in the system performance. There are several methods for studying this behavior. Trace-driven simulation has been the most widely used by now. Nevertheless, analytical modeling requires shorter computing times and provides more information. In the last years a series of fast and reliable strategies for the modeling of set-associative caches with LRU replacement policy has been presented. However, none of them has considered the modeling of codes with data-dependent conditionals. In this article we present the extension of one of them in this sense.

Estimating the worst-case execution time (WCET) of parallel applications running on many-core architectures is a significant challenge. Some approaches have been proposed, but they assume the mapping of parallel applications on cores already done. Unfortunately, on architectures with caches, task mapping requires a priori known WCETs for tasks, which in turn requires knowing task mapping (i.e., co-located tasks, co-running tasks) to have tight WCET bounds. Therefore, scheduling parallel applications and estimating their WCET introduce a chicken and egg situation. In this paper, we address this issue by developing an optimal integer linear programming formulation for solving the scheduling problem, whose objective is to minimize the WCET of a parallel application. Our proposed static partitioned non-preemptive mapping strategy addresses the effect of local caches to tighten the estimated WCET of the parallel application. We report preliminary results obtained on synthetic parallel ap...

We propose a novel formal method to compute an upper estimation of the WCET that contains the loss of precision and also can be easily parametrized by the hardware architecture. Assuming that there exists an executable timed model of the hardware, we first use symbolic execution [5] to precisely infer the execution time for a given instruction flow. We secondly identify execution states that can be merged with no loss of precision. Depending on the loss of precision we are ready to accept, we finally merge execution paths that have similar execution times.

Abstract--In this paper we present a model able to serve in validating either functional or non-functional properties of the hard real time systems. We firstly introduce the timed SystemC waiting state automata (TWSA) that will serve in the modeling of the hardware. TWSA ...

Abstract-In present day sub-micron technology, reduction of circuit complexity of on-chip VLSI interconnects is an important issue for the analysis and verification of integrated circuits. In this paper, we present an exact method to compute the analytic time-domain response for a RC circuit including coupling capacitors for ramp input excitation. Accuracy and efficiency of the method is shown for various examples. Key words: RC Interconnect; VLSI; Reduction Technique; Execution Time; Circuit Complexity; Ramp Input

Multicore processors (CMPs) represent a good solution to provide the performance required by current and future hard real-time systems. However, it is difficult to compute a tight WCET estimation for CMPs due to interferences that tasks suffer when accessing shared hardware resources. We propose an analyzable JEDEC-compliant DDRx SDRAM memory controller (AMC) for hard real-time CMPs, that reduces the impact of memory interferences caused by other tasks on WCET estimation, providing a predictable memory access time and allowing the computation of tight WCET estimations.

An accurate and safe estimation of a task's worst case execution time (WCET) is crucial for reasoning about the timing properties of real-time systems. In RISC processors, the execution time of a program construct (e.g., a statement) is a ected by various factors such as cache hits/misses and pipeline hazards, and these factors impose serious problems in analyzing the WCETs of tasks. To analyze the timing e ects of RISC's pipelined execution and cache memory, we propose extensions to the original timing schema where the timing information associated with each program construct is a simple time-bound. In our approach, associated with each program construct is what we call a WCTA (Worst Case Timing Abstraction), which contains detailed timing information of every execution path that might be the worst case execution path of the program construct. This extension leads to a revised timing schema that is similar to the original timing schema except that concatenation and pruning operations on WCTAs are newly de ned to replace the add and max operations on time-bounds in the original timing schema. Our revised timing schema accurately accounts for the timing e ects of pipelined execution and cache memory not only within but also across program constructs. This paper also reports on preliminary results of WCET analysis for a RISC processor. Our results show that tight WCET bounds (within a maximum of about 30% overestimation) can be obtained by using the revised timing schema approach.

One of the key challenges in real-time systems is the analysis of the memory hierarchy. Many Worst-Case Execution Time (WCET) analysis methods supporting an instruction cache are based on iterative or convergence algorithms, which are rather slow. Our goal in this paper is to reduce the WCET analysis time on systems with a simple lockable instruction cache, focusing on the Lock-MS method. First, we propose an algorithm to obtain a structure-based representation of the Control Flow Graph (CFG). It organizes the whole WCET problem as nested subproblems, which takes advantage of common branch-and-bound algorithms of Integer Linear Programming (ILP) solvers. Second, we add support for multiple locking points per task, each one with specific cache contents, instead of a given locked content for the whole task execution. Locking points are set heuristically before outer loops. Such simple heuristics adds no complexity, and reduces the WCET by taking profit of the temporal reuse found in loops. Since loops can be processed as isolated regions, the optimal contents to lock into cache for each region can be obtained, and the WCET analysis time is further reduced. With these two improvements, our WCET analysis is around 10 times faster than other approaches. Also, our results show that the WCET is reduced, and the hit ratio achieved for the lockable instruction cache is similar to that of a real execution with an LRU instruction cache. Finally, we analyze the WCET sensitivity to compiler optimization, showing for each benchmark the right choices and pointing out that O0 is always the worst option.

In multitasking real-time systems it is required to compute the WCET of each task and also the effects of interferences between tasks in the worst case. This is very complex with variable latency hardware, such as instruction cache memories, or, to a lesser extent, the line buffers usually found in the fetch path of commercial processors. Some methods disable cache replacement so that it is easier to model the cache behavior. The difficulty in these cache-locking methods lies in obtaining a good selection of the memory lines to be locked into cache. In this paper, we propose an ILP-based method to select the best lines to be loaded and locked into the instruction cache at each context switch (dynamic locking), taking into account both intra-task and inter-task interferences, and we compare it with static locking. Our results show that, without cache, the spatial locality captured by a line buffer doubles the performance of the processor. When adding a lockable instruction cache, dynamic locking systems are schedulable with a cache size between 12.5% and 50% of the cache size required by static locking. Additionally, the computation time of our analysis method is not dependent on the number of possible paths in the task. This allows us to analyze large codes in a relatively short time (100 KB with 10 65 paths in less than 3 min).

This study introduces an analysis to the performance of the Enhanced Associativity Based Routing protocol (EABR ) based on two factors; Operation complexity (OC) and Communication Complexity (CC). OC can be defined as the number of steps required in performing a protocol operation, while CC can be defined as the number of messages exchanged in performing a protocol operation . The values represent the worst-case analysis. The EABR has been analyzed based on CC and OC and the results have been compared with another routing technique called ABR. The results have shown that EABR can perform better than ABR in many circumstances during the route reconstruction.

In this paper, we consider the online uniform machine scheduling problem on m processors when speed s i = 1 for i = k+1, ..., m and s i = s, s > 1, for i = 1, ..., k. The objective is to minimize makespan. We propose a parametric scheme with the worst-case performance 2.618 when 1 < s ≤ 2, and with the asymptotic worst-case performance 1 2 (1+s+ √ 5-2s + s 2) for all s > 1 when the ratio m/k tends to infinity.

Most existing research on Mixed-Criticality (MC) scheduling (see [1] for a review) has focused on dealing with different WCET estimations of a single piece of code. This is typically a consequence of different tools for determining worst case execution time (WCET) bounds being more or less conservative than each other. This narrative is now being repeated with respect to processor speeds. Modern powerful and energy-efficient processors are yielding innovations that result in varying speed during run-time. For example, [2] describes a mechanism such that late signals can be recovered by delaying the next clock tick, so that logical faults do not propagate to higher (i.e., the software) levels. In a Globally Asynchronous Locally Synchronous (GALS) circuit, local clocks can be affected by signals propagating between different synchronous modules in an asynchronous manner. Research on such varying-speed platform may lead to better understanding of a wider range of problems. For example,...

An integrated guidance and control system for tracking a reference flight path trajectory of a reusable launch vehicle in the presence of model uncertainties, external disturbances, and measurement noises is proposed. To achieve this goal, a properly-trained feedforward neural network to estimate uncertainties in conjunction with a disturbance observer, which estimates external disturbances and the estimation error made by the neural network, is implemented in both the guidance and control loops. In addition, a state observer is designed whose state estimation error is included (along with the tracking error) in the learning algorithm of the neural network and the disturbance observer; such learning is called composite learning. The combined neural network and disturbance observer (employed in both the guidance and control loops) can consistently compensate for complex uncertain terms in the dynamic model of a reusable launch vehicle. More specifically, the introduced design results in an asymptotic tracking of the reference command, thereby providing a resilient flight control system. Extensive simulations are performed to show the effectiveness and robustness of the proposed integrated guidance and control system for trajectory tracking in the presence of uncertainties, aerodynamic disturbances, and measurement noises.

Four authors wish to write a book, which will consist of fifteen chapters. Each chapter is to be written by a single author. The chapters differ in length, and the authors differ in expertise. The speed at which an author will be able to complete a chapter depends on his, or her, familiarity with its subject matter. The completion date of the manuscript is to be minimized. Who should do what? Irrespective of the practical relevance of this model, it is one of the central problems in scheduling theory. In its general form, the authors are unrelated parallel machines, the chapters are jobs, and the problem is R||C max . The reader should recall the definitions of unrelated, uniform, and identical parallel machines (see Section 1.2). We have seen that, for these machine environments, there is a drastic difference in complexity between minimizing maximum and total completion time: R|| ∑Cj is solvable in polynomial time (see Section 8.1), but P2||C max is already NP-hard (see Section 2.4). As long as the number of machines is a constant, dynamic programming can be applied to solve Rm||C max in pseudopolynomial time (see Section 8.3); however, when m is an input, even P||C max is NP-hard in the strong sense (see Section 2.4). This chapter, then, is about hard problems. The design of efficient approximation algorithms and of enumerative optimization methods is called for. We will emphasize the performance analysis of approximation algorithms. The empirical analysis of approximation and optimization procedures will not be discussed in detail. We have

The maximum flow algorithm is distinguished by the long line of successive contributions researchers have made in obtaining algorithms with incrementally better worst-case complexity. Some, but not all, of these theoretical improvements have produced improvements in practice. The purpose of this paper is to test some of the major algorithmic ideas developed in the recent years and to assess their utility on the empirical front. However, our study differs from previous studies in several ways. Whereas previous studies focus primarily on CPU time analysis, our analysis goes further and provides detailed insight into algorithmic behavior. It not only observes how algorithms behave but also tries to explain why algorithms behave that way. We have limited our study to the best previous maximum flow algorithms and some of the recent algorithms that are likely to be efficient in practice. Our study encompasses ten maximum flow algorithms and five classes of networks. The augmenting path algorithms tested by us include Dinic's algorithm, the shortest augmenting path algorithm, and the capacity scaling algorithm. The preflow-push algorithms tested by us include Karzanov's algorithm, three implementations of Goldberg-Tarjan algorithm, and three versions of Ahuja-Orlin-Tarjan excess-scaling algorithms. Among many findings, our study concludes that the preflow-push algorithms are substantially faster than other classes of algorithms, and the highest-label preflow-push algorithm is the fastest maximum flow algorithm for which the growth rate in the computational time is O(n 1 5) on four out of five of our problem classes. Further, in contrast to the results of the worst-case analysis of maximum flow algorithms, our study finds that the time to perform relabel operations (or constructing the layered networks) takes at least as much computation time as that taken by augmentations and/or pushes.

Fixed-priority scheduling with deferred preemption (FPDS) has been proposed in the literature as a viable alternative to fixed-priority pre-emptive scheduling (FPPS), that obviates the need for non-trivial resource access protocols and reduces the cost of arbitrary preemptions. This paper shows that existing worst-case response time analysis of hard real-time tasks under FPDS, arbitrary phasing and relative deadlines at most equal to periods is pessimistic and/or optimistic. The same problem also arises for fixedpriority non-pre-emptive scheduling (FPNS), being a special case of FPDS. This paper provides revised analysis, resolving the problems with the existing approaches. The analysis is based on known concepts of critical instant and busy period for FPPS. To accommodate for our scheduling model for FPDS, we need to slightly modify existing definitions of these concepts. The analysis assumes a continuous scheduling model, which is based on a partitioning of the timeline in a set of non-empty, right semi-open intervals. It is shown that the critical instant, longest busy period, and worst-case response time for a task are suprema rather than maxima for all tasks, except for the lowest priority task, i.e. that instant, period, and response time cannot be assumed. Moreover, it is shown that the analysis is not uniform for all tasks, i.e. the analysis for the lowest priority task differs from the analysis of the other tasks. To build on earlier work, the worst-case response time analysis for FPDS is expressed in terms of known worst-case analysis results for FPPS. The paper includes pessimistic variants of the analysis, which are uniform for all tasks.

Let S n be the set of all permutations of {1, 2, . . . , n} represented in cycle notation. Define a n,m to be the number of π ∈ S n such that the length of the initial longest increasing sequence (ILIS) in π is at most m. For fixed m, we find the exponential generating function for the sequence a n,m , and give an asymptotic formula for a n,m when n → ∞. Moreover, we show that the expected value of the total ILIS in all cycles of π over all permutations of S n is asymptotic to e n j=1 1 j .

Bank switching in embedded processors having partitioned memory architecture results in code size as well as run time overhead. An algorithm and its application to assist the compiler in eliminating the redundant bank switching codes introduced and deciding the optimum data allocation to banked memory is presented in this work. A relation matrix formed for the memory bank state transition corresponding to each bank selection instruction is used for the detection of redundant codes. Data allocation to memory is done by ...

The compilation of Esterel into software has mainly targeted uniprocessor execution. The inherent parallelism of the original description would typically have to be compiled away in order for it to be executed sequentially on a processor. This paper proposes a new compilation scheme that would be able to compile Esterel for distributed execution. This method enables the parallelism of the original description to be realised through actual concurrent execution on multiple processors, or through sequentialized concurrency within a single processor. Both these forms of concurrency can be mixed together for a given implementation. Experimental results indicate significant speed-ups in the performance of concurrently executed distributed programs compared to software implementations on a uniprocessor. When the prototype compiler is used to compile for just a single processor, results show that its performance is comparable to other simulation-based compilers, and significantly faster compared to gate-based compilers, especially for large programs.

This paper introduces a new analytical framework for analyzing and designing caches. It consists of four major parts: TSpec notation, into which reference traces can be transformed; equivalence classes, which abstract away chance effects of address bindings and specific inputs; the functional filter model, which operates on TSpec traces and provides a formal description of cache operation; and new metrics, which evaluate cache performance. This paper gives an overview of TSpec notation and equivalence classes, and then illustrates how the functional filter model can be used to derive better understanding of cache behavior.

This paper introduces an analytical method for approximating the performability of a firm realtime system modeled by a multi-server queue. The service discipline in the queue is earliestdeadline-first (EDF), which is an optimal scheduling algorithm. Real-time jobs with exponentially distributed relative deadlines arrive according to a Poisson process. All jobs have deadlines until the end of service and are served non-preemptively. An important performance measure to calculate is the loss probability. The performance of the system is approximated by a Markovian model in the long run. A key parameter, namely, the loss rate when there are n jobs in the system is used in the model, which is estimated by partitioning the system into two subsystems. The resulting model can then be solved analytically using standard Markovian solution techniques. The number of servers in the system may change due to failure or repair. The performability of the system is evaluated in the presence of such structural changes. The latter measure is approximated by a Markov reward model, considering the loss probability as the reward rate. Comparing numerical and simulation results, we find that the existing errors are relatively small.

The Stacker-Crane Problem (SCP) is a sequencing problem, arising in scheduling and transportation, that consists of finding the minimum cost cycle on a mixed graph with oriented arcs and unoriented edges: feasible solutions must traverse all the arcs. Approximation algorithms are known to provide a fixed worst-case bound if the triangle inequality holds. We consider the worst-case performance of approximation algorithms for the SCP when the triangle inequality can be violated (General SCP) and for a similar problem formulated on a complete digraph (Asymmetric SCP).

Consider a homogeneous isotropic elastic-perfectly plastic body modeled by a bounded open subset of R 3 having a Lipschitz boundary = ∂. The body is assumed to be supported on an open subset 0 of its boundary and t denotes an external surface traction acting on the complementary part, t , of the boundary. Body forces may be included in the analysis but for the sake of simplicity we omit them here. We prove (see [1]) that there exists a maximal positive number C, to which we refer as the load capacity ratio, such that the body will not collapse plastically under any external traction field t bounded by Y 0 C, where Y 0 is the yield stress. Thus, while the limit analysis factor of the theory of plasticity pertains to a specific distribution of external loading, the load capacity ratio is independent of the distribution of the external loading and implies that no collapse will occur for any field t on ∂ as long as ess sup x∈∂ |t (y)| < Y 0 C. Collapse will occur for some t for which the essential supremum of its magnitude over t is greater than Y 0 C. The analysis also allows one to consider subspaces of external loadings, e.g., the collection of loadings acting on a particular subset of the boundary. The load capacity ratio depends only on the geometry of the body and we prove (see [1]) that it is given by

Several groups are developing different versions of a new class of leadless, permanently implanted electronic devices with a size and form factor that allows them to be injected into muscles (BIONs TM). Their circuitry is protected from body fluids by thin-walled hermetic capsules made from rigid and brittle materials (glass or ceramic) that include feedthroughs to their electrodes. These packages experience repetitive stresses from the very contractions that they excite. We here provide a worst-case analysis of such stresses and methods for testing and validation of devices intended for such usage, along with the failure analysis and remediation strategy for a design that experienced unanticipated failures in vivo.

There is a noticeable interest in merging standard database technology and real-time technology recently, resulted in combined systems known as Real-Time Database Systems. They are similar to the conventional databases, but they must ensure some degree of reliability regarding the real-time response requirements. It is very difficult to achieve guaranteed real-time database services in terms of both deadline miss ratio and data freshness because various components can compete for system resources. Transactions travel in a RTDB system through various components until their termination. Our objective is to design an experimental real-time database system which would be suitable enough to study the most important real-time database issues, including CPU scheduling, concurrency control and conflict resolution. Because of the strong interactions among the processed components, proposed system can help us to understand their effect on system performance and to identify the most important factors.

We present new algorithms for permutation group manipulation. Our methods result in an improvement of nearly an order of magnitude in the worst-case analysis for the fundamental problems of finding strong generating sets and testing membership. The normal structure of the group is brought into play even for such elementary issues. An essential element is the recognition of large alternating composition factors of the given group and subsequent extension of the permutation domain to display the natural action of these alternating groups. Further new features include a novel fast handling of alternating groups and the sifting of defining relations in order to link these and other analyzed factors with the rest of the group. The analysis of the algorithm depends on the classification of finite simple groups. In a sequel to this paper, using an enhancement of the present method, we shall achieve a further order of magnitude improvement.

It is essential for social robots to be able to locate and direct attention towards communicating persons, however the operating environments can be challenging. When using sound source localization (SSL) acoustic noise sources can distract the robot, which interrupts the desired interaction with people. Since the noise sources can be of many different kinds, it is important for the robot to adapt to any environment. In this paper we present a simple strategy for a robot to adapt to the environment using feedback from a face detection routine, thus eventually only directing attention towards humans. Four experiments with different noise types and different strategies for using feedback from face detection show the effectiveness of the proposed strategy.

This paper deals with day-ahead static security assessment with respect to a postulated set of contingencies while taking into account uncertainties about the next day system conditions. We propose a heuristic approach to check whether, given some assumptions regarding these uncertainties, the worst case with respect to each contingency is still controllable by appropriate combinations of preventive and corrective actions. This approach relies on the solution of successive optimal power flow (OPF) and securityconstrained optimal power flow (SCOPF) problems of a special type. The interest of the approach is shown by illustrative examples on the Nordic32 system.

Common real-time analysis techniques for embedded systems mainly concentrate on a task model where every single activation of a task leads to a single outgoing event that is emitted at the end of the task's computation. An extension has been introduced that allows for multiple events to occur during a single job by respecting the control flow inside a task in order to recalculate the worst-case density for outgoing events. This previous work does however not consider the effect that data dependencies have on the calculation, which leads to pessimistic results caused by infeasible paths inherent in the control flow. In this paper we propose a method involving a flow graph transformation that reduces this pessimism when using the existing analysis and show its integration into a reasonable workflow.

Common real-time analysis techniques for embedded systems mainly concentrate on a task model where every single activation of a task leads to a single outgoing event that is emitted at the end of the task's computation. An extension has been introduced that allows for multiple events to occur during a single job by respecting the control flow inside a task in order to recalculate the worst-case density for outgoing events. This previous work does however not consider the effect that data dependencies have on the calculation, which leads to pessimistic results caused by infeasible paths inherent in the control flow. In this paper we propose a method involving a flow graph transformation that reduces this pessimism when using the existing analysis and show its integration into a reasonable workflow.

Recently, there has been substantial progress in the formal understanding of how caching resources should be allocated when multiple caches each deploy the common LRU policy. Nonetheless, the role played by caching policies beyond LRU in a networked setting where content may be replicated across multiple caches and where channels are unreliable is still poorly understood. In this paper, we investigate this issue by first analyzing the cache miss rate in a system with two caches of unit size each, for the LRU, and the LFU caching policies, and their combination. Our analytical results show that joint use of the two policies outperforms LRU, while LFU outperforms all these policies whenever resource pooling is not optimal. We provide empirical results with larger caches to show that simple alternative policies, such as LFU, provide superior performance compared to LRU even if the space allocation is not fine tuned. We envision that fine tuning the cache space used by such policies may...

Following the successful WCET Tool Challenges in 2006 and 2008, the third event in this series was organized in 2011, again with support from the ARTIST DESIGN Network of Excellence. Following the practice established in the previous Challenges, the WCET Tool Challenge 2011 (WCC'11) defined two kinds of problems to be solved by the Challenge participants with their tools, WCET problems, which ask for bounds on the execution time, and flow-analysis problems, which ask for bounds on the number of times certain parts of the code can be executed. The benchmarks to be used in WCC'11 were debie1, PapaBench, and an industrial-strength application from the automotive domain provided by Daimler. Two default execution platforms were suggested to the participants, the ARM7 as "simple target" and the MPC5553/5554 as a "complex target," but participants were free to use other platforms as well. Ten tools participated in WCC'11: aiT, Astrée, Bound-T, FORTAS, METAMOC, OTAWA, SWEET, TimeWeaver, TuBound and WCA.

In this article, we present OTAWA, a framework for computing the Worst Case Execution Time of a program. From its design, it provides an extensible and open architecture whose objective is the implementation of existing and future static analyses for WCET computation. Inspired by existing generic tools, it is based on an architecture abstraction layers where hooked annotations store specific analyses information. Computing the WCET is viewed as performing a chain of analyses that use and produce annotations until getting the WCET evaluation. Finally, the efficiency of the framework, in term of development productivity, is evaluated by two case studies that show some pitfalls that we are currently fixing but also the success of the approach.

These last years, many researchers have proposed solutions to estimate the Worst-Case Execution Time of a critical application when it is run on modern hardware. Several schemes commonly implemented to improve performance have been considered so far in the context of static WCET analysis: pipelines, instruction caches, dynamic branch predictors, execution cores supporting out-of-order execution, etc. Comparatively, components that are external to the processor have received lesser attention. In particular, the latency of memory accesses is generally considered as a fixed value. Now, modern DRAM devices support the open page policy that reduces the memory latency when successive memory accesses address the same memory row. This scheme, also known as row buffer, induces variable memory latencies, depending on whether the access hits or misses in the row buffer. In this paper, we propose an algorithm to take the open page policy into account when estimating WCETs for a processor with an instruction cache. Experimental results show that WCET estimates are refined thanks to the consideration of tighter memory latencies instead of pessimistic values.

Following the successful WCET Tool Challenges in 2006 and 2008, the third event in this series was organized in 2011, again with support from the ARTIST DESIGN Network of Excellence. Following the practice established in the previous Challenges, the WCET Tool Challenge 2011 (WCC&#x27;11) dened two kinds of problems to be solved by the Challenge participants with their tools, WCET problems, which ask for bounds on the execution time, and ow-analysis problems, which ask for bounds on the number of times certain parts of ...

In real-time task scheduling on multiprocessor systems, partitioning approach has received the attention of many researchers because of its higher least upper bound utilization of safe systems. Semi-partitioning allows some tasks to be split into subtasks and each subtask to be assigned to a different processor. Though task splitting improves the performance of systems, by counting each subtask as a separate task, it increases the effective number of tasks to be scheduled, which in turn, raises the execution overhead. This research is on semi-partitioning of tasks and assigning each partition to a separate processor to be scheduled by the well-known scheduler Rate-Monotonic (RM). Using our algorithm, we do not need to define release time for subtasks of a task to assure their nonconcurrent execution and the number of effective tasks, in turn, is reduced. It is theoretically proven that with the proposed semi-partitioning and RM scheduling algorithm, all processors may safely run their tasks according to their deadlines. Further, experimental results on 3000 randomly generated task-sets indicates that not only is utilization factor boosted, but the number of broken tasks also is decreased.

To assure the consistency in a database, transactions have been used as a technique for a long time. Commonly transactions impart consistency at the overhead of appropriateness (abort or retry) and source (duplicate shared data and locking), Considerable attempts have been made to confine these two qualities of transactions while fulfilling application constraints. Consistency or operational trade-off develops severe concern for any retrieval of data over a network is not only costly, but comparatively slow when compared to co-located client/database systems, in situations where consumers are geologically far from a database. Additionally, improved transactions overhead may also boost power overhead for consumers hooked on battery power. Nevertheless, for all these shortcomings, transactions do provide the data consistency which is a basic requirement for many applications. In this paper we study the solution associated to prompt transactional systems for isolated clients and centra...

The service provision problem described in this paper comes from an application of distributed processing in telecommunications networks. The objective is to max­ imize a service provider&#39;s profit from offering computational based services to cus­ tomers. The service provider has limited capacity of some resources and therefore must choose from a set of software applications those he would like to offer. This can be done in a dynamic manner taking into consideration that demand for the differ­ ent services is uncertain. This problem is examined in the framework of stochastic integer programming. Approximations and complexity are examined for the case when demand is described by a discrete probability distribution and one resource limits the number of software applications that may be installed. For the determin­ istic counterpart a fully polynomial approximation scheme is known [2]. We show that introduction of stochasticity makes the problem strongly NP-hard, implying that the ...

Failure of a safety-critical application on an embedded processor can lead to severe damage or even loss of life. Here we are concerned with two kinds of failure: stack overflow, which usually leads to run-time errors that are difficult to diagnose, and failure to meet deadlines, which is catastrophic for systems with hard real-time characteristics. Classical software validation methods like simulation and testing with debugging require a lot of effort, are expensive, and do not really help in proving the absence of such errors. AbsInt's tools StackAnalyzer and aiT (timing analyzer) provide a solution to these problems. They use abstract interpretation as a formal method that leads to statements valid for all program runs. Both tools have been used successfully at Hispano-Suiza to analyze applications running on a Motorola PowerPC MPC555. They turned out to be well-suited for analyzing large safety-critical applications developed at Hispano-Suiza. They can be used either during the development phase providing information about stack usage and runtime behavior well in advance of any run of the analyzed application, or during the validation phase for acceptance tests prior to the certification review.

Synthesizing code from model-based software specifications using automatic code gener- ators such as the SCADE Suite allows design verifi- cation at early project stages and helps to avoid cod- ing errors, thus reducing the need for low-level test- ing. Non-functional properties of the implementa- tion such as execution time and memory consump- tion require specific analysis. Static program anal- ysis tools like AbsInt&#x27;s StackAnalyzer and timing analyzer aiT complete ideally the model-based de- sign process with the verification of these proper- ties. These tools can also give SCADE users a di- rect feedback on the effects of their design decisions on resource usage, allowing them to select more ef- ficient designs and implementation methods. The SCADE tool, StackAnalyzer and aiT can be inte- grated in a way that the analysis results for code generated by the SCADE tool are conveniently ac- cessible from within the SCADE development envi- ronment. We present the tools and their...

The Java programming language has been widely described as secure by design. Nevertheless, a number of serious security vulnerabilities have been discovered in Java, particularly in the component known as the Bytecode Verifier. This paper describes a method for representing Java security constraints using the Alloy modeling language. It further describes a system for performing a security analysis on any block of Java bytecodes by converting the bytes into relation initializers in Alloy. Any counterexamples found by the Alloy analyzer correspond directly to insecure code. Analysis of a real-world malicious applet is given to demonstrate the efficacy of the approach. Introduction. This paper will describe an analysis tool for verifying security constraints within Java bytecodes. This investigation was motivated by the continued appearance of malicious Java code that violates the security constraints imposed by the Java compiler, the Java Bytecode Verifier and the Java runtime. The analysis approach is based on the lightweight modeling language Alloy [AL, DJ]. This paper will describe the security verification approach taken by the Java Virtual Machine (JVM), and briefly enumerate some of the ways that it has been circumvented. A review of the top level goals of this work will then be presented, followed by a hierarchical description of the design of the analysis tool and its implementation. Results will then be presented in detail using a real-world example of malicious code: the BlackBox applet. Finally, a path toward future work on the analysis tool will be described. The analysis tool has, in fact, proven to be a powerful approach to analyzing JVM security constraints. The approach of applying lightweight modeling as a means to check JVM security constraints appears to be a new approach. Background. The Java programming language has been touted as "secure by design" since its inception. However, attacks against Java security have been promulgated from the earliest days of Java. Felten discovered several weaknesses in the Java security model almost immediately, and his work on Java [FE] contains an extensive list of early exploits. The development of Java malware has continued unabated up to the present. The Common Vulnerabilities and Exposures project [CV] lists numerous Java bugs that can lead to privilege escalation, sensitive data exfiltration, denial of service and other malicious outcomes. Of particular note is the BlackBox malicious Java applet [BB, LS]. This applet exploits a number of Java security weaknesses, and was widely deployed, infecting thousands of machines. The BlackBox applet not only breaks out of the supposedly invulnerable sandbox that the Java applet runtime imposes, it also manages to escalate its privilege to the highest possible level (since

We introduce here a new method for extracting worst-cases of algorithms by using rewrite systems over automorphisms groups of inputs. We propose a canonical description of an algorithm, that is also related to the problem it solves. The description identifies an algorithm with a set of a rewrite systems over the automorphisms groups of inputs. All possible execution of the algorithm will then be reduced words of these rewriting system. Our main example is reducing two-dimensional Euclidean lattice bases. We deal with the Gaussian algorithm that finds shortest vectors in a two-dimensional lattice. We introduce four rewrite systems in the group of unimodular matrices, i.e. matrices with integer entries and with determinant equal to ±1 and deduce a new worst-case analysis of the algorithm that generalizes Vallée's result[16] to the case of the usual Gaussian algorithm. An interesting (but not easy) future application will be lattice reduction in higher dimensions, in order to exhibit a tight upper-bound for the number of iterations of LLL-like reduction algorithms in the worst case. Sorting ordered finite sets are here as a nice esay example to illustrate the purpose of our method. We propose several rewrite systems in the group S of permutations and canonically identify a sorting algorithm with a rewrite system over S. This brings us to exhibit worst-cases of several sorting algorithms.

We introduce here a new method for extracting worst-cases of algorithms by using rewrite systems over automorphisms groups of inputs. We propose a canonical description of an algorithm, that is also related to the problem it solves. The description identifies an algorithm with a set of a rewrite systems over the automorphisms groups of inputs. All possible execution of the algorithm will then be reduced words of these rewriting system. Our main example is reducing two-dimensional Euclidean lattice bases. We deal with the Gaussian algorithm that finds shortest vectors in a two-dimensional lattice. We introduce four rewrite systems in the group of unimodular matrices, i.e. matrices with integer entries and with determinant equal to ±1 and deduce a new worst-case analysis of the algorithm that generalizes Vallée's result to the case of the usual Gaussian algorithm. An interesting (but not easy) future application will be lattice reduction in higher dimensions, in order to exhibit a tight upper-bound for the number of iterations of LLL-like reduction algorithms in the worst case. Sorting ordered finite sets are here as a nice esay example to illustrate the purpose of our method. We propose several rewrite systems in the group S of permutations and canonically identify a sorting algorithm with a rewrite system over S. This brings us to exhibit worst-cases of several sorting algorithms.