Thin Film Transistor

Contact effects in organic thin film transistors (OTFTs) remain an important problem to be solved in these devices. Therefore, the correct physio-chemical modeling of the contact regions in OTFTs is necessary. In this work, a standard model for the contact region of OTFTs is proposed. It is a versatile model that describes the current-voltage characteristics of different kinds of contacts. It reproduces the behavior of Schottky barrier or space-charge limited contacts. It is a simple unified model since only a single parameter is necessary in order to distinguish between both kinds of contacts. The model is easily integrated in a generic compact model for the current-voltage characteristics of OTFTs. The resulting compact model, used in combination with an evolutionary parameter extraction procedure, allows to extract the intrinsic parameters and the current-voltage curves at the contact of single short-channel transistors. There is no need to use transistors with multiple channel lengths to accurately characterize the contact region or the active channel of the transistor. The model is tested with published experimental data of OTFTs with Schottky barrier or space-charge limited contacts. Finally, the method has been used as a diagnostic tool to analyze how an ammonia sensor reacts to different concentrations of the ammonia gas. Interestingly, alterations in the contact region have been detected when the gas concentration varies, transforming the space-charge limited contact of a pristine OTFT into a Schottky barrier contact under the exposure of gas.

In this work, the topic of the detrimental contact effects in organic thin-film transistors (OTFTs) is revisited. In this case, contact effects are considered as a tool to enhance the characterization procedures of OTFTs, achieving more accurate values for the fundamental parameters of the transistor threshold voltage, carrier mobility and on-off current ratio. The contact region is also seen as a fundamental part of the device which is sensitive to physical, chemical and fabrication variables. A compact model for OTFTs, which includes the effects of the contacts, and a recent proposal of an associated evolutionary parameter extraction procedure are reviewed. Both the model and the procedure are used to assess the effect of the annealing temperature on a nickel-1,4,8,11,15,18,22,25-octakis(hexyl)phthalocyanine (NiPc6)-based OTFT. A review of the importance of phthalocyanines in organic electronics is also provided. The characterization of the contact region in NiPc6 OTFTs complement...

this document describes howLow Cost HF (13.56 MHz) antennas can be built and tuned so that their characteristics match the requirements of the high performance reader and third party RF modules. This third edition places greater emphasis on antennas for the higher power readers. In general, the distance at which a Tag-it™ transponder inlay (tag) can be read is related to the size of the Reader's antenna system and its associated magnetic field strength, the larger the antenna, the greater the range. Depending on the type and make of the long range RFID reader, more gate pedestals can be configured and integrated to a single reader. For a three pedestal gate, its antenna pedestals are spaced at up to 1.2 meter apart. Optionally, each gate pedestal can be equipped with a flasher light.

this document describes howLow Cost HF (13.56 MHz) antennas can be built and tuned so that their characteristics match the requirements of the high performance reader and third party RF modules. This third edition places greater emphasis on antennas for the higher power readers. In general, the distance at which a Tag-it™ transponder inlay (tag) can be read is related to the size of the Reader's antenna system and its associated magnetic field strength, the larger the antenna, the greater the range. Depending on the type and make of the long range RFID reader, more gate pedestals can be configured and integrated to a single reader. For a three pedestal gate, its antenna pedestals are spaced at up to 1.2 meter apart. Optionally, each gate pedestal can be equipped with a flasher light.

Among amorphous oxide thin film transistors, amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFT) is currently highlightened because of its advantages such as high mobility, transparent characteristic, flexibility and so on. It is required to ensure the stability of the device under various environments has to be verified before high-volume manufacturing. In this paper, the instability of amorphous InGaZnO TFT depending on the SiOx/SiNx stacked gate dielectric material is investigated through bias and light illumination stress test. Here, the TFT’s instability characteristics are examined by the density of total trap states at the channel/gate dielectric interface (Nit).

The inkjet-printing process of precursor solutions containing In nitrate dissolved in 2-methoxyethanol is optimized using ethylene glycol as a cosolvent that allows the stabilization of the droplet formation, leading to a robust, repeatable printing process. The inkjet-printed precursor films are then converted to In 2 O 3 semiconductors at flexible-substrate-compatible low temperatures (150-200 °C) using combined far-ultraviolet (FUV) exposure at ∼160 nm and thermal treatment. The compositional nature of the precursor-to-metal oxide conversion is studied using grazing incidence X-ray diffraction (GIXRD), X-ray reflectivity (XRR), and Fourier transform infrared (FTIR) spectroscopy that indicate that amorphous, high density (up to 5.87 g/cm 3 ), and low impurity In 2 O 3 films can be obtained using the combined annealing technique. Prolonged annealing (180 min) at 150 °C yields enhancement-mode TFTs with saturation mobility of 4.3 cm 2 /(Vs) and ∼1 cm 2 /(Vs) on rigid Si/SiO 2 and flexible plastic PEN substrates, respectively. This paves the way for manufacturing relatively high-performance, printed metal-oxide TFT arrays on cheap, flexible substrate for commercial applications.

Besides displays, sensing is another key application field for oxide TFTs, including X-ray sensors, photosensors, gas sensors, and biosensors. Compared to their organic counterparts, metal-oxide TFTs can reach better performance, such as higher electron saturation mobility (μ sat ) and current density. Oxide TFTs are commonly produced using sequential multistep vacuum and photolithography processes. Solution-process patterning, such as reverse-offset printing, flexographic printing, or inkjet printing is desirable for scalable roll-to-roll and sheet-to-sheet fabrication due to reduced cost through high-throughput processing, reducing the number of processing steps and conservation of active materials, which is highlighted for additive inkjet printing. An exemplary application for this technology is displays with inkjet-printed oxide TFT backplanes coupled with inkjet-printed organic light-emitting diode frontplanes. Gate dielectric material has a critical impact on TFT performance. Polarization of charges within the dielectric material occurs upon applied gate bias, which directly influences the extent of charge depletion or accumulation in the semiconductor channel. As TFTs evolve toward smaller architectures with increasingly thinner gate dielectrics, tunnelingrelated leakage current becomes a limitation with high operation voltages, presenting a need for replacing materials such as SiO 2 (ε = 3.9) with ones having a higher dielectric constant (high-κ). Binary high-κ oxide dielectrics can be prepared by solution processes. Some examples prepared by spin coating or spray pyrolysis include AlO x (ε = 10.4), ZrO x (ε = 22.6), YO x (ε = 25.4), TiO x (ε = 53.4), and LiO x (ε = 6.7) (ε at 1 kHz). Oxide materials with higher dielectric constant than these examples exist, but those typically possess low bandgaps, making those prone to unfavorable leakage currents. Ternary oxides can provide superior performance compared to binary oxides, by incorporating a high bandgap from one component, combined with a high dielectric constant from another component. Also, by adding a dopant with higher Gibbs free energy of oxidation than the host oxide, one can suppress the Additive solution process patterning, such as inkjet printing, is desirable for high-throughput roll-to-roll and sheet fabrication environments of electronics manufacturing because it can help to reduce cost by conserving active materials and circumventing multistep processing. This paper reports inkjet printing of Y x Al 2-x O 3 gate dielectric, In 2 O 3 semiconductor, and a polyethyleneimine-doped In 2 O 3 interfacial charge injection layer to achieve a thin-film transistor (TFT) mobility (μ sat ) of ≈1 cm 2 V -1 s -1 at a low 3 V operating voltage. When the dielectric material is annealed at 350 °C, plasma treatment induces low-frequency capacitance instability, leading to overestimation of mobility. On the contrary, films annealed at 500 °C show stable capacitance from 1 MHz down to 0.1 Hz. This result highlights the importance of low-frequency capacitance characterization of solution-processed dielectrics, especially if plasma treatment is applied before subsequent processing steps. This study progresses metal-oxide TFT fabrication toward fully inkjet-printed thin-film electronics.

The study aimed at enhancement and optimisation of SnS conductivity via annealing for field effect transistor’s semiconductor channel layer application. Interstitials and vacancies in SnS films are known to cause carrier traps which limit charge carriers and hence limit the achievement of the threshold voltage for a field effect transistor operation. Tuning of SnS conductivity for transistor application is of emerging interest for novel device operation. SnS thin film semiconductors of 0.4 thickness were deposited using Aerosol assisted chemical vapour deposition and annealed in open air at annealing temperatures of150, 200, 250, 300 and 350 . Variation of the annealing temperature from 150 through 250 enhances the crystallinity of the annealed thin film samples by increasing the number of crystallites of the annealed films which is also buttress by the decreasing values of FWHM. However a further decrease in crystallite size at higher annealing temperature of 300 to 350 was observe...

SnS semiconductor thin film of 0.20, 0.25, 0.30, 0.35, 0.40 μm were deposited using aerosol assisted chemical vapour deposition (AACV) on glass substrates and were investigated for use in a field effect transistor. Profilometry, X-ray diffraction, Scanning electron microscope and Energy dispersive X-ray spectroscopy were used to characterise the structural and microstructural properties of the SnS semiconductor. The SnS thin film was found to initially consist of a single crystal at thickness of 0.20 to 0.25μm after which it becomes polycrystalline with an orthorhombic crystal structure consisting of Sn and S elements whose composition varied with increase in thickness. The SnS film of 0.4 μm thickness shows a more uniform grain distribution and growth with a crystal size of 60.57 nm and grain size of 130.31 nm signifying an optimum for the as deposited SnS films as the larger grains reduces the number of grain boundaries and charge trap density hence allowing charge carriers to mov...

This study is focused on the investigation of SnS thin film for transistor application. Electron trap which is associated with grain boundary effect affects the electrical conductivity of SnS semiconductor thin film thereby militating the attainment of the threshold voltage required for transistor operation. Grain size and grain boundary is a function of a semiconductor’s thickness. SnS semiconductor thin films of 0.20, 0.25, 0.30, 0.35, 0.40 μm were deposited using aerosol assisted chemical vapour deposition on glass substrates. Profilometry, Scanning electron microscope, Energy dispersive X-ray spectroscopy and hall measurement were used to characterise the composition, microstructure and electrical properties of the SnS thin film.  SnS thin films were found to consist of Sn and S elements whose composition varied with increase in thickness. The film conductivity was found to vary with grain size and grain boundary which is a function of the film thickness. The SnS film of 0.4 μm ...

A small molecule organic semiconductor, D(D ′ -A-D ′ ) 2 comprising benzothiadiazole as an acceptor, 3hexylthiophene, and thiophene as donors, was successfully synthesized. X-ray diffraction and atomic force microscopy were used to investigate the effect of a dual solvent system with varying ratios of chloroform and toluene on film crystallinity and film morphology via inkjet printing. The film prepared with a chloroform to toluene ratio of 1.5 : 1 showed better performance with improved crystallinity and morphology due to having enough time to control the arrangement of molecules. In addition, by optimizing ratios of CHCl 3 to toluene, the inkjet-printed TFT based on 3HTBTT using a CHCl 3 and toluene ratio of 1.5 : 1 was successfully fabricated and exhibited a hole mobility of 0.01 cm 2 V -1 s -1 due to the improved molecular ordering of the 3HTBTT film.

The progress in high technology has led to the wide use of thin film transistor-liquid crystal display (TFT-LCD). The evolution of the manufacturing technology of TFT-LCD keeps increasing the size of TFT-LCD since a larger TFT-LCD allows a larger display application and an improved productivity. However, as the size of TFT-LCD increases, the size of TFT-array substrates and color filter substrates has to increase simultaneously. This leads to a more complicated inventory problem of large-sized substrates. Therefore, this paper considers a color filter replenishment problem in TFT-LCD manufacturing with the consideration of storage space, yield rate, quantity discounts and multiple suppliers. We first formulate the color filter replenishment problem as a fuzzy multiple objective programming, and then a fuzzy multiple objective programming with assigned weights for objectives based on experts' opinions is proposed. An example with four cases is given to illustrate the practicality for empirical investigation. The results demonstrate that both methods are effective tools for inventory management of color filters for multi-periods. In addition, the methods can be applied or modified for managing inventory in general.

Solution processed thin films organic semiconductors with controlled optimum morphology is a key feature required for organic electronics. The thin-film fabrication of organic conjugated polymers (CP) with controlled morphology is, therefore, highly desired since it is very sensitive on processing conditions due to the one-dimensionality of -conjugation. Our group has developed a unique thin film casting procedure to obtain highly

A novel film preparation method utilizing polymer suspension, entitled adsorbing deposition in suspensions (ADS), has been proposed. The poly(3-hexylthiophene) (P3HT) toluene solution forms P3HT nanofibrils dispersed suspension by aging. P3HT nanofibrils are highly crystallized with sharp vibronic absorption spectra. By the ADS method, only P3HT nanofibrils in suspension can be deposited on the substrate surface without any disordered fraction from the dissolved P3HT in suspension. Formed ADS film contains only the nanostructured conjugated polymer. Fabricated polymer thin-film transistor (TFT) utilizing ADS P3HT film shows good TFT performances with low off current, narrow subthreshold swing and large on/off current ratio.

Cyclopentasilane (CPS) has been studied as an liquid precursor for the deposition of thin silicon films for printed electronics and related applications. The processing involves a UV‐induced prepolymerization of CPS followed by liquid deposition and low‐temperature thermolysis. An insight into the oligomer and polymer formation including crosslinking in solution using 29Si NMR spectroscopy and electron spin resonance spectroscopy is reported. Formation of SiH (T‐units) and SiH3 (M‐units) is observed as well as short‐lived paramagnetic species. Additionally, the polymerization is followed by Raman spectroscopy. Reactive molecular dynamics simulations are applied to develop a theoretical model for the CPS‐ring‐opening and crosslinking steps. The experimental and computational data correspond well to each other and allow insight into the mechanism of polymer formation. The processing steps include spin‐coating, thermal drying, and conversion to amorphous silicon, H‐passivation, and fab...

Low temperature polycrystalline silicon thin film transistors (LTPS poly-Si TFTs) are essential for large area electronics and high performance flat panel displays. In recent years, LTPS TFT performance has substantially increased due to the important breakthroughs in the field of polycrystalline silicon crystallization and also due to the optimization of the process steps that differ from those of typical MOSFETs, mainly because of the requirement for low temperature procedures. In this review we present the electrical characteristics of polycrystalline silicon TFTs, crystallized with different variations of the advanced SLS ELA technique, and the determination of process technological parameters that affect the device performance, in order to further optimize the production of such high performance transistors, in terms of poly-Si microstructure, channel dimensions and topology. Also, the effect of these fabrication parameters on device degradation characteristics is studied, with...

Bio and chemical sensing represents one of the most attractive applications of organic electronics and of Organic Thin Film Transistors (OTFTs) in particular. The implementation of miniaturized portable systems for the detection of chemical analytes as well as of biological species, is still a challenge for the sensors' community. In this respect OTFTs appear as a new class of sensors able, in principle, to overcome some of the commercial sensors drawbacks. As far as volatile analytes are concerned, commercially available sensing systems, such as metal oxide based chemi-resistors, offer great; stability but rather poor selectivity. In spite of the improved selectivity offered by organic chemi-resistors the reliability of such devices is not yet satisfactorily proven. Oil the other hand, complex odors recognition, but also explosives or pathogen bacteria detection are currently being addressed by sensor array systems, called "e-noses", that try to mimic the mammalian ol...

Single-Molecular Wire Transistor Based on Carbon-Bridged Oligo-Phenylene Vinylene 1 東京工業大学フロンティア材料研究所, 2 東京大学理学研究科化学専攻, 3 神奈川大学理学部 居藤 悠馬 1, Chun Ouyang 1, 橋本康平 ,辻 勇人 ,中村 栄一 2, 真島 豊 1 1Laboratory for Materials and Structures, Tokyo Institute of Technology, 2Department of Chemistry, School of Science, The University of Tokyo, 3Faculty of Science, Kanagawa University Yuma Ito1, Chun Ouyang1, Kouhei Hashimoto2, Hayato Tsuji3, Eiichi Nakamura2 and Yutaka Majima1 E-mail: ito@nanoele.msl.titech.ac.jp

We studied the effect of insertion of metal-oxide layers into electrodes for OTFTs (organic thin film transistors) to improve their electrical characteristics. The thickness of pentacene was about 50 nm and the metal electrode was made of gold. The metal-oxide thin-film layers inserted between the electrode and the organic pentacene layers were about 2∼8 nm and the electrical properties of the inserted metal-oxide layers were measured by using UPS (ultraviolet photoelectron spectroscopy). From the results for the electrical properties, the mobility and the threshold voltage of the OTFTs with inserted WO3 layers were improved from 8.80 × 10 -3 cm 2 /V•s to 2.48 × 10 -2 cm 2 /V•s and were decreased from -12.3 V to -4.09 V, respectively. The mobility and the threshold voltage of the OTFTs with inserted TiO2 layers were decreased to 7.04 × 10 -3 cm 2 /V•s and -3.38 V, respectively. From the results of the UPS analysis, we found that the inserted WO3 layers decreased and TiO2 layers increased the energy barriers at the interface between the electrode and the organic pentacene layers.

We studied the effect of insertion of metal-oxide layers into electrodes for OTFTs (organic thin film transistors) to improve their electrical characteristics. The thickness of pentacene was about 50 nm and the metal electrode was made of gold. The metal-oxide thin-film layers inserted between the electrode and the organic pentacene layers were about 2∼8 nm and the electrical properties of the inserted metal-oxide layers were measured by using UPS (ultraviolet photoelectron spectroscopy). From the results for the electrical properties, the mobility and the threshold voltage of the OTFTs with inserted WO3 layers were improved from 8.80 × 10 -3 cm 2 /V•s to 2.48 × 10 -2 cm 2 /V•s and were decreased from -12.3 V to -4.09 V, respectively. The mobility and the threshold voltage of the OTFTs with inserted TiO2 layers were decreased to 7.04 × 10 -3 cm 2 /V•s and -3.38 V, respectively. From the results of the UPS analysis, we found that the inserted WO3 layers decreased and TiO2 layers increased the energy barriers at the interface between the electrode and the organic pentacene layers.

The electrical degradation (aging) of copper phthalocyanine (CuPc) organic thin film transistors (OTFTs) was investigated. Thick (1000 ML) and ultrathin (4 ML) channel thicknesses were used in bottom contact OTFTs to correlate the electrical effects of aging with film microstructure. Proper TFT saturation behavior was unattainable in thick devices subject to ambient aging; however ultrathin devices were significantly less susceptible and maintained good saturation and subthreshold behavior. Therefore 1000 monolayer (ML) CuPc OTFTs were characterized in ambient air, clean dry air, clean humidified air, and NOx environments to isolate the ambient components that induce aging. Thick channel devices which had been aged in ambient air to the point of losing all saturation behavior could be restored to proper saturation behavior by exposure to clean humidified air. The data are consistent with aging resulting primarily from adsorption of strong oxidants from ambient air within the grain b...

Microcrystalline silicon (mc-Si) films deposited using a Plasma Enhanced Chemical Vapour Deposition (PECVD) process constitute an important material for manufacturing low-cost, large-area thin-film devices, such as solar cells or thin-film transistors. Although the deposition of electronic-grade mc-Si using the PECVD process is now well established, the high substrate temperature required (∼ 300 • C) does not lend itself to electronic devices with flexible form factors fabricated on low-cost plastic substrates. In this study, we first investigated an intrinsic mc-Si layer deposited at plastic-compatible substrate temperatures (150 • C) by characterising the properties of the film and then evaluated its applicability to p-i-n solar cells though device characterisation. When the performance of the solar cell was correlated with film properties, it was found that, although it compared unfavourably with mc-Si deposited at higher temperatures, it remained a very promising option. Nonetheless, further development is required to increase the overall efficiency of mc-Si flexible solar cells.

We demonstrate a fabrication method for high-performance field-effect transistors (FETs) based on dry-processed random single-walled carbon nanotube networks (CNTNs) deposited at room temperature. This method is an advantageous alternative to solution-processed and direct CVD grown CNTN FETs, which allows using various substrate materials, including heat-intolerant plastic substrates, and enables an efficient, density-controlled, scalable deposition of as-produced single-walled CNTNs on the substrate directly from the aerosol (floating catalyst) synthesis reactor. Two types of thin film transistor (TFT) structures were fabricated to evaluate the FET performance of dry-processed CNTNs: bottom-gate transistors on Si/SiO 2 substrates and top-gate transistors on polymer substrates. Devices exhibited on/off ratios up to 10 5 and field-effect mobilities up to 4 cm 2 V -1 s -1 . The suppression of hysteresis in the bottom-gate device transfer characteristics by means of thermal treatment in vacuum and passivation by an atomic layer deposited Al 2 O 3 film was investigated. A 32 nm thick Al 2 O 3 layer was found to be able to eliminate the hysteresis.

A novel non-lithographic technique for the fabrication of carbon nanotube thin film transistors is presented. The whole transistor fabrication process requires only one mask which is used both to pattern transistor channels based on aerosol synthesized carbon nanotubes and to deposit electrodes by metal evaporation at different angles. An important effect of electrodynamic focusing was utilized for the directed assembly of transistor channels with feature sizes smaller than the mask openings. This dry non-lithographic method opens up new avenues for device fabrication especially for low cost flexible and transparent electronics.

Semiconductor nanowires represent unique materials for exploring phenomena at the nanoscale. Developments in nanowire growth have led to the demonstration of a wide range of nanowire materials with precise control of composition, morphology, and electrical properties, and it is believed that this excellent control together with small channel size could yield device performance exceeding that obtained using top-down techniques. Here, we review advances in chemically synthesized semiconductor nanowires as nanoelectronic devices. We first introduce basic nanowire field-effect transistor structures and review results obtained from both p-and n-channel homogeneous composition nanowires. Second, we describe nanowire heterostructures, show that by using nanowire heterostructures, several limiting factors in homogeneous nanowire devices can be mitigated, and demonstrate that nanowire transistor performance can reach the ballistic limit and exceed state-of-the-art planar devices. Third, we discuss basic methods for organization of nanowires necessary for fabricating arrays of device and circuits. Fourth, we introduce the concept of crossbar nanowire circuits, discuss results for both transistor and nonvolatile switch devices, and describe unique approaches for multiplexing/demultiplexing enabled by synthetically coded nanowire. Fifth, we discuss the unique application of thin-film nanowire transistor arrays on low-cost substrates and illustrate this with results for relatively high-frequency ring oscillators and completely transparent device arrays. Finally, we describe 3-D heterogeneous integration that is uniquely enabled by multifunctional nanowires within a bottom-up approach.

Precise control over the threshold voltage of pentacene-based organic thin film transistors was achieved by inserting a genetically engineered quartz-binding polypeptide at the semiconductor-dielectric interface. A 30 V range was accessed with the same peptide by adjusting the pH of the solution for peptide assembly while leaving other device properties unaffected. Mobility of 0.1-0.2 cm 2 V -1 s -1 and on/off current ratio of Ͼ10 6 could be achieved for all devices regardless of the presence of the neutral peptide or the peptide assembled in acidic or basic conditions. This shift in threshold voltages is explained by the generation of charged species and dipoles due to variation in assembling conditions. Controlling device characteristics such as threshold voltage is essential for integration of transistors into electronic circuits.

Precise control over the threshold voltage of pentacene-based organic thin film transistors was achieved by inserting a genetically engineered quartz-binding polypeptide at the semiconductor-dielectric interface. A 30 V range was accessed with the same peptide by adjusting the pH of the solution for peptide assembly while leaving other device properties unaffected. Mobility of 0.1–0.2 cm2 V−1 s−1 and on/off current ratio of >106 could be achieved for all devices regardless of the presence of the neutral peptide or the peptide assembled in acidic or basic conditions. This shift in threshold voltages is explained by the generation of charged species and dipoles due to variation in assembling conditions. Controlling device characteristics such as threshold voltage is essential for integration of transistors into electronic circuits.

Oxide compounds belonging to Zn-Sn-O (ZTO) system with the rutile (SnO2), wurtzite (Zn), perovskite (ZnSnO3) and inverse spinel (Zn2SnO4) type structure with outstanding electrical and optical properties have become recently extremely attractive, to obtain transparent conducting oxide (TCO) films. It is well known that TCO films are playing an increasingly main role in many applications as transparent electrode of solar cell, the flat panel devices, infra-red (IR) reflectors, organic light emitting diode (OLED) and thin film transistor-liquid crystal display (TFT-LCD).

Organic semiconductor-based thin-film transistors' (TFTs) chargecarrier mobility has been enhanced up to 25 cm 2 /V s through the improvement of fabrication methods and greater understanding of the microstructure chargetransport mechanism. To expand the practical feasibility of organic semiconductor-based TFTs, their electrical properties should be easily accessed from the fully printed devices through a scalable printing method, such as a roll-to-roll (R2R) gravure. In this study, four commercially available organic semiconductors were separately formulated into gravure inks. They were then employed in the R2R gravure system (silver ink for printing gate and drain-source electrodes and BaTiO 3 ink for printing dielectric layers) for printing 20 × 20 TFT-active matrix with the resolution of 10 pixels per inch on poly(ethylene terephthalate) (PET) foils to attain electrical properties of organic semiconductors a practical printing method. Electrical characteristics (mobility, on-off current ratio, threshold voltage, and transconductance) of the R2R gravure-printed 20 × 20 TFT-active matrices fabricated with organic semiconducting ink were analyzed statistically, and the results showed more than 98% device yield and 50 % electrical variations in the R2R gravure TFT-active matrices along the PET web.

This work presents the effect of grain boundaries in nanocrystalline silicon thin-film transistors (nc-Si TFT). In this study, it is assumed that the nanocrystalline silicon film which is used as the channel material in TFT consists of grain boundaries perpendicular as well as parallel to the carrier flow. Analytical model for mobility due to perpendicular GBs (perp) and mobility due to parallel GBs (parallel) are developed separately and then the overall (effective) mobility, FE, is calculated incorporating both type of GBs. Thereafter the overall (effective) mobility µFE and drain current are plotted as a function of gate voltage. The trend observed from the theoretical plot of drain current versus gate voltage is in agreement with the experimentally observed trend.

The bulk of semiconductor technology has been based on silicon till today. But silicon has its own limitations. It is not transparent to visible light and hence it cannot be used in certain applications. ZnO is a material which is transparent to visible light. In this paper, we compare the electrical performance of ZnO Thin film Transistors using different gate insulators. Certain performance indices and material indices were considered as the selection criteria for electrical performance. A methodology known as Ashby's approach was adopted to find out the best gate insulators and based on this methodology various charts were plotted to compare different properties of competing materials. This work concludes that Y2O3 is the best insulator followed by ZrO2 and HfO2.

The effect of the grain size on the effective carrier mobility (μ eff ) and transfer characteristics of a polycrystalline silicon thin-film transistor (poly-Si TFT) have been theoretically investigated by developing an analytical model. The dependence of μ eff is studied as a function of doping concentrations and gate voltage for different values of grain size. It is observed that at low as well as at high doping concentrations, the effective carrier mobility (μ eff ) increases with increase in grain size, whereas the observed dip at the intermediate doping concentration is getting confirmed. The effect of the grain size on transfer characteristics of poly-Si TFT in its linear region is also presented. It is found that at low gate voltages, μ eff and I D increase rapidly with the increase in V G for all values of grain sizes due to the grain boundary barrier lowering effect. At high gate voltage the grain boundary barrier lowering effect becomes insignificant and causes the saturation of μ eff and I D . The model was found to account correctly for the experimentally observed mobility variation and yield a reasonably good agreement.

Carrier transport through transverse and longitudinal grain boundaries (GBs) in polysilicon thin film transistors (poly-Si TFTs) has been studied. The model considers an array of square grains in the channel of poly-Si TFT in which current flows along the longitudinal GBs and through the grains and the transverse GBs. The variation of field-effect mobility (μ FE ) and drain current (I D ) is computed for different values of grain size. This study reveals that at low gate voltage the longitudinal GBs are seen to influence the field-effect mobility and drain current. As gate voltage increases, the effect of transverse GBs is found to account for experimental results. This is attributed to the fact that at low gate voltage, the carriers moving through longitudinal GBs have more opportunities to be trapped at the trapping sites and as gate voltage increases the carriers have sufficient energy to bypass the longitudinal GBs and obstructed by transverse GBs alone. This may be the reason that the calculated effects of longitudinal GBs do not appear in the experimental results at high gate voltage.

The effect of the grain size on the effective carrier mobility (μ eff ) and transfer characteristics of a polycrystalline silicon thin-film transistor (poly-Si TFT) have been theoretically investigated by developing an analytical model. The dependence of μ eff is studied as a function of doping concentrations and gate voltage for different values of grain size. It is observed that at low as well as at high doping concentrations, the effective carrier mobility (μ eff ) increases with increase in grain size, whereas the observed dip at the intermediate doping concentration is getting confirmed. The effect of the grain size on transfer characteristics of poly-Si TFT in its linear region is also presented. It is found that at low gate voltages, μ eff and I D increase rapidly with the increase in V G for all values of grain sizes due to the grain boundary barrier lowering effect. At high gate voltage the grain boundary barrier lowering effect becomes insignificant and causes the saturation of μ eff and I D . The model was found to account correctly for the experimentally observed mobility variation and yield a reasonably good agreement.

The antibody immobilization with low-cost materials and label-free methods are a challenge for the fabrication of biosensor devices. In this work, it was developed a strategy for antibody immobilization on ZnO TFTs over polyethylene terephthalate (PET) as a recyclable plastic substrate. Antibodies were biofunctionalized using a label-free strategy for E. coli detection. The use of a recyclable plastic substrate PET enables the compatibility with flexible electronics that could contribute for a low-cost biosensor useful in rural communities that do not have the necessary infrastructure and trained personnel for pathogenic bacterial detection in food or water.

The metal-semiconductor interface in thin-film transistors (TFTs) is one of the bottlenecks on the development of these devices. Although this interface does not play an active role in the transistor operation, a low-quality interface can be responsible for a low performance operation. In a-Si TFTs, a doped film can be used to improve this interface, however, in other TFT technologies, there is no doped film to be used. In this chapter, some alternatives to improve this interface are analysed. Also, the influence of this interface on the electrical stability of these devices is presented.

En este artículo, se reporta la fabricación de transistores de película delgada con óxido de zinc (ZnO TFTs) sobre sustratos de plástico por spray pyrolysis ultrasónico de alta frecuencia a baja temperatura. La máxima temperatura de fabricación fue de 200°C. Spin-on glass fue usado como dieléctrico de compuerta. El tereftalato de polietileno (PET) es usado como sustrato de plástico. Los ZnO TFTs exhiben una movilidad de electrones de 1.25 cm2/Vs y voltaje de umbral de 10.5V, mientras la relación de corriente on/off fue de 104. Adicionalmente, la densidad de trampas en la capa activa y en la interfaz dieléctrico/semiconductor son calculados. Además, capacitores metal-dieléctrico-metal fueron fabricados sobre plástico y caracterizados para evaluar el dieléctrico de compuerta.

In this work, we study the effect of the deposition RF-power on the structural, optical and electrical properties of hydrogenated nanocrystalline silicon-germanium (nc-SiGe:H) thin films obtained by plasma enhanced chemical vapor deposition (PECVD) at substrate temperature of 200 °C. The objective is to produce films with high crystalline fraction in order to be used as active layers in thin film transistors (TFTs). Bottom-gate (BG) thin film transistors were fabricated with nc-SiGe:H active layers, deposited at different RF-power. Values of ON-OFF current ratio, subthreshold slope and threshold voltage of 105, 0.12 V/dec and 0.9 V, respectively, were obtained on TFTs with the nc-SiGe:H active layer deposited at 25 W.

In this work, high mobility TFTs based on zinc nitride (Zn3N2) sputtered at room temperature using spin-on glass (SOG) as gate dielectric are presented. The inverted coplanar structure is used for the Zn3N2 TFTs. The devices exhibit an on/off-current ratio of 106 and a subthreshold slope of 0.88 V/decade. The extracted field-effect mobility was 15.8 cm2/Vs which is among the highest reported for Zn3N2 TFTs. In addition, n-type MOS capacitors were fabricated and characterized by capacitance – voltage and capacitance – frequency measurements to evaluate the dielectric characteristics of the SOG film.      

In this work, Zinc Nitride (Zn3N2) based flexible thin film transistors (TFTs) are presented. The zinc nitride thin film is deposited by magnetron radio-frequency sputtering at room temperature, while spin-on glass and aluminum were used as gate insulator and source/drain electrode, respectively. Polyethylene terephthalate is used as flexible substrate. The flexible Zn3N2 TFTs were characterized while bent to 5 mm tensile radius. The flexible TFTs exhibit an electron mobility of 3.8 cm 2 /Vs and an on/off current ratio close to 10 5 after several cycles of bending and being exposed to air ambient for 30 days.

The application of Zinc Oxide (ZnO) films by ultrasonic spray pyrolysis at 250, 300 and 450±C as active layer in thin-film Transistors (TFTs) is presented. The performance of the devices shows an unexpected behavior in function of the deposition temperature. The ZnO films were deposited from 0.2 M precursor solution of Zinc acetate in methanol, using air as carrier gas. 70nm-thick ZnO was deposited over 100 nm-thick Aluminum electrodes patterned on 50 nm-thick thermally grown SiO2 on highly doped Si wafers. The highly doped Si wafer was used as the gate electrode. The ZnO TFTs at 250±C showed field-effect mobilities around of 0.05 cm2/Vs and threshold voltages of 8 V.

In this paper, we study the ambipolar behavior of a-SiGe:H thin-film transistors fabricated at 200 °C. A subthreshold slope and an on/off current ratio of 0.34 V/DEC and 10 5 , respectively, were measured for the n-type region, whereas values of 0.15 V/DEC and 10 4 for were measured for the p-type region. We also obtained the characteristic energies for the deep localized states of the a-SiGe:H film, the flat-band voltages, and threshold voltages among other device parameters for the ambipolar thin-film transistors.

In this work the electrical characterization of n-channel a-SiGe:H TFTs with planarized gate electrode is presented. The planarized a-SiGe:H TFTs were fabricated at 200 • C on corning glass substrate. The devices exhibit a subthreshold slope of 0.56 V/Decade, an on/off-current ratio approximately of 10 6 and off-current approximately of 0.3×10 −12 A. The results show an improvement of the electrical characteristics when are compared to those unplanarized devices fabricated at higher temperature. Moreover, the simulation of the device using a SPICE model is presented.

ABSTRACTWe present the fabrication and characterization of low-temperature ambipolar thin-film transistors (TFTs) based on hydrogenated amorphous silicon-germanium (a-SiGe:H) as active layer. Inverted staggered a-SiGe:H TFTs were fabricated on Corning glass. Spin-on glass silicon dioxide was used as gate dielectric to improve the quality of the dielectric-semiconductor interface. For positive gate bias the transfer characteristic showed n-type TFT behavior, while for negative gate bias p-type behavior was observed. The n-type region exhibits subthreshold slope of 0.45 V/decade while the p-type region shows a subthreshold slope of 0.49 V/decade.

The present status and recent research results on amorphous oxide semiconductors (AOSs) and their thin-film transistors (TFTs) are reviewed. AOSs represented by amorphous In-Ga-Zn-O (a-IGZO) are expected to be the channel material of TFTs in next-generation flat-panel displays because a-IGZO TFTs satisfy almost all the requirements for organic light-emitting-diode displays, large and fast liquid crystal and three-dimensional (3D) displays, which cannot be satisfied using conventional silicon and organic TFTs. The major insights of this review are summarized as follows. (i) Most device issues, such as uniformity, long-term stability against bias stress and TFT performance, are solved for a-IGZO TFTs. (ii) A sixth-generation (6G) process is demonstrated for 32 and 37 displays. (iii) An 8G sputtering apparatus and a sputtering target have been developed. (iv) The important effect of deep subgap states on illumination instability is revealed. (v) Illumination instability under negative bias has been intensively studied, and some mechanisms are proposed. (vi) Degradation mechanisms are classified into back-channel effects, the creation of traps at an interface and in the gate insulator, and the creation of donor states in annealed a-IGZO TFTs by the Joule heating; the creation of bulk defects should also be considered in the case of unannealed a-IGZO TFTs. (vii) Dense passivation layers improve the stability and photoresponse and are necessary for practical applications. (viii) Sufficient knowledge of electronic structures and electron transport in a-IGZO has been accumulated to construct device simulation models.

The present status and recent research results on amorphous oxide semiconductors (AOSs) and their thin-film transistors (TFTs) are reviewed. AOSs represented by amorphous In-Ga-Zn-O (a-IGZO) are expected to be the channel material of TFTs in next-generation flat-panel displays because a-IGZO TFTs satisfy almost all the requirements for organic light-emitting-diode displays, large and fast liquid crystal and three-dimensional (3D) displays, which cannot be satisfied using conventional silicon and organic TFTs. The major insights of this review are summarized as follows. (i) Most device issues, such as uniformity, long-term stability against bias stress and TFT performance, are solved for a-IGZO TFTs. (ii) A sixth-generation (6G) process is demonstrated for 32 and 37 displays. (iii) An 8G sputtering apparatus and a sputtering target have been developed. (iv) The important effect of deep subgap states on illumination instability is revealed. (v) Illumination instability under negative bias has been intensively studied, and some mechanisms are proposed. (vi) Degradation mechanisms are classified into back-channel effects, the creation of traps at an interface and in the gate insulator, and the creation of donor states in annealed a-IGZO TFTs by the Joule heating; the creation of bulk defects should also be considered in the case of unannealed a-IGZO TFTs. (vii) Dense passivation layers improve the stability and photoresponse and are necessary for practical applications. (viii) Sufficient knowledge of electronic structures and electron transport in a-IGZO has been accumulated to construct device simulation models.