System on Chip (SoC)

We define some important properties of the permutation matrices of t-shuffle type which can be used to synthesize omega and inverse omega multistage interconnection networks. We also address some features of these networks compared to other networks of delta type. Finally, we propose one modification of omega network which decreases the number of stages in the network

Les composants de puissance a grand gap, SiC ou GaN, permettent d'atteindre de meilleures performances que les composants silicium (IGBT ou MosFet a superjonction), qui se traduisent par des temps de com-mutation plus faibles, des fonctionnements a frequences de decoupage plus importantes, ou des comportements en temperature plus interessants. Ces deux premiere caracteristiques ont une incidence fondamentale sur le comportement CEM des convertisseurs utilisant ces com-posants. Cet article presente la modelisation CEM d'un convertisseur de puissance a base de composants GaN (EPC 2010, 200V 12A). Nous allons d'abord decrire le modele du transistor adapte a de la modelisation CEM, pour ensuite presenter les mesures effectuees sur un bras de pont compose de deux transistors eGaN FETs, et enfin etudier du point de vue CEM les perturbations conduites generees par une structure LLC a base de transistors GaN fonctionnant a 1 MHz.

Il est bien connu que la commutation des semi-conducteurs et leurs interactions avec les éléments parasites liés à l'environnement est la source principale des perturbations conduites dans les convertisseurs d'électronique de puissance. Le développement d'une méthode simple, précise et rapide pour reconstruire ces perturbations constitue un défi majeur pour les concepteurs. Dans cet article, on propose une nouvelle méthode de modélisation basée sur des fonctions de transfert partielles configurables (FTPCs). Cette méthode permet, d'une part,

convertisseurs multicellulaires entrelacés qui est en mesure de nous mener à une meilleure compréhension de ses dynamiques. D'abord, nous présentons une modélisation bien détaillée des convertisseurs multicellulaires avec l'analyse de la stabilité de ces convertisseurs en se basant sur l'étude de la sensibilité aux variations paramétriques. Les avantages de l'architecture des convertisseurs parallèles DC-DC est de fournir une tolérance de défauts, de fortes intensités de courant de sortie avec faibles tensions de sortie. À la fin, nous présentons la stratégie de commande qui est basée sur la répartition équitable de courant en utilisant la commande par mode glissant. Outre la concordance avec ce qu'a prédit la théorie, les résultats de simulation sont satisfaisants.

Esta disserta»c~ao aborda a metodologia de desenvolvimento conhecida como hardwa- re/software co-design, motivada pela complexidade emergente do desenvolvimento de sis- temas digitais embarcados e os recentes progressos da tecnologia SoC (System-on-Chip). Nesse contexto, ¶e proposta uma metodologia capaz de atuar num elevado n¶³vel de abstra»c~ao, permitindo aos projetistas: um melhor gerenciamento da complexidade, uma visualiza»c~ao bem de¯nida do processo de desenvolvimento e um re¯namento suave entre os componentes do sistema, de maneira que as decis~oes de projeto e o particionamento entre os componentes de hardware e software possam ser realizados de maneira simples e natural. Com esse objetivo foi utilizado a linguagem de modelagem uni¯cada - UML (Uni¯ed Modeling Language), para especi¯ca»c~ao do sistema em alto n¶³vel, e a linguagem SystemC, para a cria»c~ao de prot¶otipos execut¶aveis e simula»c~oes dos v¶arios n¶³veis de abstra»c~ao de¯- nidos pela proposta. Para demonstra»...

Most semiconductor companies outsource the manufacturing of their chip designs to third-party fabrication foundries. However, untrusted foundries pose significant security risks, including intellectual property (IP) piracy and the insertion of hardware Trojans (HTs)-malicious modifications intended to sabotage circuits. These HTs can lead to increased power consumption, but due to process variations and the minimal footprint of small HTs in large-scale circuits, traditional power consumption analysis (PCA) often fails to detect them. To address this challenge, circuits can be partitioned into smaller sub-circuits, with PCA applied individually to each. In this paper, we propose a novel logic locking [2] technique designed to enhance the effectiveness of PCA-based HT detection. Building on the "RESTORATION" approach introduced in [1], our method increases the power contribution of HTs relative to the overall circuit power, thereby improving their detectability. Experimental results at both the gate level and post-synthesis demonstrate that the proposed locking scheme facilitates more efficient and reliable HT detection compared to existing logic locking [2] techniques.

this paper presents a novel on-chip antenna using standard cMoS-technology based on metasurface implemented on two-layers polyimide substrates with a thickness of 500 μm. the aluminium groundplane with thickness of 3 μm is sandwiched between the two-layers. concentric dielectric-rings are etched in the ground-plane under the radiation patches implemented on the top-layer. the radiation patches comprise concentric metal-rings that are arranged in a 3 × 3 matrix. The antennas are excited by coupling electromagnetic energy through the gaps of the concentric dielectric-rings in the groundplane using a microstrip feedline created on the bottom polyimide-layer. the open-ended feedline is split in three-branches that are aligned under the radiation elements to couple the maximum energy. in this structure, the concentric metal-rings essentially act as series left-handed capacitances C L that extend the effective aperture area of the antenna without affecting its dimensions, and the concentric dielectric rings etched in the ground-plane act as shunt left-handed inductors L L , which suppress the surface-waves and reduce the substrates losses that leads to improved bandwidth and radiation properties. The overall structure behaves like a metasurface that is shown to exhibit a very large bandwidth of 0.350-0.385 THz with an average radiation gain and efficiency of 8.15dBi and 65.71%, respectively. It has dimensions of 6 × 6 × 1 mm 3 that makes it suitable for on-chip implementation. Antenna is the key component to enable wireless communication however their physical size is a function of the operating frequency. Applications of on-chip antennas is therefore limited to high-frequencies due to the large size of antenna at lower frequencies. Off chip antennas however offer the benefit of radiation efficiency as they can be implemented on low-loss dielectric substrates 1-6 .. Currently, antennas for front-end transceivers can be realised using three different methods, which include: (i) Antenna-in-Package (AiP), where the antenna is embedded in the IC's packaging; (ii) Antenna-on-Chip (AoC), where the antenna is realized on substrate; and (iii) this is a hybrid of AoC and AiP, where the radiating element is realized off-chip. Wire bonding and flip chip are the two commonly used interconnections techniques employed in AiP to connect the die and the antenna 7 . These types of interconnects are highly lossy at high frequencies due to impedance mismatch. The only viable solution to overcome this loss is by using on-chip antenna, which should significantly reduce the manufacturing cost of system-on-chip (SoC). The development of a truly efficient cost effective on-chip antenna is a challenging endeavour. The main challenges are attributed to (1) low resistivity of dielectric substrates, which is approximately 10 ohm-cm, contributes to substrate loss of 85% whereas metallization loss is only 15%; (2) high permittivity substrate confines most of the electromagnetic energy in the substrate rather than being radiated into free-space, which adversely affect radiation efficiency 8 ; (3) no specific design rule for antenna design in standard technologies for on-chip antennas.

Network-On-Chip (NoC) is used as a main part of a system. NoC overcomes traditional System-On-Chip (SoC) problems. Because, SoC has problems like cost, design risk, more complexity and more power consumption. In software part, Xilinx ISE Design suite 14.5 with VHDL programming is used. It is simple programming language. In hardware part, FPGA of Spartan 3E family is used. It is advanced 90nm technology. It is world’s the cheapest FPGA family. It has 500K gates and 40 LUTs. It has lowest cost per logic. Its better advantage is that it is designed for more volume-to-market. Power consumption of given system is compared with previous system. From output power analysis chart, it is concluded that given system has lower power consumption than previous system. Power consumption of gray to binary conversion block of previous system is nearly equal to power consumption of present (given) whole system. This proves that there is a great reduction in power consumption in the system.

In a world where networks become a dominant form of organization, the structure of networks and the position of individuals in these networks affect individual behavior and aggregate economic outcomes. The analysis of network formation by a central planner or by individuals themselves is at the heart of this thesis on the economics of networks.Chapter 1 theoretically studies the optimal formation and protection of networks by a central planner knowing that an external agent can destroy k links. The protection of the network can be guaranteed either by densifying the links between nodes, or by protecting the links. When the cost of protection is relatively small, a minimally connected network composed of protected links guarantees the communication flow; if this cost is high, the optimal solution is to form a symmetric network where each node has at least k+1 non-protected links.Chapter 2 explores the decentralized formation of networks in the laboratory by analyzing individual linki...

As the complexity of evolving integrated circuits and the number of cores in each chip increase, reliability aspects are becoming an important issue in complex chip designs. In this paper, presents a Review of Previous works on On-Chip Network Design Using an Agent-based Management Method an on-chip network architecture that incorporates a novel agentbased management method to enhance the reliability and performance of network-based Chip Multi-Processor (CMP) and System-on-Chip (SoC) designs against faulty links and routers. In addition, to utilize the fault information required for the routing process in a scalable manner, to classify the fault information to be exploited in the distributed and hierarchical management structure.

2 , Cnam 3 , 61 avenue du président Wilson 94230 Cachan RESUME-Cet article présente la mise en oeuvre d'un convertisseur DC-DC de type VRM fonctionnant à 2 MHz à commande entrelacée et dont les sorties sont couplées magnétiquement par TICs (Transformateurs InterCellules) monolithiques. Ces derniers ont été réalisés par frittage SPS et les procédés de fabrication sont détaillés dans cet article. Le fonctionnement haute fréquence a été permis grâce à la mise en oeuvre de composants GaN.

Face aux enjeux energetiques actuels, l’electronique de puissance est un domaine de recherche de premier plan. La relative fragilite des composants presents dans les chaines de conversion implique neanmoins de devoir prendre en compte la gestion des defaillances des la phase de conception. La defaillance d'un composant est une situation hautement critique tant sur le plan de la securite environnante que sur le plan de l'indisponibilite du systeme qui en decoule. Cette problematique de surete de fonctionnement constitue la ligne directive de ce travail de these, visant a imaginer, et concevoir des solutions permettant de securiser ces structures en presence de defauts. Dans cette these, nous etudions de nouveaux composants magnetiques offrant un excellent compromis entre la densite de puissance traitee et rendement de conversion, mais tres sensibles a toutes perturbations electriques. Une methode de pre-dimensionnement des composants magnetiques a ete developpee et des soluti...

— In CMOS circuit’s design, as the threshold voltage is reduced due to voltage scaling, it leads to increase in sub-threshold leakage current and hence static power dissipation. In this paper we propose a power reduction technique named transistor gating. In this technique two sleep transistors PMOS and NMOS are inserted in between the supply voltage and ground. A PMOS is inserted in between pull-up network and network output and a NMOS is inserted in between pull-down network and ground. During standby mode both sleep transistor are turned off thereby increasing the resistance of the path from Vdd to ground, so that significant reduction in static power is achieved with increase in delay. This technique is tested on one bit full adder circuit. Design and simulation were done on cadence virtuoso and spectre tools using UMC 180nm process technology.

To execute more number of programs for an efficient Soflware / Hardware platform, the internal circuitry flow is considered. The data can be of bits-number of times the bits arriving with different time intervals. In this paper, we illustrate about the compressed test data from the embedded cores in a system on a chip varies significantly during the testing process. A novel scheme has been implemented for compressed system on a chip testing based on time-multiplexing for the channels. Some / more of the channels can be introduced which can enable the sharing the data channels, on which the compressed seeds are passed to every embedded core (individual cores). The channels can be fewer / larger based on the amount of testing channels available. The uses of modular and scalable hardware for on-chip test control and test data compression have been used. We design an algorithmic model for test data compression that is applicable to system-on-chip devices comprising intellectual property-protected blocks.

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-Une structure d'onduleur à résonance intégrant des composants distribués est présentée. Un prototype d'onduleur fonctionnant à 9.85 MHz en commutation douce et délivrant une puissance de 59 W est mis au point avec un rendement maximal mesuré de 77,5 %. Les résultats expérimentaux obtenus correspondent aux résultats fournis par le modèle numérique mis au point et suggèrent que des travaux complémentaires en lien la géométrie de la structure proposée sont à mener afin d'augmenter de manière significative son rendement.

Nos travaux portent sur l’etude d’une methodologie de modelisation predictive CEM en emission conduite pour une chaine d’actionnement (CA). L’objectif ultime, lie a l’utilisation de ces modeles pour le dimensionnement de ce systeme, est base sur une optimisation sous contraintes (conception sous contraintes). Au dela de l’application, nous cherchons a mettre en exergue les benefices d’une modelisation multi-niveaux dans la recherche d’un compromis entre la precision et la duree de simulation de ces modeles. Des lors, le but sera d’obtenir un modele predictif pour les perturbations electromagnetiques (PEM) d’emission conduite provenant de la CA etudiee et de confronter les resultats de simulations aux resultats experimentaux. Pour ce faire, le developpement d’un premier modele representatif des differents phenomenes physiques intervenant dans le systeme est necessaire de facon a simuler ces PEM. Dans le but d’ameliorer la precision et la duree de simulation de ce premier modele, nous...

Resumo. Contexto: Casos de Uso (Use Cases – UCs) tornaram-se um importante artefato para a especificação dos requisitos de software. No entanto, há várias dificuldades que impedem estudantes e engenheiros de software de especificarem UCs de forma correta. Objetivo: Para explorar e entender as dificuldades em especificar UCs, foi realizado um estudo qualitativo. Método: Utilizou-se entrevistas semiestruturadas com estudantes visando identificar estas dificuldades. A análise dos dados foi conduzida utilizando procedimentos do método Grounded Theory (GT). Resultados: Foi proposto um modelo que apresenta as dificuldades encontradas para especificação de UC. Estas dificuldades foram classificadas nas categorias: abstração dos requisitos, identificação e descrição dos fluxos, relacionamento entre as regras de negócio e os fluxos na especificação do UC. Conclusões: O modelo serve como base para futuras pesquisas na área, bem como no apoio à sugestão de práticas para melhorar o processo de ...

The reuse of use case specifications within a specific area of knowledge, rather than building them from scratch, is a strategy that not only can increase the quality of the new specifications but also can help their construction. This paper presents a current and ongoing research related with the reuse in Requirements Engineering. This includes a survey on the industry, a method and a web-based tool whose objective is to provide support for reuse in the Requirements community.

Resumo O ensino tradicional de engenharia de software, em geral, possui uma colaboração estrita e com o foco em competências técnicas. Estratégias de ensino ativas, em que o estudante vivencie os conteúdos apresentados, tirando-os da condição de meros observadores para manipuladores de instrumentos da realidade, têm se mostrado eficazes em engenharia de software. O mercado de trabalho atual exige novas competências dentro do contexto da transformação digital, em uma realidade com novos desafios, que vão desde modelar cenários de negócios, o que agrega complexidade ao software eà sua construção, a lidar com a interconexão entre pessoas, sistemas e tecnologias. A transição do ensino de engenharia de software tradicional para metodologias ativas, como a estratégia PBL (Problem Based Learning mostrou-se capaz de trazer essa realidade do mercado de trabalho com enfrentamento de desafios e decepções para sala de aula. Neste artigo relata-se a experiência na disciplina de omitida para revisão, no curso omitida para revisão da Universidade omitida para revisão Apresentam-se os conceitos abordados, o estudo de caso, método de trabalho com papéis e passos dos encontros. Além disso, alguns exemplos dos resultados obtidos (diagramas de requisitos, diagrama de contexto, diagrama de casos de uso, diagrama de classes, entrevistas, outros) que compuseram o GDD (Game Design Document, construído por cada grupo através dos encontros, os protótipos de jogos de cada grupo e a discussão acerca das competências desenvolvidas.

Face aux enjeux énergétiques actuels, l'électronique de puissance est un domaine de recherche de premier plan. La relative fragilité des composants présents dans les chaines de conversion implique néanmoins de devoir prendre en compte la gestion des défaillances dès la phase de conception. La défaillance d'un composant est une situation hautement critique tant sur le plan de la sécurité environnante que sur le plan de l'indisponibilité du système qui en découle. Cette problématique de sureté de fonctionnement constitue la ligne directive de ce travail de thèse, visant à imaginer, et concevoir des solutions permettant de sécuriser ces structures en présence de défauts. Dans cette thèse, nous étudions de nouveaux composants magnétiques offrant un excellent compromis entre la densité de puissance traitée et rendement de conversion, mais très sensibles à toutes perturbations électriques. Une méthode de prédimensionnement des composants magnétiques a été développée en régime nominal et lors de régimes déséquilibrés. Des solutions efficaces ont été apportés pour sécuriser et maintenir le fonctionnement du la chaine de conversion suite à l'apparition de plusieurs défauts. Des résultats expérimentaux démontrent et valident les approches théoriques sur les solutions de robustesses des composants magnétiques lors de régimes déséquilibrés.

RESUME-L'évaluation des pertes par commutation est une étape essentielle de la conception des convertisseurs statiques. Cependant, les pertes en commutation ne sont pas toujours correctement renseignées dans les notices des fabricants. La première manière de retrouver ces pertes est d'extrapoler les informations des spécifications techniques des fabricants par simulation ou analytiquement, la deuxième est de réaliser des mesures de pertes en commutation avec le composant. Nous présenterons ainsi une méthode de mesure de pertes par commutation non intrusive pour des composants rapides, tels que les composants 'grand gap' et les MOSFETs silicium. Nous développerons par la suite, un modèle comportemental d'un interrupteur de puissance de type MOSFET grâce à une routine de simulation automatisée en vue de l'estimation des pertes et les relevés expérimentaux seront présentés. Ces estimations sont ensuite utilisées pour dimensionner divers convertisseurs. Finalement, différentes topologies de convertisseurs statiques à base de composants GaN sont présentées et testées pour différentes applications.

RESUME-Cet article présente les limites de la commutation douce sur la topologie Flyback active-clamp dans le cadre d'une utilisation sur une large gamme de tension d'entrée. Nous avons mis au point une stratégie de suivi de commutation en creux de tension permettant le maintien d'une commutation en creux de tension permettant un gain de 2% à 4% par rapport à une commande classique sur la moitié haute de la plage de tension d'alimentation. Cette stratégie a été testée sur un convertisseur 30 W-12 V alimenté entre 20 V et 120 V. Mots-clés-Flyback, active-clamp, creux de tension, large plage.

System‐on‐chip (SoC) provides a comprehensive solution to the design challenges involved in the domain of telecommunication network, multimedia, and consumer electronics. One of the crucial components of any SoC network is the crossbar‐based switching circuit which synchronizes the network traffic and provides a congestion‐free path for communication. With the increase in number of on‐chip components the power consumed by crossbar schedulers takes a significant amount of the entire power budget. This indicates the need for techniques to reduce the area and energy consumption of on‐chip schedulers. In this article, we have proposed the design of on‐chip schedulers for implementation in quantum dot cellular automata (QCA) technology. QCA is the latest nano computation technology and emerging as an alternative to replace the conventional CMOS devices. The salient features of QCA are highly dense structure, extremely low power consumption, and very high processing speed. The proposed on...

This paper deals with the development of an adaptive speed controller for autonomous mobile robot using a fuzzy logic controller.The analysis of performance between a system applying triangular membership and a system using gaussian membership is compared to distinguish their differences. The results have shown that the gaussian membership method has improved the tracking performance for the mobile robot to reach its target. This also suggest the same behavior even when a different mobile robot movements is assigned. This paper considers three, five and seven memberships for both techniques to determine their effectiveness and effects to the system performance. The investigation has leads to the conclusion that the gaussian membership has competently surpassed the triangular membership performances even when the robot has different movements to achieve its target.

Today's real-time systems are the core of most ICT applications. The rapid development of such systems has attracted researchers' attention to optimize performance and to minimize as much as possible the problems and disadvantages they suffer in order to improve their performance in proportion to the volume of tasks entrusted to them. There are many major challenges facing real-time systems, which are mainly the problem of task scheduling on processor nuclei in the quantity of multi-core processors. Several methods have been proposed, including the general method, where any task can be executed on any kernel, the split method depends on the allocation of a specific kernel for each specific set of tasks. There is also the semi-fragmented method, which is a hybrid of the two previous methods, where a set of tasks is assigned to be executed on a particular kernel, while other functions are allowed to execute on any nucleus of the nucleus Treatment. In this paper we compare the performance of random task scheduling algorithms on a multi-core platform in order to determine the best algorithm in terms of a set of parameters adopted by researchers in this field, which in turn gives us precise details about the quality of such algorithms when applied to a set of distributed random tasks The unified logarithmic probability. The simso simulator, which has proven the reliability of high performance by many researchers in this field as well as provides the possibility of generating tasks according to specific probability distributions, and simulates accurate details in-depth characteristics of random tasks.

Le développement important des systèmes intégrés sur puce (SoC) 1 montre que ces systèmes embarquent une part de plus en plus important de mémoires. Globalement, les SoCs sont constitués de coeurs de traitement généraliste et/ou spécifique et accèdent, via un réseau sur silicium (NoC 2),à une organisation mémoire plus ou moins complexe. La connexion de cette organisation mémoire aux différents acteurs du système pour l'acheminement des données depuis ou vers la mémoire est un point critique du système. Dans cet article, nous nous intéressonsà ce problème d'interconnexion entre les acteurs et la mémoire pour une application temps réel a séquence d'accès déterministe. L'approche que nous proposons, consiste en la mise en place d'une interface flexible entre les mémoires et le réseau véhiculant l'ensemble des requêtes des acteurs du système. Cette interface doit s'assurer que le système est bien en mesure de sauvegarder et de récupérer des données dans les mémoires. Nous développons une formulation ILP (Integer Linear Programming) de ce problème et nous présentons un exemple de mise en oeuvre d'application de traitement d'images (DCT 3) pour illustrer l'échange des données et le rôle de l'interface.

Résumé: Le développement important des systèmes intégrés sur puce (SoC) 1 montre que ces systèmes embarquent une part de plus en plus important de mémoires. Globalement, les SoCs sont constitués de coeurs de traitement généraliste et/ou spécifique et accèdent, via un réseau sur silicium (NoC2), à une organisation mémoire plus ou moins complexe. La connexion de cette organisation mémoire aux différents acteurs du système pour l'acheminement des données depuis ou vers la mémoire est un point critique du système. ...

1. Resumo Sistemas embarcados sao compostos de hardware e software e normalmente executam aplicaçoes dedicadas em ambientes altamente restritivos. No projeto de sistemas embarcados temos caracterısticas altamente desejáves, como o reuso de componentes, ...

In multiprocessor system-on-chip (MPSoC), a CPU can access physical resources, such as on-chip memory or I/O devices. Along with normal requests, malevolent ones, generated by malicious processes running in one or more CPUs, could occur. A protection mechanism is therefore required to prevent injection of malicious instructions or data across the system. We propose a self-contained Network-on-Chip (NoC) firewall at the network interface (NI) layer which, by checking the physical address against a set of rules, rejects untrusted CPU requests to the onchip memory, thus protecting all legitimate processes running in a multicore SoC. To sustain high performance, we implement the firewall in hardware, with rule-checking performed at segmentlevel based on deny rules. Furthermore, to evaluate its impact, we develop a novel framework on top of gem5 simulation environment, coupling ARM technology and an instance of a commercial point-to-point interconnect from STMicroelectronics (STNoC). Simulation tests include scenarios in which legitimate and malicious processes, running in different CPUs, request access to shared memory. Our results indicate that a firewall implementation at the NI can have a positive effect on network performance by reducing both end-to-end network delay and power consumption. We also show that our coarse-grain firewall can prevent saturation of the on-chip network and performs better than fine-grain alternatives that perform rule checking at page-level. Simulation results are accompanied with field measurements performed on a Zedboard platform running Linux, whereas the NoC Firewall is implemented as a reconfigurable, memory-mapped device on top of AMBA AXI4 interconnect fabric.

RESUME-Le développement d'un packaging dédié aux transistors à grand gap (SiC et GaN) est un point clef pour tirer pleinement profit de leurs caractéristiques remarquables. Un packaging en trois dimensions, basé sur un procédé de fabrication des circuits imprimés, est présenté dans cet article. Une cellule de commutation à base de MOSFET SiC est développé avec une inductance parasite de seulement 0.25nH. De plus, les interconnexions électriques du module sont réalisées sans brasures ni fil de bonding. Un module 3D est fabriqué puis validé expérimentalement. Des caractérisations électriques statiques et dynamiques sont réalisées et valident électriquement le concept « Power Chip On Chip » avec un procédé de fabrication de circuit imprimé.

(En Anglais) In recent years, the interest for parallel multicell converter has grown, which is partially due to the possibility of coupling the inductors used to connect the different commutation cells together. Coupling the inductors to form an InterCell Transformer (ICT) does not usually modify the output current, but it reduces the current ripple in windings and the flux swing in some regions of the core. It can be shown that this brings a reduction of copper and core losses in the magnetic component. The reduction of the phase current ripple also reduces the difference between turn on and turn off current in the switches, which brings a reduction of switching losses for devices generating more losses at turn off than at turn on. This article focuses on the modulation of multicell converters with the aim of simulating the paralleling of chopper arms by a magnetic coupler. The modeling of the multicellular parallel converter with three switching cells has been made, using a coupling with independent inductors, and the other a coupling with inter-cell transformers. All circuits are modeled and simulated using Matlab/Simulink.

RESUME-Ce papier présente l'analyse des perturbations à haute fréquence provoquées par la commutation des interrupteurs de puissance dans un convertisseur Buck. L'impact de différents paramètres de la cellule de commutation est traité analytiquement pour permettre la prédiction des performances CEM du convertisseur, en amont de son design complet. L'analyse est ici poursuivie par l'étude de l'amélioration des performances CEM qui peut être apportée par le choix d'une structure parallèle à commandes entrelacées. Les convertisseurs comparés le sont à surface de silicium (encombrement des composants de puissance) et rendement égaux.

In all respects of the last five decades, integrated circuit technology has advanced at exponential rates in both productivity and performance. Giga-Scale Integration (GSI) System-On-A-Chip (SoC) designs have become one of the main drivers of the integrated circuit technology in recent years. The objective of this work is to understand the challenges of Giga-scale SoC integration in nanometer technologies, and identify promising conveniences for innovation. Physical designs are crucial for SoC integration and in our work we identify them with details. In future the couplings and interactions among system components will increase as we put more of the system on a silicon die. Therefore the system designers will face challenges in several areas and we describe these future challenges briefly. Developing a design driver for GSI SoC design is important. With the help of this design driver we provide the design methodology, which ensures the high performance of the design. We present two...

(En Anglais) In recent years, the interest for parallel multicell converter has grown, which is partially due to the possibility of coupling the inductors used to connect the different commutation cells together. Coupling the inductors to form an InterCell Transformer (ICT) does not usually modify the output current, but it reduces the current ripple in windings and the flux swing in some regions of the core. It can be shown that this brings a reduction of copper and core losses in the magnetic component. The reduction of the phase current ripple also reduces the difference between turn on and turn off current in the switches, which brings a reduction of switching losses for devices generating more losses at turn off than at turn on. This article focuses on the modulation of multicell converters with the aim of simulating the paralleling of chopper arms by a magnetic coupler. The modeling of the multicellular parallel converter with three switching cells has been made, using a coupling with independent inductors, and the other a coupling with inter-cell transformers. All circuits are modeled and simulated using Matlab/Simulink.

System‐on‐chip (SoC) provides a comprehensive solution to the design challenges involved in the domain of telecommunication network, multimedia, and consumer electronics. One of the crucial components of any SoC network is the crossbar‐based switching circuit which synchronizes the network traffic and provides a congestion‐free path for communication. With the increase in number of on‐chip components the power consumed by crossbar schedulers takes a significant amount of the entire power budget. This indicates the need for techniques to reduce the area and energy consumption of on‐chip schedulers. In this article, we have proposed the design of on‐chip schedulers for implementation in quantum dot cellular automata (QCA) technology. QCA is the latest nano computation technology and emerging as an alternative to replace the conventional CMOS devices. The salient features of QCA are highly dense structure, extremely low power consumption, and very high processing speed. The proposed on...

The Freescale analog design team in Toulouse develops integrated circuits for automotive application: ASICs (Application-Specific Integrated Circuits) or standard products for chassis, engine, safety or infotainment application. Constraints associated with the embodiment of such circuits are many: die-size, cost, safety, qualification for hot temperature, and EMC (Electromagnetic Compliance). In most ICs (Integrated Circuits), power supplies are embedded. They supply power to embedded microcontroller, sensors or electromechanical devices. In these low-power automotive applications, power converters have an output voltage in a range between 1.2V to 7V, for a load current up to 1A. Power is supplied by the car battery whose voltage can vary from 4V (car start) to 40V (load dump). The need of high efficiency makes the use of SMPS (Switch Mode Power Supply) mandatory, while it implies voluminous passive devices for filtering. The evolution and the increase of electronic circuits connected to the same battery node imply very harsh Conducted Emission (CE) constraints. This creates the need for new converter topologies study and for optimization methods, for more efficient and less emissive converters. This PhD thesis is to study and compare advanced non isolated converter topologies, to challenge the limitations of the basic single-phase converter. Three Buck topologies are compared on three points: efficiency, volume of the filters, and conducted emissions at the input. These topologies are two quasi-resonant Buck converters with soft switching, ZVS (Zero Voltage Switching) and ZCS (Zero Current Switching), and the multiphase Buck with "N" interleaved cells in parallel. The study shows that conduction losses are too high in quasiresonant converters sized for this kind of application, because of the wide range of the input voltage. In contrast, multiphase Buck converters respond to the need of improved efficiency and the need of reduced filters. The study of the conducted emission level at the input of multiphase Buck converters shows that the elevation of the number of cells in parallel allows the reduction of the high frequency disturbances magnitude. The interleaved multiphase topology responds to the all three raised challenges of the thesis. A prototype with five interleaved cells in parallel is produced. A chip is developed in the Freescale smartmos8 0.25µm BiCMOS technology. It integrates all the silicium power devices: switches, drivers, and linear power supplies for the drivers. The volume of the external filter is optimized. Cells are controlled by 1MHz PWM signals from an external chip from Intersil. All the devices are mounted on a four layers PCB. The prototype shows a very low level of conducted emissions at the input despite the low volume of the filtering passive components.

Digital RF solutions have been shown to be advantageous in various design aspects, such as accurate modeling, design reuse, and scaling when migrating to the next CMOS process node. Consequently, the majority of new low-cost and feature cell phones are now based on this approach. However, another equally important aspect of this approach to wireless transceiver SoC design, which is instrumental in allowing fast and low-cost productization, is in creating the inherent capability to assess performance and allow for low-cost built-in calibration and compensation, as well as characterization and final-testing. These internal capabilities can often rely solely on the SoCs existing processing resources, representing a zero cost adder, requiring only the development of the appropriate algorithms. This paper presents various examples of built-in measurements that have been demonstrated in wireless transceivers offered by Texas Instruments in recent years, based on the digital-RF processor (DRP TM) technology, and highlights the importance of the various types presented; built-in self-calibration and compensation, built-in self-characterization, and builtin self-testing (BiST). The accompanying statistical approach to the design and productization of such products is also discussed, and fundamental terms related with these, such as 'soft specifications', are defined.

Utilization of the third dimension can lead to a significant reduction in power and average hop-count in Networks-on-Chip (NoC). TSV technology, as the most promising technology in 3D integration, offers short and fast vertical links which copes with the long wire problem in 2D NoCs. Nonetheless, TSVs are huge and their manufacturing process is still immature, which reduces the yield of 3D NoC based SoC. Therefore, Vertically-Partially-Connected 3D-NoC has been introduced to benefit from both 3D technology and high yield. Moreover, Vertically-Partially-Connected 3D-NoC is flexible, due to the fact that the number, placement, and assignment of the vertical links in each layer can be decided based on the limitations and requirements of the design. However, there are challenges to present a feasible and high-performance Vertically-Partially-Connected Mesh-based 3D-NoC due to the removed vertical links between the layers. This thesis addresses the challenges of Vertically-Partially-Connected Mesh-based 3D-NoC: Routing is the major problem of the Vertically-Partially-Connected 3D-NoC. Since some vertical links are removed, some of the routers do not have up or/and down ports. Therefore, there should be a path to send a packet to upper or lower layer which obviously has to be determined by a routing algorithm. The suggested paths should not cause deadlock through the network. To cope with this problem we explain and evaluate a deadlock-and livelockfree routing algorithm called Elevator First. Fundamentally, the NoC performance is affected by both 1) micro-architecture of routers and 2) architecture of interconnection.

Utilization of the third dimension can lead to a significant reduction in power and average hop-count in Networks-on-Chip (NoC). TSV technology, as the most promising technology in 3D integration, offers short and fast vertical links which copes with the long wire problem in 2D NoCs. Nonetheless, TSVs are huge and their manufacturing process is still immature, which reduces the yield of 3D NoC based SoC. Therefore, Vertically-Partially-Connected 3D-NoC has been introduced to benefit from both 3D technology and high yield. Moreover, Vertically-Partially-Connected 3D-NoC is flexible, due to the fact that the number, placement, and assignment of the vertical links in each layer can be decided based on the limitations and requirements of the design. However, there are challenges to present a feasible and high-performance Vertically-Partially-Connected Mesh-based 3D-NoC due to the removed vertical links between the layers. This thesis addresses the challenges of Vertically-Partially-Connected Mesh-based 3D-NoC: Routing is the major problem of the Vertically-Partially-Connected 3D-NoC. Since some vertical links are removed, some of the routers do not have up or/and down ports. Therefore, there should be a path to send a packet to upper or lower layer which obviously has to be determined by a routing algorithm. The suggested paths should not cause deadlock through the network. To cope with this problem we explain and evaluate a deadlock-and livelockfree routing algorithm called Elevator First. Fundamentally, the NoC performance is affected by both 1) micro-architecture of routers and 2) architecture of interconnection.

No presente trabalho é apresentada uma arquitetura para acelerar o ciclo do projeto de sistemas digitais na etapa de prototipação. A ferramenta em questão consiste em uma placa para prototipação (comercializada pela empresa inglesa Sundance) composta por um dispositivo lógico programável (FPGA), um processador Transputer, memórias e compiladores (para geração dos arquivos de configuração do FPGA e código a ser executado pelo Transputer). Na implementação dois enfoques são abordados: sistemas descritos totalmente em hardware; e sistemas descritos parte em hardware e parte em software. Os sistemas são descritos na forma de processos concorrentes e comunicantes, sendo que os processos de hardware são implementados em Handel-C (FPGA) e os processos de software são implementados em occam (Transputer). Com a utilização da placa de prototipação é possível avaliar quais processos devem ser executados em hardware (tempo de execução crítico) e quais devem ser executados em software. Esse trabalho está sendo desenvolvido no âmbito do projeto PISH (PROTEM-CNPq), do qual participam a UFPE, UFRGS e PUCRS.

Cet article présente des travaux de modélisation CEM (Compatibilité Electro-Magnétique) d'une chaîne de puissance utilisée dans une application pour véhicules électriques ou hybrides (VHE). Un modèle est développé, en domaine temporel, dans l'objectif de prédire les perturbations en mode conduit. Ce modèle sera utilisé par la suite pour dimensionner un filtre CEM passif afin de réduire ces perturbations dans la gamme de fréquences 150 KHz-108 MHz imposée par la norme CISPR 25. Le modèle développé prend en considération les différents éléments parasites existant sur la chaine de puissance (Printed Circuit Board (PCB), connexions, composants passifs et actifs, moteurs, câblages). Pour étudier la validité du modèle conduit, un banc de test CEM a été réalisé à l'IRSEEM permettant d'effectuer des mesures normatives sur toute la gamme de fréquence. Les résultats obtenus ont montré une bonne concordance entre le modèle et les résultats expérimentaux. Ces travaux s'inscrivent dans le cadre du projet COMPACITE soutenu par le pôle de compétitivité MOV'EO.

This paper presents a delay compensator fuzzy control for trajectory tracking of omni-directional mobile robots. Fuzzy logic control (FLC) of the robots is a suitable strategy for dealing with model uncertainties, nonlinearities and disturbances. On the other hand, in many robotic applications such as mobile robots, delay phenomenon is able to substantially deteriorate the behavior of system's performance if not considered in the controller design. In this work, a delay compensator strategy is employed in order to eliminate the influence of dead time problem. On the other hand, a discrete-time kinematic model is presented for high level control of SSL soccer robots. Also, the model uncertainties are considered as multiplicative parameters and external random disturbances are noticed as additive parameters. The simulation experiments as well as real system experiments demonstrate that the proposed method handles both constant time delay and uncertainties with a small tracking err...

A new floating-gate (FG) MOSFET based wireless dosimeter system-in-package (SiP) is presented. This miniature and completely integrated wireless dosimeter SiP comprises a CMOS FG radiation sensor and transmitter (TX) in a low-temperature co-fired ceramic (LTCC) package. The design is very well suited to wireless transmission of radiation sensor data in radiotherapy and to Extra Vehicular Activity Radiation Monitoring (EVARM) in space. Two different solutions, namely system-on-chip (SoC) and SiP, are demonstrated. In the SoC, which is size and power efficient, the TX includes an on-chip loop antenna which also acts as the inductor for the VCO resonant tank circuit. The SiP solution has an LTCC antenna with optimized impedance to conjugate match the TX chip. The radiation sensor demonstrates a measured sensitivity of 5 mV/rad. The SoC module size is only 2 mm 2 , consumes 5.3 mW of power and delivers 0.9 dBm of radiated power, sufficient to communicate with a low noise receiver connected to an off-chip patch antenna placed 1.38 m away. The SiP design provides a larger communication range of 75 m at the cost of additional power consumption and size. Index Terms-Integrated transmitter, low-temperature co-fired ceramic (LTCC), on-chip antenna, system-in-package (SiP), system-on-chip (SoC), wireless dosimeter.

Three-dimensional (3D) surface anthropometry enables us to extend the study to 3D geometry and morphology of human body. The purpose of this study is to build a whole 3D body scanner. Using lasers and cameras mounted on a scanning platform moved by a single motor and controlled by an embedded controller, a device has been implemented to capture the shape of the entire human body. One application case study (body fat percentage) is presented. The results suggests that the developed scanner can be useful for that particular case study and other like size surveying and medicine

Le prototypage virtuel des equipements electriques est aujourd'hui devenu incontournable dans les phases de developpement et se doit evidemment d'integrer l'ensemble des contraintes critiques jouant directement sur le design des convertisseurs de puissance (rendement, cout, volume, poids, thermique…). L'objectif de cette etude est de proposer une methode de dimensionnement des inductances de mode commun realisees sur des circuits magnetiques toriques. Ces elements, presents dans la quasi-totalite des structures de puissance commercialisees, sont generalement dimensionnes a partir de mesures sur un prototype, par une approche de type "essai-erreur". Si cette demarche permet dans la majeure partie des cas de repondre aux contraintes normatives, elle est toutefois loin d'etre satisfaisante et ne permet pas de definir les elements representant "la meilleure solution" pour le filtrage de la structure developpee.

System on chip is integration of multimillion transistors in single chip for reducing the cost of design. With the new level of integration the System on Chip design is methodology where intellectual property blocks combined on single chip and allow huge chips to be design at acceptable cost and quality. Hence a standard interface bus protocol is required to increase the productivity with design time reduction. Wishbone is flexible System on Chip bus architecture, connecting IP cores together and alleviating System on Chip integration problems. Wishbone can communicate over variety of devices. Motivated by this, this paper presents different feature of wishbone bus interface. TheSoC design with DMA master cores and memory slave cores using wishbone point to point interconnection and shared bus interconnection scheme has been designed in Xilinx 12.3. This paper investigates and compare wishbone interconnection point to point and shared scheme.