Built-In Measurements in Low-Cost Digital-RF Transceivers

2010 53rd IEEE International Midwest Symposium on Circuits and Systems, 2010

A novel design-for-testability approach is proposed, which is derived from the aggressive probabilistic targets set forth for the yield and quality to be achieved in the massproduction of high-volume low-cost transceiver SoCs, thus requiring solutions that are fundamentally different from the traditional approaches. Statistical analysis is presented as the basis for the proposed approach, and specific guidelines are defined and demonstrated through examples. The proposed approach, based on built-in-self-testing (BIST) of RF/mixedsignal functions in the transceiver SoC, relies on digital processing resources that are typically available within the SoC at no additional cost and may aid in its testing and calibration. The important roles of characterization and built-in-selfcalibration and compensation in this context are also defined.

Proceedings of the 24th edition of the great lakes symposium on VLSI - GLSVLSI '14, 2014

Taking advantage of continuous advances in the integrated CMOS technology, systems-on-chip (SoC) designs that include analog mixed-signal (AMS) circuits are widely used. Their applications in communications, signal processing, and embedded systems are also increasing. Even though the technology and circuit performance are This thesis could not have been written without Dr. Kim, who not only served as my supervisor, but also encouraged and challenged me throughout my academic program. He and other faculty members, Dr. Onabajo and Dr. Lombardi, guided me through the thesis process, never accepting less than my best efforts. I thank them all.

IEEE Communications Magazine, 2003

IEEE Microwave Magazine, 2020

F and microwave system design is a complex process that often requires several iterations of subsystem design. An example is a mixed-signal component (where analog and digital waveforms coexist) composed of several subsystems, with the most important being the sampling circuit and quantization subsystem, possibly extended with RF up-or downconversion. Analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) are mixed-signal components used in softwaredefined radio (SDR) front ends. Understanding the behavior of these mixed-signal components is important when it is necessary to connect them to other components in building a full RF system. Motivation The common approach for representing the behavior of traditional RF building blocks in computer-aided design/computer-aided engineering (CAD/CAE) solutions is to use measurementbased models [for example, the use of scattering parameters (S-parameters) to represent the linear behavior of filters or amplifiers]. This approach captures some important nonidealities that allow engineers to optimize their RF designs in a way that, if considering them as ideal, would not be achievable. However, most of the time, the models of mixed-signal components are considered as ideal approximations by RF engineers when they use CAD/ CAE tools. One example is in SDR front ends, where the use of mixed-signal components like ADCs and DACs is fundamental to the overall solution. The RF characteristics of these components (such as the input/output impedance) vary with frequency. This implies that a correct characterization of their frequency response will significantly improve the overall SDR front-end design and operation. The ability to use those models as we use S-parameter models is of high interest to the optimization of RF and microwave system design. One of the challenges of 5G is to increase the signal bandwidth, which creates the need to use higher-speed data converters. For example, RF ADCs, RF DACs, and integrated RF-signal systems-on-chip (SoCs) operate directly at RF bands. However, these devices cannot be considered as ideal, and their frequency response must be taken into account throughout the design process. Another relevant aspect in 5G is the increase of antenna structures for massive multiple input/multiple output, bringing distributed amplification into the loop

IEEE Transactions on Very Large Scale Integration Systems, 2010

The essentials of the on-chip loopback test for integrated RF transceivers are presented. The available on-chip baseband processor serves as a tester while the RF front-end is under test enabled by on-chip test attenuator and in some cases by an offset mixer, too. Various system-level tests, like BER, EVM or spectral measurements are discussed. By using this technique in mass production, the RF test equipment can be largely avoided and the test cost reduced. Different variants of the loopback setup including the bypassing technique and RF detectors to boost the chip testability are considered. The existing limitations and tradeoffs in terms of test feasibility, controllability, and observability versus the chip performance are discussed. The fault-oriented approach supported by sensitization technique is put in contrast to the functional test. Also the impact of production tolerances is addressed in terms of a simple statistical model and the detectability thresholds. The paper is based on the present and previous work of the authors, largely revised and upgraded to provide a comprehensive description of the on-chip loopback test. Simulation examples of practical communication transceivers such as WLAN and EDGE under test are also included. He has specialized in macromodeling and simulation of analog and mixed-signal circuits. Currently, he is an Associate Professor at Linköping University, Sweden. His recent research interests are in RF ICs design and design-for-testability for analog/RF circuits. He published over 80 research papers in international journals and conference proceedings, and one monograph. He holds 12 patents (as a coauthor) in switched-mode power supplies and electronic instrumentation.

IBM Journal of Research and Development, 2003

The rapidly expanding telecommunications market has led to a need for advanced rf integrated circuits. Complex rf-and mixed-signal system-on-chip designs require accurate prediction early in the design schedule, and time-to-market pressures dictate that design iterations be kept to a minimum. Signal integrity is seen as a key issue in typical applications, requiring very accurate interconnect transmission-line modeling and RLC extraction of parasitic effects. To enable this, IBM has in place a mature project infrastructure consisting of predictive device models, complete rf characterization, statistical and scalable compact models that are hardware-verified, and a robust design automation environment. Finally, the unit and integration testing of all of these components is performed thoroughly. This paper describes each of these aspects and provides an overview of associated development work.

IEEE Transactions on Circuits and Systems II: Express Briefs, 2006

We propose a least-mean square based gain calibration technique of an RF digitally controlled oscillator (DCO) in an all-digital phase-locked loop (ADPLL). The DCO gain of about 12-kHz/least significant bit is subject to process, voltage and temperature variations, but is tracked and compensated in real time. Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wide-band frequency modulation that is independent from the ADPLL loop bandwidth. The technique is part of a single-chip fully compliant Global System for Mobile Communications (GSM)/EDGE transceiver in 90-nm digital CMOS.

Testing of on-chip RF and microwave circuits has always been a challenge to the test engineers. Since the emergence of System-on-a-Chip (SoC), characterization and test development is time-consuming, they contribute to a significant part of the manufacturing cost. Moreover, test development of RF and microwave circuits requires years of experience and expertise. In this paper, we propose to use built-in-test in the form of specific sensors. Instead of testing the devices specifically for certain performance metrics, the output values of the sensors, which are usually DC or a very low frequency signal, can be used to get a quick and accurate estimate of the behavior of the device under test (DUT). For a relatively low-yielding process, which is usually the case for RF and microwave circuits, significant number of faulty devices can be identified without even performing the standard manufacturing test on the devices. Moreover, these sensors can also be used for on-line test. In this paper, we also propose an algorithm to optimally place the sensors at the output of a system-under-test and use the sensor output to get an estimate of the specifications of the system-under-test. Using this method, specifications can be estimated within an accuracy of ±3% of its actual value

2013 European Conference on Circuit Theory and Design (ECCTD), 2013

In this paper a technique suitable for on-chip IP3/IP2 RF test by embedded RF detectors is presented. A lack of spectral selectivity of the detectors and diverse nonlinearity of the circuit under test (CUT) impose stiff constraints on the respective test measurements for which focused calibration approach and a support by customized models of CUT is necessary. Also cancellation of second-order intermodulation effects produced by the detectors under the two-tone test is required. The test technique is introduced using a polynomial model of the CUT. Simulation example of a practical CMOS LNA under IP3/IP2 RF test with embedded RF detectors is presented showing a good measurement accuracy.

IEEE Journal of Solid-State Circuits, 2003

The drive for cost reduction has led to the use of CMOS technology in the implementation of highly integrated radios. This paper presents a single-chip 5-GHz fully integrated direct conversion transceiver for IEEE 802.11a WLAN systems, manufactured in 0.18-m CMOS. The IC features an innovative system architecture which takes advantage of the computing resources of the digital companion chip in order to eliminate mismatch and achieve accurately matched baseband filters. The integrated voltage-controlled oscillator and synthesizer achieve an integrated phase noise of less than 0.8 rms. The receiver has an overall noise figure of 5.2 dB and achieves sensitivity of 75 dBm at 54-Mb/s operation, both referred to the IC input. The transmit error vector magnitude is 33 dB at 5-dBm output power from the integrated power-amplifier driver amplifier. The transceiver occupies an area of 18.5 mm 2 .