Silicon Germanium

Product designs for 40-Gb/s applications fabricated from SiGe BiCMOS technologies are now becoming available. This paper will first briefly discuss heterojunction bipolar transistor (HBT) device operation at high speed, demonstrating that perceived concerns regarding lower CE0 and higher current densities required to operate silicon HBTs at such high speeds do not in actuality limit design or performance. The high-speed portions of the 40-Gb/s system are then addressed individually. We demonstrate the digital capability through a 4 : 1 multiplexer and a 1 : 4 demultiplexer running over 50 Gb/s error free at a 3.3-V power supply. We also demonstrate a range of analog elements, including a lumped limiting amplifier which operates with a 35-GHz bandwidth, a transimpedance amplifier with 220gain and 49.1-GHz bandwidth, a 21.5-GHz voltage-controlled oscillator with over 100-dBc/Hz phase noise at 1-MHz offset, and a modulator driver which runs a voltage swing twice the CE0 of the high-speed SiGe HBT. These parts demonstrate substantial results toward product offerings, on each of the critical high-speed elements of the 40-Gb/s system.

Electro-thermal model of power semiconductor devices are of key importance in order to optimize their thermal design and increase their reliability. The development of such an electro-thermal model for power MOSFET transistors (COOLMOS TM ) based on the coupling between two computation softwares (Matlab and Cast3M) is described in the paper. The elaborated 2D electro-thermal model is able to predict i) the temperature distribution on chip surface well as in volume, ii) the effect of the temperature on the distribution of the current flowing within the die and iii) the effects of the ageing of the metallization layer on the current density and the temperature. In the paper, the used electrical and thermal models are described as well as the implemented coupling scheme.

In this work, the effect of boron concentration on the critical thickness of heavily boron doped Si 1-x Ge x alloys ͑Si 1-x-y Ge x B y ͒ has been studied using Raman spectroscopy. The experimental results indicate that while boron decreases the stored strain energy, it can substantially increase the critical thickness for a given Ge concentration. The Si 1-x-y Ge x B y critical thickness was calculated using two different models based on energy balance and kinetic considerations. The results show that the kinetic model provides a good estimate for the Si 1-x-y Ge x B y critical thickness.

The impact of heavy boron doping on the biaxial compressive strain in Si1−xGex layers grown on Si has been investigated using Raman spectroscopy and theoretical calculations. It is shown that one boron atom is sufficient to compensate the strain due to approximately 6.9 Ge atoms. This effect is appreciably large for boron concentrations as low as 1%, typical for applications, which employ heavily boron doped layers. Using strain compensation, the Ge content can be substantially increased without increasing the stored strain energy. This phenomenon can be useful in applications, which require low-resistivity p-type strained Si1−xGex layers with high Ge content.

When a thin Si1−xGex epitaxial layer is grown on Si, it is under biaxial compression. In this letter, it is shown that a nickel germanosilicide (NiSi1−xGex) layer formed on Si1−xGex can significantly reduce the in-plane compressive strain in Si1−xGex. It is proposed that the observed reduction is due to the biaxial tensile stress applied by the NiSi1−xGex layer. Because the Si1−xGex bandgap is a strong function of the strain, this is expected to have a strong impact on the metal-semiconductor barrier height and the contact resistivity of the interface if the metal Fermi level is pinned near the Si1−xGex midgap.

The dc and ac performance of advanced SiGe:C heterojunction bipolar transistors (HBTs) featuring transit frequency (f T ) and maximum oscillation frequency (f max ) of 300 and 500 GHz was characterized from 298 K down to 4.3 K. At 4.3 K, the transit frequency f T increases by 65% from measured 317 GHz (at 298 K) to 525 GHz. The increase of f T starts to saturate below 73 K. The physical reasons for the temperature variation of the experimental characteristics and simple model extensions for improving existing compact models (CMs) are discussed so that they can be used for estimating circuit design results at cryogenic temperatures (CTs). The model extensions are verified using experimental data. To the best of our knowledge, this is the first demonstration of modeling advanced SiGe:C HBTs for such a wide temperature range from deep cryogenic to room temperature (RT) (4.3-298 K). INDEX TERMS Compact modeling, cryogenic modeling, cutoff frequency, heterojunction bipolar transistor (HBT), HIgh CUrrent Model (HICUM), quantum computing, SiGe, transfer characteristics.

The cutoff frequency performance of an NPN Si/SiGe/SiGe single-heterojunction bipolar transistor (SiGe SHBT) at high collector current densities has been analysed using a 2-D MEDICI device simulator. A conventional NPN Si/SiGe/Si double-heterojunction bipolar transistor (SiGe DHBT) having uniform 20 atomic per cent of germanium in the base region has been investigated for comparison. The analysis shows the formation of a retarding potential barrier for minority carrier electrons at the base-collector heterojunction of the DHBT structure. Whereas, the base-collector homojunction of the SiGe SHBT structure, having a uniform 15 atomic per cent of germanium profile in its base and collector, inhibits the formation of such a retarding potential barrier, the SHBT structure with a base-collector homojunction shows an improved cutoff frequency at high collector current density in comparison with conventional SiGe DHBT, which makes it more promising for high speed, scaled down, field-specific applications.

This paper describes the design and characteristics of a highly efficient multilayer parasitic microstrip antenna array (MPMAA) constructed on a multilayer substrate for millimeter-wave system-on-package modules. The antenna on a Teflon substrate achieved a radiation efficiency of greater than 91% and an associated antenna gain of 11.1 dBi at 60 GHz. Its size is only 10 mm × 10 mm. We discuss MPMAAs fabricated on both Teflon and low-temperature cofired ceramic (LTCC) substrates. The measured performances of prototype antennas are also presented. The MPMAA offers compactness and high efficiency and is easily integrated with the system-on-package design. It will lead to compact and cost-effective millimeter-wave RF modules.

Electrons in silicon/silicon-germanium two-dimensional electron gas quantum dots are a promising architecture for spin based quantum computation. Top gated quantum dots allow precise tuning of electron shape and interdot coupling. We report the observation of Coulomb blockade in Si/SiGe quantum dots defined by a combination of etching and metal top gating. A narrow channel or mesa is fabricated by electron beam lithography and subsequent reactive ion etching. Metal gates are deposited across the channel to define the leads of the dot. The sides of dot are defined by surface depletion from the etched sidewalls. Low temperature measurements (250mK) show a single electron charging energy of about 0.8meV. We use an etch-defined side gate to vary the potential in the dot, observing several conductance oscillations as the blockade is lifted, with a period of 280mV.

The present work presents a comparative theoretical analysis of SiGe channel nano scale FinFET devices. FinFETs provide a better gate control over channel region then conventional planner MOSFETs and hence are better suited for sub 100 nm device architectures. SiGe material shows higher mobility and lower effective masses of charge carrier and is utilized to provide efficient transport characteristics of electrons in channel area of FETs. The proposed device architecture is incorporated with SiGe channel. A theoretical analysis is performed in order to understand device performance with different Ge mole fractions in SiGe channel region of FinFETs. The SiGe channel FinFET shows better ON state characteristics then conventional Si channel FinFET. Silvaco ATLAS simulator is used with appropriate models to implement and characterize all device structures. This work would be useful in selecting the mole fraction in application specific SiGe channel Transistors.

Si resonant interband tunnel diodes that demonstrate negative differential resistance at room temperature, with peak-to-valley current ratios greater than 2, are presented. The structures were grown using low-temperature ͑320 °C͒ molecular-beam epitaxy followed by a postgrowth anneal. After a 650 °C, 1 min rapid thermal anneal, the average peak-to-valley current ratio was 2.05 for a set of seven adjacent diodes. The atomic distribution profiles of the as-grown and annealed structures were obtained by secondary ion mass spectrometry. Based on these measurements, the band structure was modeled and current-voltage trends were predicted. These diodes are compatible with transistor integration.

Hall effect measurements in the 4 Á/300 K temperature range have been used to investigate the electrical properties of B doped Si 1(x Ge x layers (with 0 5/x 5/0.2) grown on Si(100) by MBE. The Hall concentration and mobility of strained and relaxed Si 1(x Ge x layers have been converted into carrier concentration and drift mobility using the appropriate Hall scattering factor r H that has been determined by the comparison between the chemical B concentration profile (measured by secondary ion mass spectrometry) and the Hall carrier concentration. The mobility of both relaxed and strained layers was equal to that of Si and independent of the Ge concentration for x B/0.2 and B concentration ]/10 18 cm (3 . The Hall scattering factor as a function of temperature has been determined.

Measurements using a pulse voltage stress (PVS) technique whereby dual pulse waveforms, differing in phase, gave rise to astonishing preliminary results: the lifetime of the devices were substantially reduced as compared to both constant voltage stress (CVS) and single waveform PVS. a ramped voltage stress (RVS) stress from 0 to -12V. The inverter was configured using an nMOSFET and pMOSFET device, both with a gate oxide area of 625µm 2 and a thickness of 3.2nm. Test conditions: V IN =2V, F=2.5KHz, D.C.=50%, and V DD =2V. For both the dual waveform and SICBB experiments, the type of degradation and/or breakdown mechanism of the device was determined by pre-and post-stress I-V tests. The test voltage was low enough to avoid further degradation of the oxide. All experiments were performed in a Faraday cage using an Agilent 4156C. We also report on degradation mechanisms in nMOSFETs and their effect on inverter operation. We show for the first time the effect of limited hard breakdown (LHBD) [1,2] on inverter operation.

Recent developments in high speed silicon bipolar device technologies are reviewed. Bipolar device structures that include polysilicon are key technologies for improving circuit characteristics. Double polysilicon bipolar device structures, in particular, have made it possible both to form shallow junctions and to reduce device dimensions. Recent progress of silicon bipolar transistor technology using SiGe and the use of the SO1 technology to obtain high speed operations are also reviewed.

Enhancement-mode Si/SiGe electron quantum dots have been pursued extensively by many groups for their potential in quantum computing. Most of the reported dot designs utilize multiple metal-gate layers and use Si/SiGe heterostructures with Ge concentration close to 30%. Here we report the fabrication and low-temperature characterization of quantum dots in Si/Si 0.8 Ge 0.2 heterostructures using only one metal-gate layer. We find that the threshold voltage of a channel narrower than 1 µm increases as the width decreases. The higher threshold can be attributed to the combination of quantum confinement and disorder. We also find that the lower Ge ratio used here leads to a narrower operational gate bias range. The higher threshold combined with the limited gate bias range constrains the device design of lithographic quantum dots. We incorporate such considerations in our device design and demonstrate a quantum dot that can be tuned from a single dot to a double dot. The device uses only a single metal-gate layer, greatly simplifying device design and fabrication.

SiGe alloys are currently used for HBT and MOS as epitaxial layers for base or strained channel, respectively. In the poly phase, SiGe has been studied as a replacement for poly-Si in MOS gates due to its lower thermal budget and gate depletion and also due to the Workfunction Engineering for V t adjustments. However, for application to CMOS technology as poly-SiGe gates, others constrains emerge such as quality of the oxide interface and etch chemistry. For both applications, the Ge fraction normally lies between 20% and 40%. In this study, authors use a low Ge contents (1%) poly-SiGe thin films aiming for MOS gate electrode. The Ge fraction was determined by RBS analysis. 230 nm thick samples were deposited onto 10 nm thermally oxidized h1 0 0i, p-type Si substrates using silane and germane. Films were deposited in the temperature of 500 °C and total pressure of 667 Pa (5 Torr) by vertical LPCVD. The samples were doped using 31 P + ion implantation from 5 • 10 14 cm À2 up to 2 • 10 16 cm À2 and annealed by RTP (40 s) from 500 °C up to 900 °C. R s values were obtained by 4-point probe technique and CV curves were extracted from nMOS capacitors with 200 lm diameter. The same processing steps were used to fabricate similar poly-Si samples and capacitors for comparison. The poly-SiGe samples presented R s values one order of magnitude lower than poly-Si and CV analysis of nMOS capacitors showed very good characteristics. The 1% Ge in the alloy ensures a low thermal budget for the overall process. Although a relatively high annealing temperature (800 °C) must be used to reduce oxide charge and interface traps, the temperature is well below the necessary for poly-Si processing and can allow formation of the shallow junctions needed for next technological nodes.

Carrier transport in modern nanoelectronic devices involves physical scales which require quantum descriptions. Basic quantum mechanics describes systems determined by Hamiltonian state vectors |Ψ>, which provide the spatial and time dependences of the physical observables. A pure state density operator |Ψ><Ψ| as obtained by a single state vector contains the most complete information about the spatial correlations in the system. Mixed states are introduced as linear combinations of pure states with assigned probability distributions, reflecting the fact that the knowledge of the system is incomplete as a result of interactions with other systems. This is the case for carrier transport through open systems, such as nanodevices exchanging carriers through their contacts. The carrier system is maintained in a mixed state by a competition of quantum-coherent processes of interference and correlations with processes of decoherence caused by the environment (e.g. photon/phonon i...

We present the motivation for mixed-mode device and circuit simulation. The possible approaches are discussed and the particular methods of the multi-dimensional device/circuit simulator MINIMOS-NT are presented. The available capabilities are demonstrated on a Colpitts oscillator and two intermediate circuits, which are matter of transient and small-signal ac simulations. Advances in the development of semiconductor devices have lead to more and more sophisticated device structures. This concerns device geometry as well as doping profiles and the combination of different materials. Due to shrinking device geometries, the models describing the device physics increase in complexity. Traditional device simulation has considered the behavior of isolated devices under artificial boundary conditions (single-mode). To gain additional insight into the performance of devices under realistic dynamic boundary conditions imposed by a circuit, mixed-mode simulations have proven to be invaluable. However, this problem is very complex and only limited solutions have been available so far. The main advantages of mixed-mode simulations are: • A calibrated device simulator can be directly employed for circuit simulations: No subsequent and often expensive parameter/model extraction is necessary. Thus, in time-to-market considerations results of many different devices are available at significantly earlier times. • It is common practice to create optimization loops consisting of process and device simulators. Controlled by various kinds of optimizers, device figures of merit (e.g., cut-off frequency f t ) trigger process variations in order to be improved. By switching the device simulator in the mixed-mode, also circuit figures of merit can be optimization targets. The major drawback in comparison to compact model approaches is the significant performance difference, since much larger equation systems have to be assembled and solved.

Increased use of wireless technologies for communications and sensing results in spectral overcrowding in the lower GHz range. Spectrum allocations in the upper microwave and in the millimeter-wave ranges are available, yet realizing low-cost circuits, e.g. for the 24 GHz ISM band remains a challenge. We are investigating the use of two Si/SiGe hetero-junction bipolar transistor technologies at Atmel Germany (the commercially available SiGe1 and the emerging SiGe2 processes), combined with compact circuit design and back-end micromachining techniques, for the realization of cost-efficient RF frontend solutions at frequencies above 20 GHz. Results presented here include a fully monolithic receiver IC for 24 GHz, and a 33 GHz oscillator module combined with a thin-film antenna structure using wafer-level integration.

In this paper, we investigate a new reliability damage mechanism in SiGe Heterojunction Bipolar transistor (HBTs).This study differs from conventional HBT/SiGe device reliability associated with other stress. Since it results from an Electromagnetic field aggression which consists of a new stress methodology. The near-field bench is used to disturb with electromagnetic field the Device Under test (DUT) on a localized area, contrary to the disturbance created in the TEM cell. We find that only the base is most sensitive to the disturbance caused, when compared to those on the package, collector and emitter. This is primarily due to the electromagnetic coupling phenomenon between the induced electromagnetic field and the microstrip line connecting the base of the transistor. Degradations in the base current and the current gain are identified. It is induced by a large I B leakage current due to hot carrier which introduces generation/recombination center traps and leads to excess non-...

The voltage transfer characteristics (VTC) of a complementary metal-oxide-semiconductor (CMOS) inverter provides necessary information about some of the most important performance parameters, such as noise margin (low/high), inverter logic threshold voltage, and so on. Over years, there has been an increasing trend to use various commercially available Technology Computer Aided Design (TCAD) tools and circuit simulators to study such performance parameters. The emergence of novel devices has forced the theoretical research community to refine TCAD tools and simulators. We have developed a simulator that can plot the VTC curve of strained/unstrained nanoscale MOSFET based CMOS circuits. Our algorithm can faithfully reproduce the VTC curve of nanoscale MOSFET based CMOS inverter with an average deviation of less than 2%. We have also shown the dependence of VTC curves of nanoscale strained Si/SiGe and multi channel (MC)gate-all-around (GAA) MOSFET based CMOS inverters on some important device parameters.

Owing to the persisting technological importance of Strained-Si (S-Si) metal-oxide-semiconductor fieldeffect transistors (MOSFETs) and the hurdles offered by source (S) and drain (D) series resistances in the nanometer regime, a simulator has been developed for evaluating the voltage transfer characteristics (VTC) and analyzing some performance parameters of such devices-based CMOS inverters. The algorithms used for framing the simulator are based on analytical equations which can accurately estimate the noise margin (NM), dynamic current, and so on. The effects of strain on the circuit performance have also been investigated, with emphasis on the variations of drain current dependent transconductance ratio. A scope of using high-k dielectric materials along with strain is also explored. The algorithms proposed in this work are not only restricted to strained-Si MOSFETs but can also be applied to any novel device structure and complex digital logics, presented as case studies.

A nontraditional fabrication technique is used to produce quantum dots with read-out channels in silicon/silicon–germanium two-dimensional electron gases. The technique utilizes Schottky gates, placed on the sides of a shallow etched quantum dot, to control the electronic transport process. An adjacent quantum point contact gate is integrated to the side gates to define a read-out channel, and thus allow for noninvasive detection of the electronic occupation of the quantum dot. Reproducible and stable Coulomb oscillations and the corresponding jumps in the read-out channel resistance are observed at low temperatures. The fabricated dot combined with the read-out channel represents a step toward the spin-based quantum bit in Si∕SiGe heterostructures.

In this paper, we studied the roughening of SiGeC surface revealed by in situ reflection high energy electron diffraction (RHEED) measurements, that happens during ultra-high vacuum chemical vapor deposition (UHV-CVD) growth under certain growth conditions. A high growth rate and a low temperature are found to be favorable for smooth surfaces. Roughening is accompanied by a dramatic decrease of the substitutional C content and, further, stacking faults develop within the epilayer. According to these observations, we proposed a model of surface roughening based on the formation of carboneous complexes on the film surface and a way to maximize substitutional C incorporation in very thin layers by using RHEED as a probe for monitoring the development of lattice defects. By this means, more than 2% of substitutional C atoms can be incorporated in 5 nm Si 1Ày C y films (assuming Vegard's law).

Packard Laboratories -The efficiency of thermoelectric devices can be enhanced by increasing electrical conductivity and lowering thermal conductivity. Semiconductor nanostructures, whose electrical and thermal conductivities could be optimized by changing their electronic and structural properties, are ideal candidates for such device applications. However, complete understanding of their device properties and limitations requires a technique allowing temperature measurements with a nanoscale spatial resolution. In this work, we studied the thermal conductivities of two groups of Si/Ge nanostructures: Si/SiGe multilayer samples prepared by molecular beam epitaxy, and Si/Ge nanowire heterojunctions prepared by chemical vapor deposition based vapor-solid-liquid process. Sample temperatures during irradiation by a laser beam were measured using Stokes and Anti-Stokes modes of Raman scattering of different vibration modes, and thermal conductivity was calculated by using the temperature gradient between different parts of SiGe nanostructures. We find clear correlations between samples' structural properties and their thermal conductivity. This work suggests a novel approach toward high-efficiency Si/SiGe nanostructure-based thermoelectric generators.

A nontraditional fabrication technique is used to produce quantum dots with read-out channels in silicon/silicon–germanium two-dimensional electron gases. The technique utilizes Schottky gates, placed on the sides of a shallow etched quantum dot, to control the electronic transport process. An adjacent quantum point contact gate is integrated to the side gates to define a read-out channel, and thus allow for noninvasive detection of the electronic occupation of the quantum dot. Reproducible and stable Coulomb oscillations and the corresponding jumps in the read-out channel resistance are observed at low temperatures. The fabricated dot combined with the read-out channel represents a step toward the spin-based quantum bit in Si∕SiGe heterostructures.

There is a well recognised need to introduce new materials and device architectures to Si technology to achieve the objectives set by the international roadmap. This paper summarises our work in two areas: vertical MOSFETs, which can allow increased current drive per unit area of Si chip and SiGe HBT's in silicon-on-insulator technology, which bring together and promise to extend the very high frequency performance of SiGe HBT's with SOI-CMOS.

This paper presents a general study on the germanium (Ge) condensation technique to assess its potential, issues and applications for advanced metal oxide semiconductor field effect transistor (MOSFET) technologies. The interest in such process for fabrication of ultrathin germanium on insulator (GeOI) layers for fully depleted GeOI MOSFETs application is first described. We highlight the impact of initial silicon on insulator (SOI) substrates uniformity on the process, determined as the key parameter to be improved. Next, a global procedure is described for MOSFETs integration on Ge layers grown on 75% Ge-enriched silicon germanium on insulator (SGOI) substrates obtained by the Ge condensation technique. A third section reviews the different local Ge condensation techniques for fabrication of SOI-GeOI hybrid substrates. Interests of such substrates for SOI-GeOI planar co-integration either at the microprocessor, at the cell or at the transistor level will be discussed. Finally, the fabrication of a first 50-nm-thick SOI-GeOI hybrid substrate is described.

: We are investigating the use of Raman spectroscopy of tin as an analytical tool for discerning specific allotropic differences in ultra-thin tin films, and discerning differences between the tin and the growth substrates of interest. We have acquired spectra from barium difluoride (BaF2), crystalline silicon dioxide (SiO2), as well as ultra-thin tin semiconductor and tin metallic allotropes, and we are developing a fundamental understanding of the spectra. The research has identified that BaF2 is an excellent passivation layer for two-dimensional tin (stanene) that will enhance the resolution of the Raman spectrum of future tin layers and facilitate the molecular beam epitaxy (MBE) growth of stanene.

A nontraditional fabrication technique is used to produce quantum dots with read-out channels in silicon/silicon–germanium two-dimensional electron gases. The technique utilizes Schottky gates, placed on the sides of a shallow etched quantum dot, to control the electronic transport process. An adjacent quantum point contact gate is integrated to the side gates to define a read-out channel, and thus allow for noninvasive detection of the electronic occupation of the quantum dot. Reproducible and stable Coulomb oscillations and the corresponding jumps in the read-out channel resistance are observed at low temperatures. The fabricated dot combined with the read-out channel represents a step toward the spin-based quantum bit in Si∕SiGe heterostructures.

A highly efficient push-push voltage controlled oscillator (VCO) with a new varactor-less-based frequencytuning topology for terahertz (THz) frequencies is presented. The tuning technique is based on a variable inductance seen at the emitter node of a base degenerated transistor. Fabricated in a 130nm SiGe BiCMOS process, the VCO achieves a tuning range of 3.5% and output power of ----7.2 dBm at 201.5GHz. The VCO consumes 30mW of DC power, resulting in a record-breaking power efficiency of 0.6%. To demonstrate the functionality of the tuning technique, three other VCO prototypes at different oscillation frequencies, including one operating at 222.7~229 GHz range, have been implemented.

We present, for the first time, an analysis of the error signatures captured during pulsed laser microprobe testing of high-speed digital SiGe logic circuits. 127-bit shift registers, configured using various circuit level latch hardening schemes and incorporated into the circuit for radiation effects self test serve as the primary test vehicle. Our results indicate significant variations in the observed upset rate as a function of strike location and latch architecture. Error information gathered on the sensitive transistor nodes within the latches and characteristic upset durations agree well with recently reported heavy-ion microprobe data. These results support the growing credibility in using pulsed laser testing as a lower-cost alternative to heavy-ion microprobe analysis of sensitive device and circuit nodes, as well as demonstrate the efficiency of the autonomous detection and error approach for high speed bit-error rate testing. Implications for SEU hardening in SiGe are addressed and circuit-level and device-level Radiation Hardening By Design recommendations are made. Index Terms-Built-in self-test, circuit level hardening, highspeed bit-error rate testing, pulsed laser testing, silicon-germanium (SiGe), single-event effects (SEU). I. INTRODUCTION S ILICON-GERMANIUM HBT technology continues to make in-roads into the extreme environment electronics market. Recently reported results on the most aggressively scaled SiGe technologies include excellent low temperature performance [1] and inherent tolerance to multi-Mrad (SiO ) levels of ionizing dose [2]. These attributes, coupled with its seamless integration with best-of-breed CMOS to form SiGe Manuscript received August 25, 2006.

Product designs for 40-Gb/s applications fabricated from SiGe BiCMOS technologies are now becoming available. This paper will first briefly discuss heterojunction bipolar transistor (HBT) device operation at high speed, demonstrating that perceived concerns regarding lower CE0 and higher current densities required to operate silicon HBTs at such high speeds do not in actuality limit design or performance. The high-speed portions of the 40-Gb/s system are then addressed individually. We demonstrate the digital capability through a 4 : 1 multiplexer and a 1 : 4 demultiplexer running over 50 Gb/s error free at a 3.3-V power supply. We also demonstrate a range of analog elements, including a lumped limiting amplifier which operates with a 35-GHz bandwidth, a transimpedance amplifier with 220gain and 49.1-GHz bandwidth, a 21.5-GHz voltage-controlled oscillator with over 100-dBc/Hz phase noise at 1-MHz offset, and a modulator driver which runs a voltage swing twice the CE0 of the high-speed SiGe HBT. These parts demonstrate substantial results toward product offerings, on each of the critical high-speed elements of the 40-Gb/s system.

Phase diagrams have been studied to describe the RF PECVD process for intrinsic-hydrogenated silicon Si:H and silicon-low germanium alloy a-Si 1Àx Ge x :H thin films using textured Al substrates that have been overdeposited with n-type amorphous Si:H (n + a-Si:H). UV, vis, IR, atomic force microscopy (AFM), Raman spectroscopy, small angle X-ray and cross-section transmission electron microscopy (TEM) are used to establish the phase diagram. The a-Si:H, a-Si 1Àx Ge x and mc-Si:H processes are applied for optimization of triple-junction thin silicon-based n-i-p solar cells.

In this letter we not only show improvement in the performance but also in the reliability of 30nm thick biaxially strained SiGe (20%Ge) channel on Si p-MOSFETs. Compared to Si channel, strained SiGe channel allows larger hole mobility (µ h ) in the transport direction and alleviates charge flow towards the gate oxide. µ h enhancement by 40% in SiGe and 100% in Si-cap SiGe is observed compared to the Si hole universal mobility. A ~40% reduction in NBTI degradation, gate leakage and flicker noise (1/f) is observed which is attributed to a 4% increase in the hole-oxide barrier height (φ) in SiGe. Similar field acceleration factor (Γ) for threshold voltage shift (ΔV T ) and increase in noise (ΔS VG ) in Si and SiGe suggests identical degradation mechanisms.

This paper describes the design and characteristics of a highly efficient multilayer parasitic microstrip antenna array (MPMAA) constructed on a multilayer substrate for millimeter-wave system-on-package modules. The antenna on a Teflon substrate achieved a radiation efficiency of greater than 91% and an associated antenna gain of 11.1 dBi at 60 GHz. Its size is only 10 mm × 10 mm. We discuss MPMAAs fabricated on both Teflon and low-temperature cofired ceramic (LTCC) substrates. The measured performances of prototype antennas are also presented. The MPMAA offers compactness and high efficiency and is easily integrated with the system-on-package design. It will lead to compact and cost-effective millimeter-wave RF modules.

In this paper, we examine alternative methods for reducing the dimensionality of nonlinear dynamical system models arising in control of rapid thermal chemical vapor deposition (RTCVD) for semiconductor manufacturing. We focus on model reduction for the ordinary differential equation model describing heat transfer to, from, and within a semiconductor wafer in the RTCVD chamber. Two model reduction approaches are studied and compared: the proper orthogonal decomposition and the method of balancing. This leads to a discussion of computational issues in the practical implementation of balancing for nonlinear systems.

Three photodetector structures were simulated, fabricated and characterized at 850nm in a SiGe BiCMOS process. The measurement and simulation results suggest that with modest equalization, multi-Gb/s communication is achievable without any special device fabrication.

This paper details the effects of increasing the growth rate of hydrogenated amorphous silicon (a-Si:H), deposited by dc plasma chemical vapor deposition, on the structural and electronic properties of the material in comparison with the performance of solar cells incorporating such layers. The hydrogen content exhibits the strongest correlation with the solar cell efficiency. The defect density measured by two different techniques, correlate poorly but when measured by a third technique, correlates well. On the other hand, the Urbach tail slope correlated well when measured by two different techniques but poorly when measured by a third one.

Mobilities and relaxation times are the fundamental parameters of macroscopic transport models. They are determined by the scattering integral of Boltzmann's equation and thus depend on the shape of the distribution function. They are normally modeled in an empirical way because knowledge of the distribution function is difficult to obtain. Based on an analytic expression for the distribution function which exactly reproduces its first six moments we present models for these parameters which are highly accurate even for nanometer devices. We show that this accuracy cannot be obtained within the conventional heated and shifted Maxwellian approximation.

We present a reliable technique to model the influence of DC current-crowding in bipolar transistors on the variation of emitter width (W E,ef ) as a function of collector current density (J C ) in silicon-germanium-carbon heterojunction bipolar transistors (SiGe:C HBTs). This method avoids using geometrical assumptions that may be invalid for highly scaled devices. We point out that according to the scientific literature consulted, this is the first time that the evolution of W E,ef with J C extracted from measurements of S-parameters, high frequency noise and small-signal electric modelling is reported for a bipolar transistor technology (homojunction or heterojunction). The investigated SiGe:C HBTs have eight different base layer configurations, varying in base doping level and Ge content. The results show that W E,ef decreases with J C for all devices. This behaviour is directly linked to the current-crowding effect. The procedure was used to identify the base configuration layer from the batch of eight SiGe:C HBTs that minimized current-crowding. This method could be applied to state-of-the-art SiGe:C HBTs to determine the base layer technological configuration that mitigates current-crowding and improves the reliability of SiGe:C HBTs. Finally, knowledge of the effective emitter width as a function of bias opens the road to thoroughly analyse the self-heating impact on ultra-fast SiGe:C HBTs.

The present contribution introduces theoretical studies of photonic crystals. On the basis of Maxwell's equations and a `plane wave expansion' band structures and densities of states are computed for triangular and square 2D lattices of air columns in silicon. The main topic of the paper are investigations of band gap modifications (TM-and TE-polarization) for pores of deteriorating roundness, approximated by ellipses of varying eccentricity. The presented computations include the consideration of background structures in the form of stripes (SiO 2 ) in the model. The results are compared with calculations for circular air columns of varying filling factors. Im vorliegenden Beitrag werden theoretische Untersuchungen zu photonischen Kristallen vorgestellt. Auf der Grundlage der Maxwellschen Gleichungen und einer `ebenen Wellen Entwicklung' werden fu È r triangulare und quadratische 2D Gitter Bandstrukturen und Zustandsdichten berechnet. Schwerpunkt der Publikation bilden Untersuchungen zu Vera È nderungen der Bandlu È cken (TM-und TE-Polarisation), wenn die Poren in Silizium nicht mehr exakt rund sind, sondern durch Ellipsen mit variabler Exzentrizita È t gena È hert werden. Die vorgestellten Berechnungen erlauben zusa È tzlich, streifenfo È rmige Hintergrundstrukturen (SiO 2 ) in den Modellen zu beru È cksichtigen. Die Ergebnisse werden mit Rechnungen fu È r kreisfo È rmige Luftsa È ulen bei variablem Fu È llfaktor verglichen.

In December 1996, a project was initiated at the Institute for Systems Research (ISR), under an agreement between Northrop Grumman Electronic Sensors and Systems Division (ESSD) and the ISR, to investigate the epitaxial growth of silicon-germanium (Si-Ge) heterostructures in a commercial rapid thermal chemical vapor deposition (RTCVD) reactor. This report provides a detailed account of the objectives and results of work done on this project as of September 1997. The report covers two main topics -modeling and model reduction. Physics-based models are developed for thermal, fluid, and chemical mechanisms involved in epitaxial growth. Experimental work for model validation and determination of growth parameters is described. Due to the complexity and high computational demands of the models, we investigate the use of model reduction techniques to reduce the model complexity, leading to faster simulation and facilitating the use of standard control and optimization strategies. Some of the contents of this report are contained in .

In this work, the source structure of an n-type thin-film tunneling FET is engineered to get better performance. An ultra-thin SiGe along with Si is used in the source of silicon-based TFET. Two structures are compared with conventional TFET, one, SiGe is located on the top of Si in the source and another one in reverse. Simulations approve these structures can reduce sub-threshold swing, OFF-current several times, and increase the ON-OFF ratio. Band diagram for conduction and valance bands are investigated and band to band tunneling (BTBT) generation rate is used to find better performance. We find current flows at Si in the source with the wider bandgap. Ge mole fraction of SiGe is varied and its effects on the performance of TFET are studied. The SiGe thickness for both structures is explored to obtain the best thickness for SiGe.

This is the first report of a Si/SiGe resonant interband tunneling diodes (RITDs) on silicon substrates grown by the chemical vapor deposition process. The nominal RITD structure forms two quantum wells created by sharp δ-doping planes which provide for a resonant tunneling condition through the intrinsic spacer. The vapor phase doping technique was used to achieve abrupt degenerate doping profiles at higher substrate temperatures than previous reports using low-temperature molecular beam epitaxy, and postgrowth annealing experiments are suggestive that fewer point defects are incorporated, as a result. The as-grown RITD samples without postgrowth thermal annealing show negative differential resistance with a recorded peak-to-valley current ratio up to 1.85 with a corresponding peak current density of 0.1 kA/cm 2 at room temperature.

The aim at enhancing the performance of solar cells, detectors and microelectronic devices through band gap engineering caused an increasing attention in processes for growing thin silicon germanium carbon (SiGeC) films in a wide range of composition, crystalline structure and surface roughness. The already obtained results evidence that such tailored thin film