Hardware/Software Co-Design

Artificial Intelligence (AI) is redefining the boundaries of web development by automating complex tasks, enhancing user experience, and reshaping how developers design and deploy web applications. This article examines the convergence of AI technologies and web development practices, with a focus on the transformative role of Large Language Models (LLMs), user interface generation, automated software engineering, and humancentered prototyping approaches. By referencing recent scientific and peer-reviewed studies, the paper presents original observations about AI's impact on software engineering, analyzes common issues and ethical concerns in using AI, and considers why end-users and smart devices are changing their methods of interaction. There is a particular focus on LLMs being able to help generate websites, the use of a dual-hemisphere approach to UI planning, and the effects of AI on making development projects faster and better. Critical analysis in this study shows that AI is involved in shaping the future of web development, more than just supporting it.

Members of my family who understood my busy days. In particular, my wife and my parents. The Professors Ricardo Rabelo, Antonio Loureiro, Bruce Thomas and Mark Billinghurst for having patience with me and give me directions to conclude this work. The colleagues who spent some precious time and weekends contributing to the development. In particular, Thiago D'Angelo. To my friends who made my adaptation in Australia easier. There are too many people to cite here... All persons who imposed barriers and make this work harder. I became stronger learning with you. There are too many people to cite here...

Healthcare systems face mounting pressures to deliver high-quality, safe, and efficient services in increasingly complex clinical environments. Rising patient expectations, resource constraints, and the growing burden of chronic disease underscore the need for frameworks that not only improve performance but also sustain long-term impact. Traditional models of service delivery, often episodic and compliance-oriented, have proven insufficient for addressing systemic inefficiencies and patient safety concerns. Against this backdrop, continuous quality improvement (CQI) has emerged as a cornerstone of transformation, enabling healthcare organizations to pursue incremental and sustained enhancements in care delivery. CQI-driven innovation integrates data monitoring, feedback loops, and evidence-based practices into everyday workflows, allowing clinical teams to identify inefficiencies, test interventions, and scale successful models. This approach fosters a culture of accountability by linking outcomes to shared goals and transparent performance metrics, ensuring that staff at all levels remain invested in delivering measurable improvements. At the same time, CQI emphasizes collaboration across disciplines, recognizing that complex health challenges demand teamwork among physicians, nurses, administrators, and allied professionals. By aligning innovation, accountability, and interdisciplinary cooperation, CQI not only improves clinical outcomes but also strengthens organizational resilience, adaptability, and patient trust. This paper argues that CQI-driven approaches provide a practical and sustainable pathway for reengineering healthcare delivery. By embedding innovation into service delivery systems and fostering shared accountability across teams, healthcare institutions can achieve meaningful and lasting transformation in quality, safety, and patient-centered care.

Efficient shortest-path computation in weighted graphs is essential in domains like networking and logistics. Dijkstra's algorithm depends heavily on the choice of priority queue, and while theoretical complexities are well-documented, their real-world performance varies. This study compares three priority queue implementations-Binary Heap, Fibonacci Heap, and Binomial Heap-within Dijkstra's algorithm using road network data from Zenodo (https://doi.org/10.5281/zenodo.1290209). The dataset was preprocessed, normalized, and converted into a usable format using MATLAB (R2024b). Theoretical time complexities for core operations-insert, decrease-key, and extract-min-were analyzed. Experiments conducted on synthetically generated graphs showed Binary Heap achieved the fastest execution time (0.00126s) and highest throughput (3313 edges/sec), outperforming Fibonacci and Binomial Heaps. Results indicate that Binary Heap is the optimal choice for execution speed and throughput, especially for large or dense graphs. The findings provide practical guidance for selecting priority queues in real-world shortest-path applications and contribute to the empirical evaluation of data structures in algorithm design.

Este artigo examina o uso da computação generativa em projetos de identidades visuais, analisando animações de marcas gráficas geradas por algoritmos computacionais. Os conceitos de tempo e movimento apresentados por Lupton e Phillips (2008) fundamentaram a elaboração de um modelo de análise visual de movimento, apoiado em compilações de sequências de imagens capturadas. Com isso, foi possível identificar as variações presentes nos quadros das animações, observando semelhanças e diferenças nas marcas gráficas de seis projetos selecionados. O modelo de análise forneceu uma base para compreensão das técnicas visuais exploradas pelas animações, e serviu também como uma ferramenta para auxiliar o entendimento de como a tecnologia computacional está sendo explorada em projetos de identidade visual.

In conventional vehicle conversion of kinetic energy into heat and unused emission during friction braking is wasted into the Environment in the form of heat, electrical motors used by hybrid and electric vehicles is used to recover some portion of the Kinetic energy which can be reused. We have accomplished a model on Regenerative Braking integrated with Solar Hybrid system in which the battery gets charged by Regenerative braking as well as with Solar energy with the help of PIC 18F4550 andLCD16X2(JHD162A) application and correspondingly Power generated can be calculated.

In this paper a co-design methodology based on multifonnalism modelling is presented. It defines a platfonn that integrates different notations and, the necessary mechanisms to handle different in nature models in a coherent way. The supported fonnalisms cover a wide area of application domains, allowing the designer to select the notations that are mostly appropriate for his/her application. The proposed co-design development cycle provides a full blown path from system specification to a virtual prototype of the system under construction. The methodology has been applied for the design and implementation of a MAC layer protocol, named MASCARA, for providing A TM QoS over wireless connections.

This paper presents a hardware/software co-design approach where different specification languages can be used in parallel, allowing effective system co-modeling. The proposed methodology introduces a process model that extends the traditional spiral model so as to reflect the design needs of modern embedded systems. The methodology is supported by an advanced toolset that allows co-modeling and co-simulation using SDL, Statecharts and MATRIX X , and interactive hardware/software partitioning. The effectiveness of the proposed approach is exhibited through two application examples: the design of a car window lift mechanism, and the design of a MAC layer protocol for wireless ATM networks.

Technological advances of Field Programmable Gate Array (FPGA) are making that this technology becomes the most preferred platform for the rapid prototyping of highly integrated digital systems. In addition, protection of processor-based systems to mitigate the harmful effects of radiation-induced upset events is gaining importance while technology shrinks. In this context, the main contribution of this work is a novel rapid prototyping approach for the codesign of dependable embedded systems using FPGA. This is supported by a hardening platform that allows combining software-only fault-tolerance techniques with hardware-only approaches, representing several trade-offs among design constraints, reliability and cost. As case study, several radiationtolerant embedded systems have been developed based on a technology-independent version of the Picoblaze processor.

This paper presents a hardware/software co-design approach where different specification languages can be used in parallel, allowing effective system co-modeling. The proposed methodology introduces a process model that extends the traditional spiral model so as to reflect the design needs of modern embedded systems. The methodology is supported by an advanced toolset that allows co-modeling and co-simulation using SDL, Statecharts and MATRIX X , and interactive hardware/software partitioning. The effectiveness of the proposed approach is exhibited through two application examples: the design of a car window lift mechanism, and the design of a MAC layer protocol for wireless ATM networks.

This work investigates the use of reconfigurable devices as computing platform for self-organizing embedded systems. Those usually consist of a set of distributed, autonomous nodes interacting with each other in order to solve a given problem. Several aspects of hardware-software co-design as well as partial reconfiguration are presented in order to enforce adaptivity of a node. One targeted application field for this kind of system are sensor networks in which reconfigurable devices, in this case FPGAs, can be used as computation nodes to provide services that require more computation power. To manage the available hardware resources as a whole we suggest a market-economy-like system of supply and demand. Requests, built up out of several tasks, can be posed to the collective. The goal is to gain a system able to perform simple tasks as well as very complex computations, while keeping the overall energy consumption low. This will be achieved by deploying highly specialized hardware accelerators and a reasonable resource management. First results show the viability of the methods in the distributed management of available resources.

This work investigates the use of reconfigurable devices as computing platform for self-organizing embedded systems. Those usually consist of a set of distributed, autonomous nodes interacting with each other in order to solve a given problem. Several aspects of hardware-software co-design as well as partial reconfiguration are presented in order to enforce adaptivity of a node. One targeted application field for this kind of system are sensor networks in which reconfigurable devices, in this case FPGAs, can be used as computation nodes to provide services that require more computation power. To manage the available hardware resources as a whole we suggest a market-economy-like system of supply and demand. Requests, built up out of several tasks, can be posed to the collective. The goal is to gain a system able to perform simple tasks as well as very complex computations, while keeping the overall energy consumption low. This will be achieved by deploying highly specialized hardware accelerators and a reasonable resource management. First results show the viability of the methods in the distributed management of available resources.

A two-unit PLC system is analysed with two different situations resulting in to two models. In first model two identical units are used in hot standby and no priority regarding operation/ repair is set for any of the units. While in the other model two units are used in hot standby on master-slave basis. The slave unit can also fail but generally its failure rate is lower than that of the master unit. Priority is given to the repair of minor fault over the major fault. In other cases of failure, priority for repair is given to the master unit. Also, priority for operation is given to the master unit. For various measures of system effectiveness the expressions are obtained and a comparative study of both the models is done for the profit with respect to various parameters followed by the conclusion.

A two-unit PLC system is analysed with two different situations resulting in to two models. In first model two identical units are used in hot standby and no priority regarding operation/ repair is set for any of the units. While in the other model two units are used in hot standby on master-slave basis. The slave unit can also fail but generally its failure rate is lower than that of the master unit. Priority is given to the repair of minor fault over the major fault. In other cases of failure, priority for repair is given to the master unit. Also, priority for operation is given to the master unit. For various measures of system effectiveness the expressions are obtained and a comparative study of both the models is done for the profit with respect to various parameters followed by the conclusion.

A well-defined system-level model contains explicit parallelism and should be free from parallel access conflicts to shared variables. However, safe parallelism is difficult to achieve since risky shared variables are often hidden deep in the design and are not exposed through simulation. In this paper, we propose a new static analysis approach based on segment graphs that identifies a tight set of potential access conflicts in segments that may-happen-in-parallel (MHP). Our experimental results show that the analysis is complete, accurate and fast to reveal dangerous shared variables in several embedded application models. Compared to earlier work, our approach significantly reduces the number of false conflict reports and thus saves the designer time.

We describe a method for verifying hardware whose correct behavior depends upon its software interface. It is presumed that the hardware i s p r esented as a synchronous RTL model whereas the software i s p r esented as an asynchronous abstraction. Our methodology incorporates partial order reduction on the software side, and localization reduction, to deal with the computational complexity of the veri cation. The partial order reduction is implemented a s a c onstraint on the transition relation of a synchronous transformation of the software m o del. The reduced t r ansformed m o del then may be veri ed using a veri cation algorithm whose scope is purely synchronous models, without modi cation. Thus, independent of the interface veri cation problem, this gives a general method for combining partial order reduction with symbolic model-checking.

This research has as main objective to show in a general way the FPGA technology, Field Programmable Gate Array-Arrangement of programmable Gates on the Chip. We will talk here about its architecture, manufacturing companies, description of a simple circuit using VHDL, Very High Speed Hardware Description Language, Quartus II Software and the INTEL Cyclone II card. A simple combinational logic circuit was used to carry out the simulation with the Quartus II software. Leaving everything clearly indicated to carry out larger projects. The results of the study show that the graphs obtained as a response of the circuit studied were as expected, and also that the properties of the software under study could be verified. The general characteristics of the FPGA technology were studied. The basic functions of the Quartus II software were known to execute a project in all its phases. This is a basic project. In the future there are projects that work with sequential logic and with other tools such as the ISP Lever software from the LATTICE Semiconductor company, which allows, using only software, to develop FPGA projects. In other words, this research serves as the basis for larger-scale projects.

Simultaneous localization and mapping (SLAM) has been highly studied in the last decade. It allows the estimation of the camera pose of a mobile device and the creation of a map of the surrounding environment concurrently. Recently, Visual SLAM (VSLAM) has become the most widely used state-of-the-art technique to implement SLAM tasks due to its reduced cost, lower size, and affordability. However, the intensive computation of VSLAM systems does not fit in a wide range of limited resources and energy mobile devices. A possible solution is to split its functionality between mobile devices and the edge cloud. This solution showed the necessity for efficient visual data compression methods to be integrated within VSLAM systems. This work proposes a multi-level encoding method for visual data frame compression integrated within the monocular Oriented FAST and Rotated BRIEF-SLAM (ORB-SLAM) system. The performance results of the proposed system are compared to corresponding ORB-SLAM systems adopting the most popular classical still image compression standards; the Joint Photographic Experts Group (JPEG) and the advanced version, the JPEG 2000, in terms of reconstruction quality, robot's trajectory estimation, and computational complexity.

A number of techniques and software tools for embedded system design have been recently proposed. However, the current practice in the designer community is heavily based on manual techniques and on past experience rather than on a rigorous approach to design. To advance the state of the art it is important to address a number of relevant design problems and solve them to demonstrate the power of the new approaches. We chose an industrial example in automotive electronics to validate our design methodology: an existing commercially available Engine Control Unit. We discuss in detail the specification, the implementation philosophy, and the architectural trade-off analysis. We analyze the results obtained with our approach and compare them with the existing design underlining the advantages offered by a systematic approach to embedded system design in terms of performance and design time.

The area of software verification has grown its importance in software engineering. This is a bibliography of verification of a specialized class of softwares called compiler. The citations are sorted year wise in chronological order with most recent years first. The format of each citation is authors; Title; publisher; year. 2003

Specialized hardware accelerators designed by artificial intelligence (AI) technology developers improve the performance rate of machine learning operations as AI speeds forward rapidly. The three key components of these AI accelerators are Graphics Processing Units (GPUs) together with Tensor Processing Units (TPUs) and Field-Programmable Gate Arrays (FPGAs) whose primary role is to perform efficient processing of large datasets and execute complex algorithms. AI system complexities create significant problems for validating and maintaining correct functionality and reliable performance. The paper explores dedicated AI accelerator verification approaches to explain system-specific verification requirements for these specialized devices.

AI accelerator verification is vital because of its complex structures and precise computational demands. The verification methods based on simulation and formal techniques fail to operate effectively for AI-specific hardware because AI algorithms demonstrate non-deterministic properties and require testing under various operational parameters. Researchers explore novel verification methods that combine machine learning approaches with existing verification techniques because of the existing challenges. The new verification approaches increase the coverage of tests while finding critical corner situations and meeting performance standards, which leads to the creation of dependable AI hardware.
The verification process now needs to validate the combined performance of accelerators with other essential system components, including memory units and communication ports. A complete verification method must assess the system's functional behavior and performance characteristics. Engineers can achieve effective AI accelerator operation in their application environments using advanced verification tools, including constrained random testing and assertion-based verification. These verification techniques must be appropriately applied because they determine the deployment success rates of AI accelerators in critical use cases, including autonomous vehicles, healthcare, and real-time data processing systems.

Artificial intelligence and other emerging technologies have developed considerably which now profoundly affects how projects get managed. There is an analysis of how artificial intelligence drives innovation for project management which evaluates Agile versus Traditional approaches. Agile methodologies excel in iterative development therefore they efficiently integrate AI tools like predictive analytics and automation with machine learning technology to improve both decision-making capability and risk management as well as efficiency (Schmidt & Wagner 2022). Traditional project management stands in opposition to artificial intelligence implementation because of its fixed work processes but it shows signs of development through AI-implemented insights within structured frameworks (Turner et al., 2023). Time-sensitive data analysis and automated task distribution as well as adaptive resource management through AI methods enhance Agile approaches to Scrum and Kanban according to Lee and Chen (2021). Traditional Waterfall and other methodologies find it difficult to incorporate AI because they mainly use predictions but AI forecasting and risk assessment systems create opportunities to boost efficiency (Johnson, 2020). The study establishes that Agile frameworks combine AI adoption effectively due to their adaptive nature but Traditional methods need to restructure to use AI effectively. The research shows that AI matching approaches Agile practices through their ability to adapt while Traditional project management achieves enhancements by applying AI to strategic forecasting and process enhancement (Brown & Patel, 2022). Future projects should adopt combined management systems that unite systematic planning methods with AI capabilities for adaptation needs. Project managers must acquire digital competency combined with strategic visioning to harness AI potential within organizational structures for effective governance and performance (Martinez et al., 2023).

Because of their growing complexity, modern hardware systems require highly efficient verification methodologies for proper functionality examination and reliability assurance. The research examines Universal Verification Methodology (UVM) reference models that work to accelerate verification operations. We evaluate multiple models by analyzing their capabilities and faults and present operational suggestions so verification time shortens effectively without sacrificing fundamental testing criteria. Engineers who read this study can find guidance for critical reference model selection, leading to enhanced project productivity through high-quality results. This report analyzes three reference models: UVM testbench in traditional use, constrained random verification, and assertion-based verification. UVM testbench applications consume significant time because they require verbose configuration and extensive setup procedures. The constrained random verification system provides flexibility and efficiency for test generation, allowing users to create a more exhaustive scan of cases through minimal manual involvement. The verification process improves through assertion-based verification because engineers can perform immediate design behavior examinations through embedded check functionality. Different verification models contain distinct strengths, allowing projects to improve the verification cycle's efficiency when choosing the correct model based on individual project constraints and needs. The paper outlines how best practices and methodologies can be integrated to improve verification time efficiency within the UVM environment. The verification process benefits from reusable components combined with layered architecture and contains automation tools which automate verification procedures. According to our research, the application of reference model elements from multiple sources into a single framework leads to better system resource utilization and performance outcomes. Integrating constrained random techniques with assertion-based checks creates a verification environment that delivers maximized efficiency and reduced effort time. This work provides strategic recommendations for verification teams and engineers who must enhance workflow productivity through proper model distribution methods.

Artificial intelligence experiences fast growth through large language models (LLMs) which now shape hardware
design practice and verification systems. The research examines LLM technology in hardware engineering by showing
its potential benefits for design improvement, along with verification speedups and resolution of software development
and hardware design communication gaps. Hardware design operations benefit from LLMs, which improve
productivity while decreasing errors, and developing innovative hardware systems that improve hardware solutions'
efficiency.
Adopting large language models continues to expand to improve hardware design operations. Engineers can benefit
from LLM natural language processing characteristics, which help them produce design specs, circuit optimization,
and execute automated repetitive work. These models extract valuable information from enormous design databases,
enabling them to shape current engineering work. Large Language Models translate natural language design
specifications into technical specifications, thus saving engineers' initial drafting time. Collaboration in design teams
improves through LLMs because these models automatically generate instant recommendations and document
processes, leading to elevated creativity and productivity rates among team members.
Hardware development verification is vital because it ensures design systems operate according to their stated
requirements. Standard verification methods require extensive time and susceptibility to human mistakes. The
verification process becomes more efficient because LLMs handle several verification workflow tasks independently.
Testbench generation combined with hardware simulations leads LLMs to conduct verification result analysis for the
early detection of design issues during development. LMs can process verification documents with requirements to
help engineers generate detailed test cases that boost design validation effectiveness. The efficient operations shorten
product development duration and improve hardware product reliability.
Issues about communication gaps appear to be one of the main obstacles engineers experience when designing
hardware products between staff who build hardware and those who create software. The technical jargon becomes
more understandable through the help of LLMs because they provide translation services, which enhance
interdisciplinary collaboration. With their ability to provide better communication, LLMs enable engineering teams
to maintain identical understanding regarding project aims and specifications. LMCs contribute to complex hardware
documentation management and version control services, which usually make cooperative work difficult. Through
their role in enhancing communication between teams, LLMs produce better hardware project results and original
solutions.
Integrating large language models within hardware design and verification processes creates a transformative
advancement that improves productivity, verification effectiveness, and inter-team communication. The developing
technologies show a growing ability to change how hardware engineering functions. The development of LLM

Architecture and Implementation of adaptive NoC to improve performance and power consumption is presented. On platforms hosting multiple applications, hardware variations and unpredictable workloads make static design-time assignments highly sub-optimal e.g. in terms of power and performance. As a solution to this problem, adaptive NoCs are designed, which dynamically adapt towards optimal implementation. This paper addresses the architectural design of adaptive NoC, which is an essential step towards design automation. The architecture involves two levels of agents: a system level agent implemented in software on a dedicated general purpose processor and the local agents implemented as microcontrollers of each network node. The system agent issues specific instructions to perform monitoring and reconfiguration operations, while the local agents operate according to the commands from the system agent. To demonstrate the system architecture, best-effort power management with distribu...

Modern platform-based design involves the application-specific extension of embedded processors to fit customer requirements. To accomplish this task, the possibilities offered by recent custom/extensible processors for tuning their instruction set and microarchitecture to the applications of interest have to be exploited. A significant factor often determining the success of this process is the utomation available in application analysis and custom instruction generation. In this paper we present YARDstick, a design automation tool for custom processor development flows that focuses on generating and evaluating application-specific hardware extensions. YARDstick is a building block for ASIP development, integrating application analysis, custom instruction generation and selection with user-defined compiler intermediate representations. In a YARDstick-enabled environment, practical issues in traditional ASIP design are confronted efficiently; the exploration infrastructure is liberated from compiler and simulator idiosyncrasies, since the ASIP designer is empowered with the freedom of specifying the target architectures of choice and adding new implementations of analyses and custom instruction generation/selection methods. To illustrate the capabilities of the YARDstick approach, we present interesting exploration scenarios: quantifying the effect of machine-dependent compiler optimizations and the selection of the target architecture in terms of operation set and memory model on custom instruction generation/selection under different input/output constraints.

Traditional processors use the von Neumann execution model, some other processors in the past have used the dataflow execution model. A combination of von Neuman model and dataflow model is also tried in the past and the resultant model is referred as hybrid dataflow execution model. We describe a hybrid dataflow model known as the microthreading. It provides constructs for creation, synchronization and communication between threads in an intermediate language. The microthreading model is an abstract programming and machine model for many-core architecture. A particular instance of this model is named as the microthreaded architecture or the Microgrid. This architecture implements all the concurrency constructs of the microthreading model in the hardware with the management of these constructs in the hardware.

The EU Apple-CORE project 1 has explored the design and implementation of novel general-purpose many-core chips featuring hardware microthreading and hardware support for concurrency management. The introduction of the latter in the cores ISA has required simultaneous investigation into compilers and multiple layers of the software stack, including operating systems. The main challenge in such vertical approaches is the cost of implementing simultaneously a detailed simulation of new hardware components and a complete system platform suitable to run large software benchmaks. In this paper, we describe our use case and our solutions to this challenge.

This project presents the design and construction of a quality control machine for the hardware of Flip phones (Clamshell), for the wireless terminal evaluation management of Telefónica Venezuela, which is capable of automatically testing any phone of this model regardless of its dimensions. Through a keyboard it is possible to program the machine to perform complete movements of opening and closing the phones to the number of repetitions that the user wants. It also has a graphical interface where you can visualize the progress and results of the movement. This research is framed in the modality of feasible project, supported by field and descriptive research, applying for this purpose the knowledge acquired in terms of the management of microcontrollers, the available technological resources, the ideas of their own and of the people interested in carrying out the project.

Note: Special degree project originally completed in Spanish, but translated to broaden its audience reach

Embedded multiprocessor design presents challenges and opportunities that stem from task coarse granularity and the large number of inputs and outputs for each task. We have therefore designed a new architecture called embedded concurrent computing (ECC), which is implement on FPGA chip using VHDL. The performances of a realistic application show scalable speedups comparable to that of the simulation. The design methodology is expected to allow scalable embedded multiprocessors for system expansion. In recent decades, two forces have driven the increase of the processor performance: Advances in very largescale integration (VLSI) technology and Micro architectural enhancements. Therefore, we aim to design the full architecture of an embedded processor for realistic to perform arithmetic, logical, shifting and branching operations. We will be synthesize and evaluated the embedded system based on Xilinx environment. Processor performance is going to be improving through clock speed inc...

This study consider the problem of high-resolution imaging of the remote sensing (RS) environment formalized in terms of a nonlinear ill- posed inverse problem of nonparametric estimation of the power spatial spectrum pattern (SSP) of the wavefield scattered from an extended remotely sensed scene (referred to as the scene image). However, the remote sensing techniques for reconstructive imaging in many RS application areas are relatively unacceptable for being implemented in a (near) real time implementation. In this work, we address a new aggregated descriptive-regularization (DR) method and the Hardware/Software (HW/SW) co-design for the SSP reconstruction from the uncertain speckle-corrupted measurement data in a computationally efficient parallel fashion that meets the (near) real time image processing requirements. The hardware design is performed via efficient systolic arrays (SAs). Finally, the efficiency both in resolution enhancement and in computational complexity reductio...

The paper suggest a novel approach to the problem of high-resolution array radar/SAR imaging as an ill-conditioned inverse spatial spectrum pattern (SSP) estimation problem with model uncertainties. We explain the theory recently developed by the authors of this presentation that addresses a new fused Bayesian-regularization paradigm for radar/SAR image formation/reconstruction. We show how this theory leads to new adaptive and robustified computational methods that enable one to derive efficient and consistent estimates of the SSP via unifying the Bayesian minimum risk estimation strategy with the ME randomized a priori image model and other projection-type regularization constraints imposed on the solution. We detail such fused Bayesian-regularization (FBR) paradigm and analyze some efficient numerical schemes for computational implementation of the relevant FBR-based methods. Also, we present the results of extended simulation study of the family of the radar image (RI) formation...

With more embedded systems networked, it becomes an important problem to effectively defend embedded systems against buffer overflow attacks. Due to the increasing complexity and strict requirements, off-the-shelf software components are widely used in embedded systems, especially for military and other critical applications. Therefore, in addition to effective protection, we also need to provide an approach for system integrators to efficiently check whether software components have been protected. In this paper, we propose the HSDefender (Hardware/Software Defender) technique to perform protection and checking together. Our basic idea is to design secure call instructions so systems can be secured and checking can be easily performed. In the paper, we classify buffer overflow attacks into two categories and provide two corresponding defending strategies. We analyze the HSDefender technique with respect to hardware cost, security, and performance. We experiment with our HSDefender technique on the SimpleScalar/ARM simulator with benchmarks from MiBench, an embedded benchmark suite. The results show that our HSDefender technique can defend a system against more types of buffer overflow attacks with less overhead compared with the previous work.

HW/SW techniques make it possible for the system designers to validate their design, assign modules to be implemented in either hardware or software in the early stages of the system design life cycle. In addition, those techniques provide powerful mechanism for continuous system validation until the final product is done. Partitioning the system into either hardware or software, in the system early stages, is vital decision that has to be done iteratively and accurately. Many techniques have been proposed for HW/SW partitioning: conventional circuit partitioning techniques, simulated annealing, expert systems, and even genetic algorithm techniques. The partitioning problem has been proved to be and NP-Hard problem, thus AI, ANN and GA techniques can find a rich playground to apply their techniques. This paper presents a novel approach to use Bayesian Belief Networks as the tool that does the partitioning decision when provided by simulation parameters that measure certain character...

A committee of industry and government technology experts has completed a three-year effort to develop a set of specifications that consist of a unifying set of functions, communications protocols, a common set of commands, and electronic data sheet formats that will serve as the basis for all future IEEE 1451 smart transducer interface standards. This paper will highlight the key features of the proposed IEEE P1451.0 standard and describe how these features are being used in applications, and how they are beneficial to users in achieving data-level interoperability where multiple wired and wireless sensor networks are connected.

Architecture and Implementation of adaptive NoC to improve performance and power consumption is presented. On platforms hosting multiple applications, hardware variations and unpredictable workloads make static design-time assignments highly sub-optimal e.g. in terms of power and performance. As a solution to this problem, adaptive NoCs are designed, which dynamically adapt towards optimal implementation. This paper addresses the architectural design of adaptive NoC, which is an essential step towards design automation. The architecture involves two levels of agents: a system level agent implemented in software on a dedicated general purpose processor and the local agents implemented as microcontrollers of each network node. The system agent issues specific instructions to perform monitoring and reconfiguration operations, while the local agents operate according to the commands from the system agent. To demonstrate the system architecture, best-effort power management with distribu...

Skills in hardware-software co-design are quickly becoming critical to product development in hightechnology computer industries. Systems-on-silicon typically include a considerable amount of software as well as custom hardware and are increasingly difficult to develop using traditional techniques. To satisfy a growing demand in industry, students in electrical engineering, computer engineering, and computer science should be introduced to concepts of hardware-software co-design at the undergraduate level. This paper examines a new laboratory at the University of Missouri-Rolla in which students in Electrical and Computer Engineering are exposed to modern system design concepts through the use of hardware-software co-simulation. Key tools used in the course including a hardware prototype consisting of an 8051 microcontroller and a field programmable gate array, and a VHDL model of the prototype are discussed.

Field-programmable gate arrays (FPGA's) have come a long way from the days when they served primarily as glue logic and prototyping devices. Today's FPGA's have matured to the level where they can host a significant number of programmable gates and CPU cores to create complete System on Chip (SoC) hybrid CPU+FPGA devices. These hybrid chips promise the potential of providing a unified platform for seamless implementation of hardware and software co-designed components. Realizing the potential of these new hybrid chips requires a new high-level programming model, with capabilities that support a far more integrated view of the CPU and the FPGA components than is achievable with current methods. Adopting a generalized programming model can lead to programming productivity improvement, while at the same time providing the benefit of customized hardware from within a familiar software programming. Achieving abstract programming capabilities across the FPGA/CPU boundary requires adaptation of a high-level programming model that abstracts the FPGA and CPU components, bus structure, memory, and low-level peripheral protocol into a transparent computational platform [2]. This thesis presents research on extending the multithreaded programming model across the CPU/FPGA boundary. Our objective was to create an environment to support concurrent executing hybrid threads distributed flexibly across CPU and FPGA assets. To support this generalized model across the FPGA, we have developed a Hardware Thread Interface (HWTI) that encapsulates mechanisms to support synchronization for FPGA based threads. The HWTI enables custom threads within the FPGA to be created, accessed, and synchronized with all other system threads through library API's. Additionally, the HWTI is capable of managing "thread state", accessing data across the system bus, and executing independently without the need to use CPU. Current multithreaded programming models use synchronization mechanisms such as semaphores to enforce mutual exclusion on shared resources. Semaphores depend on atomic operations provided through the CPU assembler instruction set. In multiprocessor systems, atomic operations are achieved by combinations of processor condition instructions integrated within memory coherency protocol of snooping data caches. Since these current mechanisms do not extend well to FPGA based threads, we have developed new semaphore mechanisms that are processor family independent. We achieve a much simpler solution and faster mechanisms (8 I would like to express my sincere appreciation and gratitude to everyone who made this thesis possible. First and foremost, I would to thank my adviser Dr. David Andrews for his guidance, encouragement and patience throughout the tenure of this research. From him, I hope that I have learned enough to conduct research, to write and publish papers.

Hybrid systems consisting of a multitude of different computing device types are interesting targets for high-performance applications. Chip multiprocessors, FPGAs, DSPs, and GPUs can be readily put together into a hybrid system; however, it is not at all clear that one can effectively deploy applications on such a system. Coordinating multiple languages, especially very different languages like hardware and software languages, is awkward and error prone. Additionally, implementing communication mechanisms between different device types unnecessarily increases development time. This is compounded by the fact that the application developer, to be effective, needs performance data about the application early in the design cycle. We describe an application development environment specifically targeted at hybrid systems, supporting data-flow semantics between application kernels deployed on a variety of device types. A specific feature of the development environment is the availability of performance estimates (via simulation) prior to actual deployment on a physical system.

This work describes a hardware/software co-design system development, named IEEE 1451 platform, to be used in process automation. This platform intends to make easier the implementation of IEEE standards 1451.0, 1451.1, 1451.2 and 1451.5. The hardware was built using NIOS II processor resources on Alteras Cyclone II FPGA. The software was done using Java technology and C/C++ for the processors programming. This HW/SW system implements the IEEE 1451 based on a control module and supervisory software for industrial automation.

Technology scaling trends and the limitations of packaging and cooling have intensified the need for thermally efficient architectures and architecture-level temperature management techniques. To combat these trends, we evaluate the thermal efficiency of the microcore architecture, a deeply decoupled processor core with larger structures factored out as helper engines. We further investigate activity migration (core swapping) as a means of controlling the thermal profile of the chip in this study. Specifically, the microcore architecture presents an ideal platform for core swapping thanks to helper engines that maintain the state of each process in a shared fabric surrounding the cores. This results in significantly reduced migration overhead, enabling seamless swapping of cores. Our results show that our thermal mechanisms outperform traditional Dynamic Thermal Management (DTM) techniques by reducing the performance hit caused by slowing/swapping of cores. Our experimental results show that the microcore architecture has 86% fewer thermally critical cycles compared to a conventional monolithic core.

Technology scaling trends and the limitations of packaging and cooling have intensified the need for thermally efficient architectures and architecture-level temperature management techniques. To combat these trends, we evaluate the thermal efficiency of the microcore architecture, a deeply decoupled processor core with larger structures factored out as helper engines. We further investigate activity migration (core swapping) as a means of controlling the thermal profile of the chip in this study. Specifically, the microcore architecture presents an ideal platform for core swapping thanks to helper engines that maintain the state of each process in a shared fabric surrounding the cores. This results in significantly reduced migration overhead, enabling seamless swapping of cores. Our results show that our thermal mechanisms outperform traditional Dynamic Thermal Management (DTM) techniques by reducing the performance hit caused by slowing/swapping of cores. Our experimental results show that the microcore architecture has 86% fewer thermally critical cycles compared to a conventional monolithic core.

We propose in this paper an algebraic approach to hard-ware/software partitioning in Verilog Hardware Description Language (HDL). We explore a collection of algebraic laws for Verilog programs, from which we design a set of syntax-based algebraic rules to conduct hardware/software partitioning. The co-specification language and the target hardware and software description languages are specific subsets of Verilog. Through this, we confirm successful verification for the correctness of the partitioning process by an algebra of ...

Hardware/software codesign is a methodology for solving design problems in systems with processors or embedded controllers where the design requirements mandate a functionality and performance level for the system, independent of the hardware and software boundary. In addition to the challenges of functional correctness and total system performance, design time is often a critical factor. To design MAGIC, the programmable memory and communication controller for the Stanford FLASH multiprocessor, we employed a hardware/software codesign methodology. This methodology allowed us to concurrently design the hardware and software thereby reducing design time while simultaneously ensuring that the design would meet ambitious performance goals. Serializing the hardware and software design would have lengthened the design time and significantly increased the amount of redesign when the tradeoffs between the hardware and software implementations became clear late in the design process. The codesign approach led us to build a series of hierarchical simulators that allowed us to begin design verification early and to reduce the level of effort required to ensure a functional design.

The wireless and ambulatory posture monitoring system monitors the movement and posture change of the human body with respect to the g-line. It is crucial to monitor the posture health of the ophthalmologist who spends a prolonged period on the static sitting posture while operating on the slit lamp which leads to any painful experience. The motivation of the proposed system is to improve the ergonomics of the ophthalmologist on their working environment and reduce any occupational potential hazard which may prompt Work-Related Musculoskeletal Disorders (WMSDs). The proposed system also induced a wireless system by using XBee wireless units to reduce the use of the wire that may tangle on the study subject which causes any uncomfortable experience to the study subject during the human trial. Inertial Measurement Unit (IMU) sensor which consists of an Accelerometer, a Gyroscope and a Magnetometer is used to measure the angle of deviation of the body segment with respect to the g-line...

Este artigo apresenta a evolução do motion graphics em que imagens e textos são apresentados em movimento, inicialmente no cinema em aberturas de filmes, títulos e créditos, depois na televisão. A moldura fixa da tela bidimensional mudou com o desdobramento da linguagem fílmica em ambientes de imersão de realidade virtual para o vídeo 360º, imagem tridimensional que envolve o observador que escolhe para onde vai olhar. O ambiente de imersão é explicado nos pontos de vista da tecnologia e percepção do observador, com óculos de realidade virtual. O foco principal é a tipografia em filmes convencionais e a variação para ambientes tridimensionais. São abordados a legibilidade e unidades de medida para textos em movimento em ambientes de vídeo 360º.