Dynamic Memory Management Research Papers

An efficient clustering method for fast rendering of time-varying volumetric medical data

2025, The Visual Computer

Visualization and exploration of time-varying volumetric medical data help clinicians for better diagnosis and treatment. However, it is a challenge to render these data in an interactive manner because of their complexity and large size.... more

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Tertiary buddy system for efficient dynamic memory allocation

by DIVAKAR YADAV

2025

An extension of the binary buddy system, called "tertiary buddy system" for dynamic storage allocation is presented in this work. Tertiary buddy system allows block sizes of 2 k and 3.2 k-3 whereas the original binary buddy system allows... more

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A new implementation technique for memory management

by Mehran Rezaei

2025, Proceedings of the IEEE SoutheastCon 2000. 'Preparing for The New Millennium' (Cat. No.00CH37105)

Dynamic memory management is an important and essential part of computer systems design. Efficient memory allocation, garbage collection and compaction are becoming increasingly more critical in parallel, distributed and real-time... more

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Exybris Pipeline: A Modular AI Framework for Industrial, Military, and Context-Driven Memory Retrieval Optimization

by Andréa Gadal

2025, Exybris Pipeline: A Modular AI Framework for Industrial, Military, and Context-Driven Memory Retrieval Optimization

The Exybris Pipeline introduces a modular architecture for optimizing contextual memory retrieval and scoring in AI systems, targeting industrial, military, and strategic applications. Leveraging dynamic memory adaptation, contextual... more

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Parallel simulation today

by Richard Fujimoto

2025, Annals of Operations Research

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The Design of a Novel Object-oriented Processor : OOMIPS

by Muhammad Kamran

2024, 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP)

A novel object-oriented processor is proposed in this paper, which provides support for object addressing, message passing and dynamic memory management. Object running on this processor has its own control thread and communicates with... more

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Memory management thread for heap allocation intensive sequential applications

by Devesh Tiwari

2024, Proceedings of the 10th workshop on MEmory performance: DEaling with Applications, systems and architecture

Dynamic memory management is one of the most ubiquitous and expensive operations in many C/C++ applications. Some C/C++ programs might spend up to one third of their execution time in dynamic memory management routines. With multicore... more

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Power aware data type refinement for the HIPERLAN/2

by Athanasios Kakarountas

2023

This paper considers a domain specific methodology that has been employed to derive a cost optimized on-chip memory architecture for network protocols such as the Data Link Control layer of the HIPERLAN/2 protocol. The performed design... more

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An efficient clustering method for fast rendering of time-varying volumetric medical data

by Nguyễn Phú

2023, The Visual Computer

Visualization and exploration of time-varying volumetric medical data help clinicians for better diagnosis and treatment. However, it is a challenge to render these data in an interactive manner because of their complexity and large size.... more

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Feasibility of decoupling memory management from the execution pipeline

by Kavi Kavi

2023, Journal of Systems Architecture

This article was published in an Elsevier journal. The attached copy is furnished to the author for non-commercial research and education use, including for instruction at the author's institution, sharing with colleagues and providing to... more

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A Hardware Assisted High Performance PHK Memory Manager

by Kavi Kavi

2023

Complex mechanisms for dynamic memory management and garbage collection are needed in modern imperative programming languages. Implementation of memory management functions efficiently both in terms of memory usage and execution... more

Figure 1: Block Diagram of Our Proposed Hardware Com- ponent (For Page Size 4096 bytes and Object Size 16 bytes) The software in our allocator is responsible for cre- ating page indexes and for initializing the page header as in a software implementation of PHK. For large objects (larger than half a page), the software takes full responsibil- ity without any hardware assistance. When an application requests allocation for a small sized object, the software portion of our hybrid system will locate the bitmap and is- sues a search request to the hardware. The hardware por- tion in our allocator will search the page index (or bitmap) in parallel to find a free chunk, and mark the bitmap to in- dicate an allocation. This co-design allocator can be fully compatible with current multitasking operating system.

show the details of the flipper logic here. It may be noted that the critical path in this design is only the AND-tree for the “allocate” operation. The “free” doesn’t generate any output, and the processor can immediately continue execu- tion of application code. Figure 2: The Block Diagram of Overall Hardware

Figure 3: Normalized Memory Management Performance Improvement

Table 1: Comparison of Chang’s Allocator and Our Design

Table 3: Percentage time spent in Selected Benchmarks for different (Average) Object Sizes

Table 4: Performance Comparison with PHK Allocator

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A Classy Memory Management System (CyM2S) using an Isolated Dynamic Two-Level Memory Allocation (ID2LMA) Algorithm for the Real Time Embedded Systems

by Narmadha Narmadha

2023, International Journal of Electrical and Electronics Research

Due to an increased scalability, flexibility, and reduced cost complexity, the dynamic memory allocation models are highly preferred for the real-time embedded systems. For this purpose, the different types of dynamic models have been... more

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Dynamic memory management design methodology for reduced memory footprint in multimedia and wireless network applications

by Dimitrios Soudris

2023, Proceedings Design, Automation and Test in Europe Conference and Exhibition

New portable consumer embedded devices must execute multimedia and wireless network applications that demand extensive memory footprint. Moreover, they must heavily rely on Dynamic Memory (DM) due to the unpredictability of the input data... more

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Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded Systems

by Dimitrios Soudris

2023, Lecture Notes in Computer Science

Portable embedded devices must presently run multimedia and wireless network applications with enormous computational performance requirements at a low energy consumption. In these applications, the dynamic memory subsystem is one of the... more

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Hardware OS communication service and dynamic memory management for RSoCs

by surya narayanan

2023, Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011

In a multiprocessor system, to gain the advantages of parallelism, efficient communication and memory management are highly required. The recent developments in the partial and dynamic Reconfigurable Computing (RC) domain require better... more

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Feasibility of decoupling memory management from the execution pipeline

by Mehran Rezaei

2022, Journal of Systems Architecture

This article was published in an Elsevier journal. The attached copy is furnished to the author for non-commercial research and education use, including for instruction at the author's institution, sharing with colleagues and providing to... more

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Fast Escape Analysis for Region-based Memory Management

by Diego Garbervetsky

2022, Electronic Notes in Theoretical Computer Science

We present an algorithm for escape analysis inspired by, but more precise than, the one proposed by Gay and Steensgaard [11]. The primary purpose of our algorithm is to produce useful information to allocate memory using a region-based... more

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Custom Design of Multi-Level Dynamic Memory Management Subsystem for Embedded Systems

by Christophe Poucet

2022, IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.

Modern embedded systems have to run new dynamic wireless network and multimedia applications. As a result, these systems must provide run-time memory management support to allow real-time memory de/allocation, retrieving and processing of... more

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Hardware Dynamic Memory Manager for Hard Real-Time Systems

by Viera Stopjakova

2022, Annals of Emerging Technologies in Computing

This paper presents novel hardware architecture of dynamic memory manager providing memory allocation and deallocation operations that are suitable for hard real-time and safety-critical systems due to very high determinism of these... more

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A Hardware Assisted High Performance PHK Memory Manager

by kavi kavi

2022

Complex mechanisms for dynamic memory management and garbage collection are needed in modern imperative programming languages. Implementation of memory management functions efficiently both in terms of memory usage and execution... more

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Model Checking Dynamic Memory Allocation in Operating Systems

by Pedro Merino

2022, Journal of Automated Reasoning

Most system software, including operating systems, contains dynamic data structures whose shape and contents should satisfy design requirements during execution. Model checking technology, a powerful tool for automatic verification based... more

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A Classy Memory Management System (CyM2S) using an Isolated Dynamic Two-Level Memory Allocation (ID2LMA) Algorithm for the Real Time Embedded Systems

by FOREX Publication

2022, IJEER

Due to an increased scalability, flexibility, and reduced cost complexity, the dynamic memory allocation models are highly preferred for the real-time embedded systems. For this purpose, the different types of dynamic models have been... more

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Architectural support for dynamic memory management

by Dan Lo

2022

Recent advances in software engineering, such as graphical user intevaces and object-oriented programming, have caused applications to become more memory intensive. These applications tend to allocate dynamic memory prolipcally. Moreove<... more

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Hardware OS communication service and dynamic memory management for RSoCs

by Daniel Chillet

2022, Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011

In a multiprocessor system, to gain the advantages of parallelism, efficient communication and memory management are highly required. The recent developments in the partial and dynamic Reconfigurable Computing (RC) domain require better... more

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A parallel evolutionary algorithm to optimize dynamic memory managers in embedded systems

by Jose Hidalgo

2022

For the last 30 years, several dynamic memory managers (DMMs) have been proposed. Such DMMs include first fit, best fit, segregated fit and buddy systems. Since the performance, memory usage and energy consumption of each DMM differs,... more

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D.E.S.K. DISCRETE EVENTS SIMULATION KERNELi

by Enrique Ramos

2021

DESK is a universal object oriented package developed using ANSI C++. It is a kernel prepared to cope with discrete events model simulations. The aim of this project is to implement a very easy and versatile simulator that is fast and... more

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Reliable General Purpose Dynamic Memory Management for Real-Time Systems

by Kelvin Nilsen

2021, Rtss

Traditional dynamic memory management techniques for imperative programming languages are unsuitable for reliable real-time applications because their worst-case time and space requirements are insufficiently bounded. This is demonstrated... more

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Reliable general purpose dynamic memory management for real-time systems

by Kelvin Nilsen

2021, Proc. IEEE-'Real-Time Systems Symposium

Traditional dynamic memory management techniques for imperative programming lan-guages are unsuitable for reliable real-time applications because their worst-case time and space requirements are insufficiently bounded. This is... more

We instrumented the dynamic memory management routines so that we could measure how much time was spent allocating new memory. The worst-case costs are summarized in Table 5.2. Note that the costs of allocating new objects using the garbage-collected C++ implementations are all less than 110 machine cycles, whereas the worst-case costs of allocating new objects using the traditional memory allocators range from 2,000 to over 150,000 machine cycles. Clearly, use of traditional memory allocators in real-time applications represents a potential source of unpredictable timing performance.

For the same workloads, Table 5.3 summarizes the average delays associated with allocation of new memory. Note the order of magnitude differences between the values reported in tables 5.2 and 5.3. Note also that the aver. age cost of allocating memory in the garbage-collected system is typically less than 10% of the cost of allocating memory using the best traditional techniques. We consider the sfft application not to be statistically significant in this measure, because it only allocates two relatively large objects. It is important to recognize that Table 5.2 reports worst-case measured execution times. For most of the explicit memory management techniques, it is not practical to analytically derive the worst-case times required to service allocation requests. In contrast, proofs of real-time performance have been demonstrated for the garbage- collector’s allocator [23].

Tables 5.4 and 5.5 report the worst- and average-case costs of deallocating memory. Note that deallocation is free in the garbage-collected system.

Remember that the cost of deallocating an object includes the cost of searching for neighboring objects with which to coalesce the deallocated object. This is why, for several of the allocators, the costs of deallocating objects is ever higher than the costs of allocating them.

Memory is a costly component in modern computer systems. In many of tomorrow’s embedded compute! memory will be the single most expensive component in the system. To achieve high memory utilization is one | the goals of a system designer. We have measured the memory heap size and memory usage of the traditional all cators and the garbage collection system. Heap sizes are reported in Table 5.6. The traditional allocators start 0 with a small heap, and expand the heap as necessary in order to support the application. The garbage-collected all cator uses a fixed size heap throughout execution of each workload. The reported heap size, which includes bo from-space and to-space, is constrained by limitations in our current simulator to be a power of two. For most of tl applications, the GC heap is much larger than the traditional heap. This is because the GC heap is unable to utili: more than one of its two semispaces at a time. For the lisp application, the GC heap is much smaller than the trac tional heap. For cham, the GC heap is approximately the same size as the traditional heaps. In both cases, tl garbage collector is able to reclaim memory that the programmers failed to deallocate.

We define heap utilization as the quotient of the combined sizes of all live objects divided by the heap size. For the traditional implementations, live objects are defined as objects allocated but not yet freed, and heap size is the maxi- mum size of the sbrk region. For the garbage-collected implementations, live objects are defined as all of the objects in existence immediately following completion of garbage collection, and the heap size is defined as the combined size of both semispaces. For both the garbage-collected and traditional allocators, the size of a live object is defined to include whatever tags accompany it. Table 5.7 reports the average heap utilization of the various work- loads. Note that the utilization of traditional allocators is not directly comparable with that of the garbage-collected implementations because of the different definitions of utilization.

Table 5.7 must be interpreted carefully. Note, for example, that lisp’s traditional allocators report much higher uti- lization than the garbage collector, even though the garbage collector executes in a smaller heap. This is because of the differences in the definition of liveness between traditional and garbage-collected allocators. In an attempt to calibrate these figures, we have quantified the storage leaks that are present in each of the applications, as tabulated in Table 5.8.

Table 5.9 reports adjusted memory utilizations for each of the allocators. This table was computed by adjusting the traditional allocator utilizations by the estimated storage leak percentages reported in Table 5.8. Note that Table 5.9 correlates roughly, but not exactly, with Table 5.6. The main differences between Table 5.6 and 5.9 result from the differences in the memory utilization sampling frequencies. For the traditional allocators, the average utilization was computed by averaging the utilizations at the point of each allocation, whereas for the garbage-collected alloca- tor, the average utilization was computed by averaging the utilizations at the end of each garbage collection. For most of the test cases, there were thousands of allocations and fewer than ten garbage collections. All of the statis- tics reported in tables 5.7 through 5.9 should be viewed with this in mind. The main point to be emphasized is that the GC implementations generally offer much poorer memory utilization than the traditional implementations. The percentages reported in Table 5.8 were determined by comparing the amounts of live memory following termi- nation of the last garbage collection performed during each of the benchmarks. In the cham application, for exam- ple, there were X bytes of live memory at the time that the last garbage collection completed. After the GNU/C++ implementation of cham had completed approximately the same fraction of its computation as the garbage-collected implementation had completed when we last measured its live memory, the difference between the amount of mem- ory that had been allocated and the amount of memory that had been deallocated was Y bytes, where (1 —0.45) xY =X. Note that in all cases, the garbage collector’s notion of live memory is smaller than that of the traditional allocators.

Table 5.10: Execution time (10° cycles), Instruction count (10° instructions), CPI As discussed above, memory allocation and deallocation runs much faster in the GC implementation than in the tra- ditional systems. Programs for which the costs of memory management are relatively large (5% or higher) are most likely to benefit from this performance advantage. Programs that do not deallocate memory do not benefit as much from this factor as those that do. The GC system imposes a 9-instruction overhead on each function call. Thus, applications that require frequent function calls generally suffer worse performance in their garbage-collected imple- mentations. This is especially noticeable in the cfrac and lisp measurements. This effect is counterbalanced by other effects in the troff benchmark, as discussed below.

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Efficient dynamic heap allocation of scratch-pad memory

by Joseph Sventek

2021, Proceedings of the 7th international symposium on Memory management - ISMM '08

An increasing number of processor architectures support scratchpad memory-software managed on-chip memory. Scratch-pad memory provides low latency data storage, like on-chip caches, but under explicit software control. The simple design... more

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Toward a high performance distributed memory climate model

by John Ambrosiano

2021, [1993] Proceedings The 2nd International Symposium on High Performance Distributed Computing

ofCalifornia, LosAngeles 90024-1565 atmosphere, whichinturnplays a critical role incontrolling theearth's climate. Under a variety ofrea. As partofa longrangeplantodevelop a compre-sonable growthscenarios forpopulation and indushensive... more

ofCalifornia, LosAngeles 90024-1565 atmosphere, whichinturnplays a critical role incontrolling theearth's climate. Under a variety ofrea. As partofa longrangeplantodevelop a compre-sonable growthscenarios forpopulation and indushensive climate systemsmodeling capability, we have trial activity, theincreasing concentration ofgreentakenthe Atmospheric GeneralCirculation Model housegases overthenextfewdecades couldresult in originally developed by Arakawa and collaborators a radiative forcing equivalent tothatproducedby a at UCLA and haverecastitin a portable, paral-doubling ofpreindustrial levels ofcarbon dioxide. lelform. The code usesan explicit time-advance While itislikely thatthisprocess willeventuprocedure on a staggered three-dimensional Eulerian ally affect global climate, we are far from being able mesh. We have implemented a two-dimensional lat-to predict accurately the timing, magnitude, and reitude/longitude domain decomposition message pass-gional pattern of such changes. Attempts to alter ing strategy. Both dynamic memory management and the present global system of energy production to efinterprocessor communication are handled with macro fectively counter a possible worldwide temperature constructs that are preprocessed prior to compilation, rise could incur enormous social and economic costs. The code can be moved about a variety of platforms, However, the effects of global climate change resulting including massively parallel processors, workstation from an unchecked temperature increase could prove clusters, and vector processors, with a mere change equally costly. For these reasons it is vitally imporof three parameters. Performance on the various plat-tant to improve the scientific basis for understanding forms as well as issues associated with coupling differ-and predicting the response of the earth's environmenent models for major components of the climate sys-tal systems to substantial perturbations, both natural tem are discussed, and human-induced.

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Toward a high performance distributed memory climate model

by J. Ambrosiano

2021, [1993] Proceedings The 2nd International Symposium on High Performance Distributed Computing

ofCalifornia, LosAngeles 90024-1565 atmosphere, whichinturnplays a critical role incontrolling theearth's climate. Under a variety ofrea. As partofa longrangeplantodevelop a compre-sonable growthscenarios forpopulation and indushensive... more

ofCalifornia, LosAngeles 90024-1565 atmosphere, whichinturnplays a critical role incontrolling theearth's climate. Under a variety ofrea. As partofa longrangeplantodevelop a compre-sonable growthscenarios forpopulation and indushensive climate systemsmodeling capability, we have trial activity, theincreasing concentration ofgreentakenthe Atmospheric GeneralCirculation Model housegases overthenextfewdecades couldresult in originally developed by Arakawa and collaborators a radiative forcing equivalent tothatproducedby a at UCLA and haverecastitin a portable, paral-doubling ofpreindustrial levels ofcarbon dioxide. lelform. The code usesan explicit time-advance While itislikely thatthisprocess willeventuprocedure on a staggered three-dimensional Eulerian ally affect global climate, we are far from being able mesh. We have implemented a two-dimensional lat-to predict accurately the timing, magnitude, and reitude/longitude domain decomposition message pass-gional pattern of such changes. Attempts to alter ing strategy. Both dynamic memory management and the present global system of energy production to efinterprocessor communication are handled with macro fectively counter a possible worldwide temperature constructs that are preprocessed prior to compilation, rise could incur enormous social and economic costs. The code can be moved about a variety of platforms, However, the effects of global climate change resulting including massively parallel processors, workstation from an unchecked temperature increase could prove clusters, and vector processors, with a mere change equally costly. For these reasons it is vitally imporof three parameters. Performance on the various plat-tant to improve the scientific basis for understanding forms as well as issues associated with coupling differ-and predicting the response of the earth's environmenent models for major components of the climate sys-tal systems to substantial perturbations, both natural tem are discussed, and human-induced.

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Efficient memory management for hardware accelerated Java Virtual Machines

by Peter Bertels

2021, ACM Transactions on Design Automation of Electronic Systems - TODAES

Application-specific hardware accelerators can significantly improve a system's performance. In a Java-based system, we then have to consider a hybrid architecture that consists of a Java Virtual Machine running on a general-purpose... more

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Hardware Dynamic Memory Manager for Hard Real-Time Systems

by Lukáš Kohútka

2021, Annals of Emerging Technologies in Computing

This paper presents novel hardware architecture of dynamic memory manager providing memory allocation and deallocation operations that are suitable for hard real-time and safety-critical systems due to very high determinism of these... more

This paper presents novel hardware architecture of dynamic memory manager providing memory allocation and deallocation operations that are suitable for hard real-time and safety-critical systems due to very high determinism of these operations. The proposed memory manager implements Worst-Fit algorithm for selection of suitable free block of memory that can be used by the external environment, e.g. CPU. The deterministic timing of the memory allocation and deallocation operations is essential for hard real-time systems. The proposed memory manager performs these operations in nearly constant time thanks to the adoption of hardware-accelerated max queue, which is a data structure that continuously provides the largest free block of memory in two clock cycles regardless of actual number or constellation of existing free blocks of memory. In order to minimize the overhead caused by implementing the memory management in hardware, the max queue was optimized by developing a new sorting architecture, called Rocket-Queue. The Rocket-Queue architecture as well as the whole memory manager is described in this paper in detail. The memory manager and the Rocket-Queue architecture were verified using simplified version of UVM and applying billions of randomly generated instructions as testing inputs. The Rocket-Queue architecture was synthesized into Intel FPGA Cyclone V with 100 MHz clock frequency and the results show that it consumes from 17,06% to 38,67% less LUTs than the existing architecture, called Systolic Array. The memory manager implemented in a form of a coprocessor that provides four custom instructions was synthesized into 28nm TSMC HPM technology with 1 GHz clock frequency and 0.9V power supply. The ASIC synthesis results show that the Rocket-Queue based memory manager can occupy up to 24,59% smaller chip area than the Systolic Array based manager. In terms of total power consumption, the Rocket-Queue based memory manager consumes from 15,16% to 42,95% less power.

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Hardware Dynamic Memory Manager for Hard Real-Time Systems

by Lukáš Kohútka

2021, Annals of Emerging Technologies in Computing

This paper presents novel hardware architecture of dynamic memory manager providing memory allocation and deallocation operations that are suitable for hard real-time and safety-critical systems due to very high determinism of these... more

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Toward a high performance distributed memory climate model

by Michael Wehner

2021, [1993] Proceedings The 2nd International Symposium on High Performance Distributed Computing

ofCalifornia, LosAngeles 90024-1565 atmosphere, whichinturnplays a critical role incontrolling theearth's climate. Under a variety ofrea. As partofa longrangeplantodevelop a compre-sonable growthscenarios forpopulation and indushensive... more

ofCalifornia, LosAngeles 90024-1565 atmosphere, whichinturnplays a critical role incontrolling theearth's climate. Under a variety ofrea. As partofa longrangeplantodevelop a compre-sonable growthscenarios forpopulation and indushensive climate systemsmodeling capability, we have trial activity, theincreasing concentration ofgreentakenthe Atmospheric GeneralCirculation Model housegases overthenextfewdecades couldresult in originally developed by Arakawa and collaborators a radiative forcing equivalent tothatproducedby a at UCLA and haverecastitin a portable, paral-doubling ofpreindustrial levels ofcarbon dioxide. lelform. The code usesan explicit time-advance While itislikely thatthisprocess willeventuprocedure on a staggered three-dimensional Eulerian ally affect global climate, we are far from being able mesh. We have implemented a two-dimensional lat-to predict accurately the timing, magnitude, and reitude/longitude domain decomposition message pass-gional pattern of such changes. Attempts to alter ing strategy. Both dynamic memory management and the present global system of energy production to efinterprocessor communication are handled with macro fectively counter a possible worldwide temperature constructs that are preprocessed prior to compilation, rise could incur enormous social and economic costs. The code can be moved about a variety of platforms, However, the effects of global climate change resulting including massively parallel processors, workstation from an unchecked temperature increase could prove clusters, and vector processors, with a mere change equally costly. For these reasons it is vitally imporof three parameters. Performance on the various plat-tant to improve the scientific basis for understanding forms as well as issues associated with coupling differ-and predicting the response of the earth's environmenent models for major components of the climate sys-tal systems to substantial perturbations, both natural tem are discussed, and human-induced.

This paper was prepared for submittal to the Second International Symposium on High Performance Distributed Computing Spokane, WA Tulv 21-93. 1993

Figure 2. Parallel performance of the AGCM on the BBN-TC2000. Speedup as defined in eq.(3). vs. number of processors.

Figure 3. Parallel speedup of the AGCM on clusters of workstations.

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Improving reliability of embedded systems through dynamic memory manager optimization using grammatical evolution

by ignacio hidalgo

2021

Technology scaling has offered advantages to embedded systems, such as increased performance, more available memory and reduced energy consumption. However, scaling also brings a number of problems like reliability degradation mechanisms.... more

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D.E.S.K. DISCRETE EVENTS SIMULATION KERNELi

by Ramón Mollá Vayá

2021

DESK is a universal object oriented package developed using ANSI C++. It is a kernel prepared to cope with discrete events model simulations. The aim of this project is to implement a very easy and versatile simulator that is fast and... more

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Optimization of dynamic memory managers for embedded systems using grammatical evolution

by David Atienza

2020, Proceedings of the 11th Annual conference on Genetic and evolutionary computation - GECCO '09

New portable consumer embedded devices must execute multimedia applications (e.g., 3D games, video players and signal processing software, etc.) that demand extensive memory accesses and memory usage at a low energy consumption. Moreover,... more

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Multi-objective optimization of dynamic memory managers using grammatical evolution

by David Atienza

2020, Genetic and Evolutionary Computation Conference, GECCO'11

New portable consumer embedded devices must execute multimedia applications (e.g., 3D games, video players and signal processing software, etc.) that demand extensive memory accesses and memory usage at a low energy consumption. Moreover,... more

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Improving reliability of embedded systems through dynamic memory manager optimization using grammatical evolution

by David Atienza

2020, Proceedings of the 12th annual conference on Genetic and evolutionary computation - GECCO '10

Technology scaling has offered advantages to embedded systems, such as increased performance, more available memory and reduced energy consumption. However, scaling also brings a number of problems like reliability degradation mechanisms.... more

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Simulation of high-performance memory allocators

by David Atienza

2020, Microprocessors and Microsystems

Current general-purpose memory allocators do not provide sufficient speed or flexibility for modern highperformance applications. To optimize metrics like performance, memory usage and energy consumption, software engineers often write... more

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A parallel evolutionary algorithm to optimize dynamic memory managers in embedded systems

by David Atienza and

2020

New multimedia embedded applications are increasingly dynamic, and rely on dynamically-allocated data types (DDTs) to store their data. The optimization of DDTs for each target embedded system is a time-consuming process due to the large... more

Fig. 1 Code before and after the exploration of DDT

another solution y € X if the following two conditions are satisfied:

Fig. 3. A graphic representation of the coarse grained model

Fig. 5 Non-dominated individuals obtained by NSGA-II, SPEA2, N‘*. S* and NS?

Fig. 7 Execution times (a) and non-dominated solutions (b) as a function of the number of workstations. Each workstation executes two islands

Table 4 Parameters for both sequential algorithms

Table 5 Comparison between the proposed sequential algorithms and other techniques

Table 6 Coverage metric Table 7 Spread and spacing for the five algorithms

Table 8 Comparison between our sequential and distributed algorithms

spread can be calculated if the obtained set is far from the POF.

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Evaluation of the Effectiveness of Domain Modeling Methods in Terms of Model Complexity

by Mykola Tkachuk

2020, Proceedings of the ICTERI-2019: 15th International Conference on ICT in Education, Research and Industrial Applications: Integration, Harmonization and Knowledge Transfer, Kherson, Ukraine, June 12-15, 2019, CEUR-WS.org/Vol-2387, pp. 513-518.

Domain Modeling Methods (DMMs) are used to improve quality in the development of complex software systems such as product families. This paper examines how the effectiveness of such methods in combination with appropriate case tools (CTs)... more

Fig. 1. Taxonomy of domain modeling methods Within the last 10-15 years, a variety of DMMs have been developed and presented [6]. Fig.1 shows a classification of such methods along the project assets whose reuse is supported by the respective method.

Fig. 2. DDD levels and variability points Transferring the traditional 3-level architecture of database management [14] to the Domain-Driven Design approach leads to a hierarchy as depicted in Fig. 2. The "variability points" in this hierarchy indicate that the same DM can have mul- tiple realizations on the logical level, which in turn can have multiple implementa- tions on the code level. Managing and exploiting this variability is currently one of the main challenges in modern software development [3].

Fig. 3. Procedure for coefficient calculation

Fig. 4. The DM realization Mtyopa, Actifsource

Fig. 5. The impact of complexity on the effectiveness coefficient E

Table 1. List of widely used case tools (+: available, -: not available, +/- needed or in progress) In the next section we will introduce our approach to DMM assessment step by step.

Table 4. Effectiveness coefficients values and ratio

Table 2. Class complexity assessment in DM Table 3. Relationship complexity assessment in DM

Table 5. Test variants This led to the results presented in Table 6. They show that applying the ODM/EMF technology to all test cases proved more effective than the JODA/Actifsource tech- nology.

Table 6. Experimental results for the test cases To discuss this result briefly, we point out once again that the reusability extent CRE of the source code depends more on the CASE-tool used to support a given DMM, while the comp exity level DMC depends more on the expertise of the model- er. To analyze the latter impact factor we considered the relation between the DMC parameter and the efficiency coefficient E (see Fig. 5) which proves that the effec- tiveness coefficient E d ecreases substantially with an increasing complexity. This fact indicates a sufficient validity of our proposed approach to determine the effectiveness of different domain modeling techniques when applied to given domain model. Moreover, the approac favorable effectiveness h ensures the selection of a domain modeling technique with a coefficient ratio (in 0.5-1.9 times in our tests).

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Hardware Dynamic Memory Manager for Hard Real-Time Systems

by Annals of Emerging Technologies in Computing (AETiC)

2019, Annals of Emerging Technologies in Computing (AETiC)

This paper presents novel hardware architecture of dynamic memory manager providing memory allocation and deallocation operations that are suitable for hard real-time and safety-critical systems due to very high determinism of these... more

This paper presents novel hardware architecture of dynamic memory manager providing memory allocation and deallocation operations that are suitable for hard real-time and safety-critical systems due to very high determinism of these operations. The proposed memory manager implements Worst-Fit algorithm for selection of suitable free block of memory that can be used by the external environment, e.g. CPU. The deterministic timing of the memory allocation and deallocation operations is essential for hard real-time systems. The proposed memory manager performs these operations in nearly constant time thanks to the adoption of hardware-accelerated max queue, which is a data structure that continuously provides the largest free block of memory in two clock cycles regardless of actual number or constellation of existing free blocks of memory. In order to minimize the overhead caused by implementing the memory management in hardware, the max queue was optimized by developing a new sorting architecture, called Rocket-Queue. The Rocket-Queue architecture as well as the whole memory manager is described in this paper in detail. The memory manager and the Rocket-Queue architecture were verified using simplified version of UVM and applying billions of randomly generated instructions as testing inputs. The Rocket-Queue architecture was synthesized into Intel FPGA Cyclone V with 100 MHz clock frequency and the results show that it consumes from 17,06% to 38,67% less LUTs than the existing architecture, called Systolic Array. The memory manager implemented in a form of a coprocessor that provides four custom instructions was synthesized into 28nm TSMC HPM technology with 1 GHz clock frequency and 0.9V power supply. The ASIC synthesis results show that the Rocket-Queue based memory manager can occupy up to 24,59% smaller chip area than the Systolic Array based manager. In terms of total power consumption, the Rocket-Queue based memory manager consumes from 15,16% to 42,95% less power.

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JDESK WEB-BASED DISCRETE EVENT SIMULATION KERNEL1

by Ramón Mollá and

2014

DESK is a universal object oriented package developed using ANSI C++. It is a kernel prepared to cope with discrete events model simulations. The aim of this project is to implement a very easy and versatile simulator that is fast and... more

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