Hardware Dynamic Memory Manager for Hard Real-Time Systems

Proceedings of the first conference on computing frontiers on Computing frontiers - CF'04, 2004

Data transfer and storage issues "take the centre stage" in information and communication systems because of the increasing complexity and data dominance typically associated to them. In this paper, we summarise a systematic methodology for the power critical storage modules such as local SRAMs. We focus on their memory organisation (access schedule and data assignment) together with an exploration of the effect that the interconnect technology may have on the energy consumed by these local memory organisations in deep sub-micron technologies.

Any embedded system contains both on-chip and off-chip memory modules with different access times. During system integration, the decision to map critical data on to faster memories is crucial. In order to obtain good performance targeting less amounts of memory, the data buffers of the application need to be placed carefully in different types of memory. There have been huge research efforts intending to improve the performance of the memory hierarchy. Recent advancements in semiconductor technology have made power consumption also a limiting factor for embedded system design. SRAM being faster than the DRAM, cache memory comprising of SRAM is configured between the CPU and the main memory. The CPU can access the main memory (DRAM) only via the cache memory. Cache memories are employed in all the computing applications along with the processors. The size of cache allowed for inclusion on a chip is limited by the large physical size and large power consumption of the SRAM cells used in cache memory. Hence, its effective configuration for small size and low power consumption is very crucial in embedded system design. We present an optimal cache configuration technique for the effective reduction of size and high performance. The proposed methodology was tested in real time hardware using FPGA. Matrix multiplication algorithm with various sizes of workloads is hence validated. For the validation of the proposed approach we have used Xilinx ISE 9.2i for simulation and synthesis purposes. The prescribed design was implemented in VHDL.

The Interactions between CPU and Main Memory Architecture, 2020

ABSTRACT In modern general-purpose computer architectures, the rate of improvement in microprocessor speed exceeds the rate of improvement in speed of main memory. Although the speed gap between processor and main memory has already been an issue, downstream it somewhere may be a bigger one. Computer designers are facing the increased speed gap between processor and main memory, which now is the primary challenge to improve computer system’s performance. In this emerging architecture, the band width of the bus interfaces between Processor & main memory has already become a greater issue to be deal with. This is just because of its limited data transfer capacity in between processor & main memory and its high access time respectively. Though computer architects devoted more efforts to dramatically increase the speed of processors, the overall performance of the computer system is not yet improved as the improvement rate of processors. This research paper focuses on incorporating new components with combination of functionalities; like accepting more than one request in parallel through different additional paths in a collision free process. Afterwards a new Memory Management Technique for improving the speed of the memory is also examined. Finally a new design solution i.e. data transfer rate between processor and main memory has been increased by integration of separate Buses. KEYWORDS Architecture, Processor, Main memory, speed gap, parallel, collision, Memory Management Technique

2011 IEEE International SOC Conference, 2011

For heterogeneous multi-core SoCs, the increasing demand of the memory capacity and bandwidth becomes a critical design challenge. In this paper, an on-demand memory sUbsystem is presented to efficiently control the memory access and memory resource allocation using adaptively allocated cache memory. The proposed adaptively allocated cache memory can dynamically assign a variable number of SRAM banks for process elements (PEs) to optimize the utilization of the centralized on-chip cache. In a wireless video entertainment system, a 7.13% execution time reduction and 10.53% energy reduction of memories can be achieved using the adaptively allocated cache memory.

IEEE Transactions on Computers, 2000

The memory system of the Dorado, a compact highperformance personal computer, has very high I/O bandwidth, a large paged virtual memory, a cache, and heavily pipelined control; this paper discusses all of these in detail. Relatively low-speed I/O devices transfer single words to or from the cache; fast devices, such as a color video display, transfer directly to or from main storage while the processor uses the cache. Virtual addresses are used in the cache and for all I/O transfers. The memory is controlled by a seven-stage pipeline, which can deliver a peak main-storage bandwidth of 533 million bits/s to service fast I/O devices and cache misses. Interesting problems of synchronization and scheduling in this pipeline are discussed. The paper concludes with some performance measurements that show, among other things, that the cache hit rate is over 99 percent.

2008 IEEE International Symposium on Parallel and Distributed Processing, 2008

With increasing demand for low power high performance computing,reducing power of not only CPUs but also memory is becoming important. In typical generalpurpose HPC environments, DRAM is installed in an overprovisioned fashion to avoid swapping, although in most cases not all such memory is used, leading to unnecessary and excessive power consumption, even in a standby state. We propose a next generation low power memory system that reduces required DRAM capacity while minimizing application performance degradation. In this system, both DRAM and MRAM, fast non-volatile memory, are used as main memory, while flash memory is used as a swap device. Our profile-based paging algorithm optimizes memory accesses by using faster memory as much as possible, reducing accesses to slower memory. Simulated results of our architecture show that the overall energy consumption of the memory system can be reduced to 25% by in the best case by reducing DRAM capacity, with only 17% performance loss in application benchmarks.

IEEE Micro, 2006

Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '11, 2011

Designing memory controllers for complex real-time and highperformance multi-processor systems-on-chip is challenging, since sufficient capacity and (real-time) performance must be provided in a reliable manner at low cost and with low power consumption. This special session contains four presentations that describe these challenges and proposed solutions for DRAM and flash memory controllers, respectively. The first presentation discusses performance and reliability issues in flash memories, while the second identifies challenges in providing DRAM access to memory clients with mixed time-criticality. The third presentation proposes an integrated approach to optimize cost and performance of the DRAM subsystem, and the last one describes how wide DRAM interfaces enabled by 3D technology improve DRAM performance and reduces power.

The modern computer systems that are in use nowadays are mostly processor-dominant, which means that their memory is treated as a slave element that has one major task-to serve execution units data requirements. This organization is based on the classical Von Neumann's computer model, proposed seven decades ago in the 1950 ties. This model suffers from a substantial processor-memory bottleneck, because of the huge disparity between the processor and memory working speeds. In order to solve this problem, in this paper we propose a novel architecture and organization of processors and computers that attempts to provide stronger match between the processing and memory elements in the system. The proposed model utilizes a memory-centric architecture, wherein the execution hardware is added to the memory code blocks, allowing them to perform instructions scheduling and execution, management of data requests and responses, and direct communication with the data memory blocks without using registers. This organization allows concurrent execution of all threads, processes or program segments that fit in the memory at a given time. Therefore, in this paper we describe several possibilities for organizing the proposed memory-centric system with multiple data and logicmemory merged blocks, by utilizing a high-speed interconnection switching network.