Study of bending-induced strain effects on MuGFET performance

This study combines direct measurements of channel strain, electrical mobility measurements and a rigorous modeling approach to provide insight about the strain induced mobility enhancement in FinFETs and guidelines for the device optimization. Good agreement between simulated and measured mobility is obtained using strain components measured directly at device level by a novel technique. A large vertical compressive strain is observed in FinFETs and the simulations show that this helps recover the electron mobility disadvantage of the (110) FinFETs lateral interfaces w.r.t. (100) interfaces, with no degradation of the hole mobility. The model is then used to systematically explore the impact of the fin-width, finheight and fin-length stress components on nand p-FinFETs mobility and to identify optimal stress configurations. IEDM09-72 4.2.2 IEDM09-74 4.2.4

We present a comprehensive electrical performance assessment of hafnium silicate (HfSiOₓ) high-κ dielectric and titanium-nitride (TiN) metal-gate-integrated FinFET-based complementary-metal-oxide-semiconductor (CMOS) on flexible silicon on insulator. The devices were fabricated using the state-of-the-art CMOS technology and then transformed into flexible form by using a CMOS-compatible maskless deep reactive-ion etching technique. Mechanical out-of-plane stresses (compressive and tensile) were applied along and across the transistor channel lengths through a bending range of 0.5-5 cm radii for n-type and p-type FinFETs. Electrical measurements were carried out before and after bending, and all the bending measurements were taken in the actual flexed (bent) state to avoid relaxation and stress recovery. Global stress from substrate bending affects the devices in different ways compared with the well-studied uniaxial/biaxial localized strain. The global stress is dependent on the type of channel charge carriers, the orientation of the bending axis, and the physical gate length of the device. We, therefore, outline useful insights on the design strategies of flexible FinFETs in future free-form electronic applications.

2012

List of Figures 1.1 Definition of Stress and Strain in elastic mechanics 2 1.2 Silicon band structures calculated using perturbation methods 5 1.3 Poisson-Schrödinger self-consistent solving procedure for calculating carrier sub-band energies in the quantum well 1.4 Sub-band energies in quantum well for different surface orientations and comparison of hole equi-energy contours between bulk and quantum well cases 8 1.5 Inversion carrier mobility issues in a MOSFET structure 9 1.6 Short-channel MOSFET carrier transport issues 10 1.7 Embedded Source/Drain stressor technologies for planar bulk MOSFETs 11 1.8 Strained Contact-etch-stop-liner technologies for planar bulk MOSFETs 11 1.9 Stress Memorization Techniques for planar bulk MOSFETs 1.10 Metal-gate last process to enhance planar bulk MOSFET channel strain 12 1.11 Stressor technologies used in advanced planar bulk MOSFETs 1.12 Fully Depleted SOI MOSFET structures and using thin BOX structure to further improve electrostatics 14 1.13 Multiple-Gate MOSFET structures and fin aspect-ratio design rule 15 1.14 Stressor technologies used in Fully Depleted SOI MOSFETs 1.15 Stressor technologies used in Multiple-Gate MOSFETs 2.1 Measured and simulated carrier mobilities in FD-SOI MOSFETs 2.2 Carrier mobility enhancement by strain in FD-SOI MOSFETs 2.3 Calculated 1 st sub-bands equi-energy contours in FD-SOI MOSFETs 32 2.4 Simulated carrier mobility vs. Silicon body thickness 33 2.5 Measured short-channel apparent mobilities vs. gate length in FD-SOI MOSFETs 2.6 Measured limiting velocities in short-channel FD-SOI MOSFETs vs. gate length 2.7 Measured strain-induced apparent mobility enhancement vs. gate length in FD-SOI MOSFETs 34 2.8 Measured strain-induced carrier limiting velocities vs. gate length in short-channel FD-SOI MOSFETs 3.1 MuGFET device meshing for the 2-D Poisson-Schrödinger solver 3.2 Simulated inversion charge distribution across the Multiple-gate structure 43 3.3 TEM cross-sectional view of MuGFET devices and the I d-V g curves 43 3.4 MuGFET design variations regarding of fin orientations and stressors 44 viii 3.5 Measured and Simulated MuGFET carrier mobilties vs. N inv 45 3.6 MuGFET carrier mobility enhancement under biaxial strain 45 3.7 FinFET electron mobility enhancement and scattering rates change under different stressor technologies 3.8 FinFET hole mobility enhancement and scattering rates change under different stressor technologies 46 3.9 Comparison between FinFET and Tri-Gate FET carrier mobilities 47 3.10 MuGFET carrier limiting velocities under different stressor technologies 48 3.11 Schematic view of FinFET structure in the stress simulation study 49 3.12 FinFETs with different local uniaxial stressor technologies 50 3.13 Multiple-layer simulation method for the sCESL stressor on FinFET 51 3.14 Simulated stress profiles in 25nm-L g SOI FinFETs with S/D and sCESL 52 3.15 Simulated stress profiles in 17/12nm-L g SOI FinFETs with S/D and sCESL 53 3.16 Simulated stress profiles in 17/12nm-L g bulk FinFETs with S/D stressors 53 3.17 Simulated stress contours during the Gate-Last process flow of a FinFET 54 3.18 Simulated stress profiles in 17/12nm-L g FinFETs fabricated by a Gate-Last flow 54 3.19 Simulated FinFET carrier mobility enhancement by S/D stressors under different process variations 56 4.1 Gate stack/channel structures for planar bulk, FD-SOI MOSFETs and FinFETs 62 4.2 Comparison between high-κ/metal gate FD-SOI MOSFET and FinFET structures 66 4.3 Measured and simulated carrier mobilities in high-κ/metal gate FD-SOI MOSFETs 67 4.4 Calculated 1 st sub-band equi-energy contours in FinFETs and FD-SOI MOSFETs 68 4.5 Comparison of simulated carrier mobilities in FinFETs and FD-SOI MOSFETs as Silicon body thickness scaling 69 5.1 Measured I d-V g curves from UTBB FD-SOI MOSFETs under different back bias 73 5.2 Measured and simulated FD-SOI inversion capacitance under different back bias 74 5.3 Back bias coefficient vs. back bias voltage in UTBB FD-SOI MOSFET 74 5.4 Simulated inversion charge distribution in UTBB FD-SOI MOSFETs at V th 75 5.5 Capacitor network model to describe the impact of back biasing on UTBB FD-SOI MOSFET inversion capacitance 76 5.6 Measured I off vs. I on for short-channel UTBB FD-SOI MOSFETs 76 5.7 Measured and simulated UTBB FD-SOI MOSFET carrier mobilities vs. inversion charge concentration under different back biasing 77 5.8 Extracted short-channel UTBB FD-SOI MOSFET apparent mobilities vs. gate length under different back biasing 78 ix 5.9 Measured and simulated UTBB FD-SOI carrier mobility enhancement under wafer bending strain, and for different back biasing 78 5.10 Simulated UTBB FD-SOI MOSFET unstrained carrier mobility enhancement ratio vs. back biasing for different Silicon body thickness 79 5.11 Simulated UTBB FD-SOI MOSFET piezo-coefficients (∏ xx and ∏ zz) vs. back biasing for different Silicon body thickness 80 5.12 Extracted UTBB FD-SOI MOSFET carrier ON-state velocities vs. gate length under different back biasing 81 5.13 Measured relationship between I on increase and I dlin increase induced by wafer bending stress and Forward Back Biasing 81 5.14 Measured I ds noise spectral density for short-channel UTBB FD-SOI MOSFETs, under different back biasing 82 5.15 Measured normalized noise spectral density at f=10Hz vs. drain current for shortchannel UTBB FD-SOI MOSFETs, under different back biasing 82 6.1 Calculated III-V material band structures using 8×8 k•p approach 87 6.2 Schematic view of fabricating high mobility channel materials on a Silicon fin 87 x List of Tables 2.1 Electron effective mass values used in 1-D Schrödinger equation 25 3.1 Electron effective mass values used in 2-D Schrödinger equation 39 3.2 Default FinFET geometrical design parameters 50 3.3 FinFET design parameters for sub-20nm CMOS technology nodes 52 3.4 Summary of Stress Transfer Efficiency values for different stressor technologies, for 12nm and 17nm-L g FinFETs fabricated using Gate-First or Gate-Last process flows 55 4.1 Frequency-dependent permittivity and optical phonon energy values for different oxide materials. 64 5.1 Elucidation of Forward Back Biasing and Silicon Body thickness scaling's impacts on Piezo-resistance coefficients ∏ xx and ∏ zz. 80 xi I would like to thank all my research partners with regards to this thesis work. With Dr. Xin Sun (IBM), Dr. Lynn T.-N. Wang (Globalfoundries) and Byron Ho, I could perform my research more elaborately. They provided the kindest assistance (especially during the conference deadlines) and countless great discussions on strain-induced enhancement in MOSFETs, advanced transistor structures, and semiconductor process issues. This work has been funded through a few sources, such as the UC Berkeley Graduate Fellowship and the UC Discovery Grant ele07-10283 under the IMPACT program. In addition, fabrication of the test chips for studying advanced thin-body MOSFETs was done and donated by Texas Instruments (Dr. Weize "Wade" Xiong), CEA-LETI Minatec (Dr.

Electron Devices, …, 2011

This study combines direct measurements of strain, electrical mobility measurements, and a rigorous modeling approach to provide insights about strain-induced mobility enhancement in FinFETs and guidelines for device optimization. Good agreement between simulated and measured mobility is obtained using strain components measured directly at device level by a novel holographic technique. A large vertical compressive strain is observed in metal gate FinFETs, and the simulations show that this helps recover the electron mobility disadvantage of the (110) FinFET lateral interfaces with respect to (100) interfaces, with no degradation of the hole mobility. The model is then used to systematically explore the impact of stress components in the fin width, height, and length directions on the mobility of both nand p-type FinFETs and to identify optimal stress configurations. Finally, self-consistent Monte Carlo simulations are used to investigate how the most favorable stress configurations can improve the ON current of nanoscale MOSFETs.

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303), 2002