Strain scaling for CMOS

2012

List of Figures 1.1 Definition of Stress and Strain in elastic mechanics 2 1.2 Silicon band structures calculated using perturbation methods 5 1.3 Poisson-Schrödinger self-consistent solving procedure for calculating carrier sub-band energies in the quantum well 1.4 Sub-band energies in quantum well for different surface orientations and comparison of hole equi-energy contours between bulk and quantum well cases 8 1.5 Inversion carrier mobility issues in a MOSFET structure 9 1.6 Short-channel MOSFET carrier transport issues 10 1.7 Embedded Source/Drain stressor technologies for planar bulk MOSFETs 11 1.8 Strained Contact-etch-stop-liner technologies for planar bulk MOSFETs 11 1.9 Stress Memorization Techniques for planar bulk MOSFETs 1.10 Metal-gate last process to enhance planar bulk MOSFET channel strain 12 1.11 Stressor technologies used in advanced planar bulk MOSFETs 1.12 Fully Depleted SOI MOSFET structures and using thin BOX structure to further improve electrostatics 14 1.13 Multiple-Gate MOSFET structures and fin aspect-ratio design rule 15 1.14 Stressor technologies used in Fully Depleted SOI MOSFETs 1.15 Stressor technologies used in Multiple-Gate MOSFETs 2.1 Measured and simulated carrier mobilities in FD-SOI MOSFETs 2.2 Carrier mobility enhancement by strain in FD-SOI MOSFETs 2.3 Calculated 1 st sub-bands equi-energy contours in FD-SOI MOSFETs 32 2.4 Simulated carrier mobility vs. Silicon body thickness 33 2.5 Measured short-channel apparent mobilities vs. gate length in FD-SOI MOSFETs 2.6 Measured limiting velocities in short-channel FD-SOI MOSFETs vs. gate length 2.7 Measured strain-induced apparent mobility enhancement vs. gate length in FD-SOI MOSFETs 34 2.8 Measured strain-induced carrier limiting velocities vs. gate length in short-channel FD-SOI MOSFETs 3.1 MuGFET device meshing for the 2-D Poisson-Schrödinger solver 3.2 Simulated inversion charge distribution across the Multiple-gate structure 43 3.3 TEM cross-sectional view of MuGFET devices and the I d-V g curves 43 3.4 MuGFET design variations regarding of fin orientations and stressors 44 viii 3.5 Measured and Simulated MuGFET carrier mobilties vs. N inv 45 3.6 MuGFET carrier mobility enhancement under biaxial strain 45 3.7 FinFET electron mobility enhancement and scattering rates change under different stressor technologies 3.8 FinFET hole mobility enhancement and scattering rates change under different stressor technologies 46 3.9 Comparison between FinFET and Tri-Gate FET carrier mobilities 47 3.10 MuGFET carrier limiting velocities under different stressor technologies 48 3.11 Schematic view of FinFET structure in the stress simulation study 49 3.12 FinFETs with different local uniaxial stressor technologies 50 3.13 Multiple-layer simulation method for the sCESL stressor on FinFET 51 3.14 Simulated stress profiles in 25nm-L g SOI FinFETs with S/D and sCESL 52 3.15 Simulated stress profiles in 17/12nm-L g SOI FinFETs with S/D and sCESL 53 3.16 Simulated stress profiles in 17/12nm-L g bulk FinFETs with S/D stressors 53 3.17 Simulated stress contours during the Gate-Last process flow of a FinFET 54 3.18 Simulated stress profiles in 17/12nm-L g FinFETs fabricated by a Gate-Last flow 54 3.19 Simulated FinFET carrier mobility enhancement by S/D stressors under different process variations 56 4.1 Gate stack/channel structures for planar bulk, FD-SOI MOSFETs and FinFETs 62 4.2 Comparison between high-κ/metal gate FD-SOI MOSFET and FinFET structures 66 4.3 Measured and simulated carrier mobilities in high-κ/metal gate FD-SOI MOSFETs 67 4.4 Calculated 1 st sub-band equi-energy contours in FinFETs and FD-SOI MOSFETs 68 4.5 Comparison of simulated carrier mobilities in FinFETs and FD-SOI MOSFETs as Silicon body thickness scaling 69 5.1 Measured I d-V g curves from UTBB FD-SOI MOSFETs under different back bias 73 5.2 Measured and simulated FD-SOI inversion capacitance under different back bias 74 5.3 Back bias coefficient vs. back bias voltage in UTBB FD-SOI MOSFET 74 5.4 Simulated inversion charge distribution in UTBB FD-SOI MOSFETs at V th 75 5.5 Capacitor network model to describe the impact of back biasing on UTBB FD-SOI MOSFET inversion capacitance 76 5.6 Measured I off vs. I on for short-channel UTBB FD-SOI MOSFETs 76 5.7 Measured and simulated UTBB FD-SOI MOSFET carrier mobilities vs. inversion charge concentration under different back biasing 77 5.8 Extracted short-channel UTBB FD-SOI MOSFET apparent mobilities vs. gate length under different back biasing 78 ix 5.9 Measured and simulated UTBB FD-SOI carrier mobility enhancement under wafer bending strain, and for different back biasing 78 5.10 Simulated UTBB FD-SOI MOSFET unstrained carrier mobility enhancement ratio vs. back biasing for different Silicon body thickness 79 5.11 Simulated UTBB FD-SOI MOSFET piezo-coefficients (∏ xx and ∏ zz) vs. back biasing for different Silicon body thickness 80 5.12 Extracted UTBB FD-SOI MOSFET carrier ON-state velocities vs. gate length under different back biasing 81 5.13 Measured relationship between I on increase and I dlin increase induced by wafer bending stress and Forward Back Biasing 81 5.14 Measured I ds noise spectral density for short-channel UTBB FD-SOI MOSFETs, under different back biasing 82 5.15 Measured normalized noise spectral density at f=10Hz vs. drain current for shortchannel UTBB FD-SOI MOSFETs, under different back biasing 82 6.1 Calculated III-V material band structures using 8×8 k•p approach 87 6.2 Schematic view of fabricating high mobility channel materials on a Silicon fin 87 x List of Tables 2.1 Electron effective mass values used in 1-D Schrödinger equation 25 3.1 Electron effective mass values used in 2-D Schrödinger equation 39 3.2 Default FinFET geometrical design parameters 50 3.3 FinFET design parameters for sub-20nm CMOS technology nodes 52 3.4 Summary of Stress Transfer Efficiency values for different stressor technologies, for 12nm and 17nm-L g FinFETs fabricated using Gate-First or Gate-Last process flows 55 4.1 Frequency-dependent permittivity and optical phonon energy values for different oxide materials. 64 5.1 Elucidation of Forward Back Biasing and Silicon Body thickness scaling's impacts on Piezo-resistance coefficients ∏ xx and ∏ zz. 80 xi I would like to thank all my research partners with regards to this thesis work. With Dr. Xin Sun (IBM), Dr. Lynn T.-N. Wang (Globalfoundries) and Byron Ho, I could perform my research more elaborately. They provided the kindest assistance (especially during the conference deadlines) and countless great discussions on strain-induced enhancement in MOSFETs, advanced transistor structures, and semiconductor process issues. This work has been funded through a few sources, such as the UC Berkeley Graduate Fellowship and the UC Discovery Grant ele07-10283 under the IMPACT program. In addition, fabrication of the test chips for studying advanced thin-body MOSFETs was done and donated by Texas Instruments (Dr. Weize "Wade" Xiong), CEA-LETI Minatec (Dr.

Electron Devices, …, 2004

A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si 1 Ge in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by

ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference, 2009

We integrated Fully Depleted Silicon-On-Insulator (FDSOI) nand pMOSFETs on (1.16 percent, 2.1GPa) eXtremely strained SOl (XsSOI) substrates. We demonstrate a 135% electron mobility enhancement at W=77nm and a significant ION-I o FF improvement for short and narrow nMOS on XsSOI compared to unstrained SOl. We in-depth analyze this performance boost thanks to accurate extractions in narrow devices of both the carrier mobility (after adaptation of the split-CV method) and the strain (by X-Ray Diffraction performed in synchrotron facility). This improvement depends on the channel orientation and is partly attributed to the tensile strain induced by the TiN gate and partly by the effective mass improvement under high and non-biaxial strain.

ACS Applied Materials & Interfaces, 2020

We report a novel approach for engineering tensely strained Si layers on a relaxed Silicon Germanium On Insulator (SGOI) film using a combination of condensation, annealing and epitaxy in selected conditions well chosen based on elastic simulations. The study evidences the remarkable role of SiO2 buried oxide layer (BOX) on the elastic behavior of the system. We show that tensely strained Si can be engineered by using alternatively rigidity (at low temperature) and viscoelasticity (at high temperature) of the SiO2 substrate. In these conditions, we get a Si strained layer perfectly flat and free of defects on top of relaxed Si1−xGex. We found very specific annealing conditions to relax SGOI while keeping an homogeneous Ge concentration and an excellent thickness uniformity resulting from the viscoelasticity of SiO2 at this temperature, which would allow layer by layer matter redistribution. Remarkably, Si layer epitaxially grown on relaxed SGOI remains fully strained with-0.85 % tensile strain. The absence of strain sharing (between Si1−xGex and Si) is explained by the rigidity of the Si1−xGex/BOX interface at low temperature. Elastic simulations of the real system show that, due to the very specific elastic characteristics of SiO2, there are unique experimental conditions that both relax Si1−xGex and keep Si strained. Various epitaxial processes could be revisited in the light of these new results. The generic and simple process implemented here meets all the requirements of the microelectronics industry and should be rapidly integrated in the fabrication lines of large multifinger 2.5 V n-type MOSFET on SOI used for RF-switches applications and for many other applications.