An experimental and simulation study of shortchannel planar bulk nMOSFET performance enhancement ... more An experimental and simulation study of shortchannel planar bulk nMOSFET performance enhancement achieved with oxygen insertion technology is presented. The benefits of this technology for low-power digital logic circuits make it a promising evolutionary approach to extend bulk MOSFET scaling.
She oversees undergraduate research programs to recruit and retain underrepresented students in s... more She oversees undergraduate research programs to recruit and retain underrepresented students in science and engineering and science and also outreach to pre-college students to introduce them to the exciting career opportunities in science and engineering. Dr.
(Keynote) Silicon-Germanium: Enabler of Moore's Law
ECS Meeting Abstracts, 2018
Exponential growth in the number and capability of computing and communication devices over the p... more Exponential growth in the number and capability of computing and communication devices over the past several decades has led to the proliferation of information technology, with transformative impact on society. Key to this rapid growth has been transistor miniaturization (“scaling”), which enables ever higher levels of integration on a silicon chip following Moore’s Law, to provide for improved integrated circuit (IC) performance and functionality per unit area. As the incremental benefits of classic (Dennard) scaling diminished due to fundamental limits for transistor operation, the industry resorted to the incorporation of the semiconductor alloy silicon-germanium (SiGe) to steadily improve the performance of complementary metal-oxide-semiconductor (CMOS) transistors and thereby enable Moore’s Law to be sustained. The application of doped polycrystalline SiGe as an alternative MOSFET gate material was first proposed and demonstrated in 1990; subsequently it was shown to provide f...
FinFET Performance Enhancement with Tensile Metal Gates and Strained Silicon on Insulator (sSOI) Substrate
2006 64th Device Research Conference, 2006
... Introduction The channel surfaces of a FinFET fabricated on a (100) Si wafer can be either ..... more ... Introduction The channel surfaces of a FinFET fabricated on a (100) Si wafer can be either ... Global and local strain engineering techniques have been shown to be effective for enhancing field-effect ... in the channel is to use a stressed gate electrode [4]. In this paper, we report on ...
Micro-relay reliability improvement by inkjet-printed microshell encapsulation
2013 Transducers & Eurosensors XXVII: The 17th International Conference on Solid-State Sensors, Actuators and Microsystems (TRANSDUCERS & EUROSENSORS XXVII), 2013
We report an extensive investigation of advanced gate technology for high-performance and high-re... more We report an extensive investigation of advanced gate technology for high-performance and high-reliability sub-ll4pm CMOS technology. Gate nitrogen implant profile engineering and gate microstructure engineering are effective approaches to control gate boron diffusion in the dual-doped gate CMOS processes. A physical model is developed to study the gate-depletion effect (GDE) in scaled MOSFET's with low-voltage / ultra-thin gate oxide as well as the impact of GDE on the speed performance of logic IC's.
A 2.4GHz power amplifier is implemented with standard thin-oxide transistors in a 1.2V, 0.13 mum ... more A 2.4GHz power amplifier is implemented with standard thin-oxide transistors in a 1.2V, 0.13 mum CMOS process. The output matching network is fully integrated on chip. The PA transmits up to 24dBm linear power with 25% drain efficiency at -1dB compression point. When driven into saturation, it transmits 27dBm peak power with 32% drain efficiency. A technique for enhancing average efficiency is proposed and demonstrated. This technique does not degrade instantaneous efficiency at peak power and maintains constant power gain with power back-off
Multi-Gate MOSFETs with Dual Contact Etch Stop Liner Stressors on Tensile Metal Gate and Strained Silicon on Insulator (sSOI)
2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2007
This paper describes a comprehensive study of the impact of tCESL (tensile Contact Etch Stop Line... more This paper describes a comprehensive study of the impact of tCESL (tensile Contact Etch Stop Liner) and cCESL (compressive Contact Etch Stop Liner) on tensile metal gate MuGFET with SOI and globally strained SOI (sSOI) substrates. We have demonstrated that tCESL and cCESL can be effectively used on MuGFETs to provide performance gain. Since tCESL and cCESL affect NMOS and
Threshold voltage and DIBL variability modeling for SRAM and analog MOSFETs
2012 Symposium on VLSI Technology (VLSIT), 2012
A physically-based variability model is developed to explain threshold voltage (VT) and drain ind... more A physically-based variability model is developed to explain threshold voltage (VT) and drain induced barrier lowering (DIBL) variations, and their correlations. Inputs to the model rely on forward (F) and reverse (R) data of measured transistor pair mismatch. Positionally asymmetric and symmetric random dopant fluctuation components of VT and DIBL variability are identified for SRAMs and analog devices from a 32nm HKMG technology and their correlations explained.
Mechanical properties of polycrystalline silicon solar cell feed stock grown via fluidized bed reactors
Journal of Materials Science, 2009
Abstract Polysilicon granular beads grown via a fluidized bed reactor, a feedstock for silicon so... more Abstract Polysilicon granular beads grown via a fluidized bed reactor, a feedstock for silicon solar cell production, were annealed, sectioned, and indented using a combination of nanoindentation and microhardness testing to determine the mechanical response of this commercially available raw material. The granular material, with macroscopic dimensions on the order of millimeters and an internal grain size on the order of 20 nm, has an indentation modulus of approximately 160 GPa, and a hardness prior to fracture of 9.6 ...
Interfacial Adhesion between Rough Surfaces of Polycrystalline Silicon and Its Implications for M/NEMS Technology
Journal of Adhesion Science and Technology, 2010
... 28. TR Thomas, B.-G. Rosen and N. Amini, Wear 232, 41 (1999). 29. A. Majumdar and B. Bhushan,... more ... 28. TR Thomas, B.-G. Rosen and N. Amini, Wear 232, 41 (1999). 29. A. Majumdar and B. Bhushan, J. Tribology 113, 1 (1991). 30. PR Nayak, J. Lubrication Technol. ... 36. JI McCool, Wear 107, 37 (1986). 37. AW Bush, RD Gibson and TR Thomas, Wear 35, 87 (1975). 38. ...
Forward body biasing is a promising approach for realizing optimum threshold-voltage (V TH) scali... more Forward body biasing is a promising approach for realizing optimum threshold-voltage (V TH) scaling in the era when gate dielectric thickness can no longer be scaled down. This is confirmed experimentally and by simulation of a 10-nm gate length MOSFET. Because forward body bias (V F) decreases the depletion width (X DEP) in the channel region, it reduces V TH rolloff significantly. MOSFET performance is maximized under forward body bias with steep retrograde channel doping, and such channel doping profiles are required to accomplish good shortchannel behavior (small X DEP) at low V TH notwithstanding body bias; therefore, the combination of forward body biasing with steep retrograde channel doping profile can extend the scaling limit of conventional bulk-Si CMOS technology to 10-nm gate length MOSFET. Considering forward biased p-n junction current, parasitic bipolar transistor, and CMOS latch-up phenomena, the upper limit for |V F | should be set at 0.6-0.7 V, which is sufficient to realize significant advantages of forward body biasing.
The impact of stress induced by biaxial mechanical bending on multiple-gate FET (MuGFET) performa... more The impact of stress induced by biaxial mechanical bending on multiple-gate FET (MuGFET) performance is studied. For relatively low levels of bending-induced surface strain (∼ 0.1%), significant enhancements in the driving current can be achieved and maintained with gate-length scaling. This makes package strain a potentially attractive approach to enhancing MuGFET-based CMOS performance at low cost. For bending-induced strain, the enhancements in electron mobility and (110) hole mobility are well predicted by the piezoresistance model using the coefficients for bulk-Si, but the impact of stress on (100) hole mobility is more complex.
Impact of Gate-Induced Strain on MuGFET Reliability
IEEE Electron Device Letters, 2008
Hot carrier injection (HCI) reliability and negative bias temperature instability (NBTI) of multi... more Hot carrier injection (HCI) reliability and negative bias temperature instability (NBTI) of multiple-gate field-effect transistors (MuGFETs) with highly tensile metal gate electrodes were investigated. The results were compared with those from control devices with poly-Si gate electrodes. It was found that gate strain boosts performance without any detrimental effect on HCI or NBTI reliability, indicating MuGFET compatibility with strained silicon technology. The impact of fin width (W fin) scaling was also investigated. HCI reliability improves with W fin scaling, whereas NBTI reliability degrades with W fin scaling. The same W fin scaling trends were observed in both strained and unstrained devices.
Impact of strained-silicon-on-insulator (sSOI) substrate on FinFET mobility
IEEE Electron Device Letters, 2006
... significant tensile σxx (1.23 GPa) and tensile σyy (1.11 GPa), and compressive σzz (−0.41 GPa... more ... significant tensile σxx (1.23 GPa) and tensile σyy (1.11 GPa), and compressive σzz (−0.41 GPa), utilizing the heavily doped Si coefficients ... S. Sivakumar, S. Tyagi, T. Ghani, K. Mistry, M. Bohr, and Y. El-Mansy, A logic nanotechnology featuring strained-silicon, Electron Device ...
Selective Enhancement of SiO[sub 2] Etch Rate by Ar-Ion Implantation for Improved Etch Depth Control
Electrochemical and Solid-State Letters, 2007
ABSTRACT Argon- ion implantation can be used to selectively and dramatically enhance the etch rat... more ABSTRACT Argon- ion implantation can be used to selectively and dramatically enhance the etch rate of a silicon dioxide film down to a precise depth, to allow for improved control of etch depth in a timed oxide etch process. An empirical model based on damage concentration, fit to experimental data, is used to explain the correlation between the implantation conditions (dose, energy) and the etch- rate enhancement parameters. The model is shown to yield predictions of the etch rate enhancement consistent with the existing model based on nuclear deposited energy. The depth of etch- rate enhancement is determined primarily by the implant energy, whereas the etch- rate enhancement factor is controlled by the implant dose. Enhancement factors close to five were achieved with moderate- dose (2 x 10(14)/ cm(2)) Ar+ implantation. Lower ion- implantation energy results in sharper transition between the etch- rate enhanced and the unaffected oxide region. This technique can be used to improve process uniformity in fabrication of three- dimensional semiconductor device structures such as bulk- Si FinFETs, for reduced variations in circuit performance. (c) 2007 The Electrochemical Society.
Resistivity of boron and phosphorus doped polycrystalline Si1−xGex films
Applied Physics Letters, 1995
Sheet resistance, Hall mobility, and effective carrier concentration as a function of annealing p... more Sheet resistance, Hall mobility, and effective carrier concentration as a function of annealing parameters for boron or phosphorus ion implanted films of polycrystalline Si, Si0.75Ge0.25, and Si0.50Ge0.50 films are presented. The films were ion implanted with boron or phosphorus at dosages between 5×1014 and 4×1015 cm−2, and then thermally annealed between 550 and 650 °C from 0.25 to 120 min.
Circuit-performance implications for double-gate MOSFET scaling in the sub-25 nm gate length regi... more Circuit-performance implications for double-gate MOSFET scaling in the sub-25 nm gate length regime are investigated. The optimal gate-to-source/drain overlap needed to maximize drive current is found to be different than that needed to minimize FO-4 inverter delay due to parasitic capacitances. It is concluded that the effective channel length must be slightly larger than the physical gate length in order to achieve optimal circuit performance.
The need for more energy-efficient solid-state switches beyond complementary metal-oxide-semicond... more The need for more energy-efficient solid-state switches beyond complementary metal-oxide-semiconductor (CMOS) transistors has become a major concern as the power consumption of electronic integrated circuits (ICs) steadily increases with technology scaling. Nano-Electro-Mechanical (NEM) relays control current flow by nanometer-scale motion to make or break physical contact between electrodes, and offer advantages over transistors for low-power digital logic applications: virtually zero leakage current for negligible static power consumption; the ability to operate with very small voltage signals for low dynamic power consumption; and robustness against harsh environments such as extreme temperatures. Therefore, NEM logic switches (relays) have been investigated by several research groups during the past decade. Circuit simulations calibrated to experimental data indicate that scaled relay technology can overcome the energy-efficiency limit of CMOS technology. This paper reviews recent progress toward this goal, providing an overview of the different relay designs and experimental results achieved by various research groups, as well as of relay-based IC design principles. Remaining challenges for realizing the promise of nano-mechanical computing, and ongoing efforts to address these, are discussed.
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