Performance-driven register insertion in placement

IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1997

A retiming algorithm is presented which includes the effects of variable register, clock distribution, and interconnect delays. These delay components are incorporated into the retiming process by assigning register electrical characteristics (RECs) to each edge in the graph representation of a synchronous circuit. A matrix, called the sequential adjacency matrix (SAM), is presented that contains all path delays. Timing constraints for each data path are derived from this matrix. Vertex lags are assigned ranges rather than single values as in existing retiming algorithms. The approach used in the proposed algorithm is to initialize these ranges with unbounded values and to continuously tighten these ranges using localized timing constraints until an optimal solution is obtained. A branch and bound method is offered for the general retiming problem where the REC values are arbitrary. Certain monotonicity constraints can be placed on the REC values to permit the use of standard linear programming methods, thereby requiring significantly less computational time. These conditions and the feasibility of their application to practical circuits are presented. The algorithm is demonstrated on modified benchmark circuits and both increased clock frequencies and the elimination of all race conditions are observed

This paper analyzes the e ect of resource sharing and assignment on the clock period of the synthesized circuit. The assignment phase assigns or binds operations of the scheduled behavioral description to a set of allocated resources. We focus on control-ow intensive descriptions, characterized by the presence of mutually exclusive paths due to the presence of nested conditional branches and loops. We show that clustering of multiple operations in the same state of the schedule, possibly leading to chaining of functional units (FUs) in the RTL circuit, is an e ective way to minimize the total number of clock cycles and hence the total execution time. We present an assignment algorithm which is particularly e ective for such design styles, by minimizing the data chaining and hence the clock period of the circuit, thereby leading to further reduction in the total execution time. Existing resource sharing and assignment approaches for reducing the clock period of the resulting circuit either increase the resource allocation or use faster modules, both leading to larger area requirements. In this paper we show that even when the type of available resource units and the number of resource units of each type is xed, di erent assignments may lead to circuits with signi cant di erences in clock period. We provide a comprehensive analysis of how resource sharing and assignment introduces long paths in the circuit. Based on the analysis, we develop an assignment algorithm which uses a high-level delay estimator to assign operations to a xed set of available resources so as to minimize the clock period of the resultant circuit, with no or minimal e ect on the area of the circuit. Experimental results on several conditional-intensive designs demonstrate the e ectiveness of the assignment algorithm.

Proceedings of the tenth international workshop on System level interconnect prediction - SLIP '08, 2008

Timing optimization in logic paths with wires has become an important issue in the VLSI circuit design process. Existing techniques for minimizing delay treat only the relatively rare cases of logic without wires (logical effort) or logic with a long resistive wire (repeater insertion). The techniques described in this paper address the fundamental questions of optimal sizing, the number and location of the gates. The Unified Logical Effort (ULE) method supports fast and precise optimal sizing of gates in the presence of interconnect based on intuitive closed-form expressions. The optimal number of repeaters is determined by the Gate-terminated Sized Repeater Insertion (GSRI) technique, resulting in lower delay as compared to standard repeater insertion methodologies. The Logic Gates as Repeaters (LGR) method is used for optimal wire segmenting and gate location, suggesting a distribution of logic gates over interconnect rather than using logically-redundant repeaters. The combination of these techniques provides solution for a wide variety of design issues.

ACM Transactions on Programming Languages and Systems

This article introduces a combinatorial optimization approach to register allocation and instruction scheduling, two central compiler problems. Combinatorial optimization has the potential to solve these problems optimally and to exploit processor-specific features readily. Our approach is the first to leverage this potential in practice : it captures the complete set of program transformations used in state-of-the-art compilers, scales to medium-sized functions of up to 1,000 instructions, and generates executable code. This level of practicality is reached by using constraint programming, a particularly suitable combinatorial optimization technique. Unison, the implementation of our approach, is open source, used in industry, and integrated with the LLVM toolchain. An extensive evaluation confirms that Unison generates better code than LLVM while scaling to medium-sized functions. The evaluation uses systematically selected benchmarks from MediaBench and SPEC CPU2006 and different...

2002

Abstract At the 250nm technology node, interconnect delays account for over 40% of worst delays [12]. Transition to 130nm and below increases this figure, and hence the relative importance of timing-driven placement for VLSI. Our work introduces a novel minimization of maximal path delay that improves upon previously known algorithms for timing-driven placement. Our placement algorithms have provable properties and are fast in practice.

Proceedings of the 41st annual conference on Design automation - DAC '04, 2004

We have developed a design flow from Verilog/VHDL to layout that mitigates the timing closure problem, while requiring no timing driven placement or routing tools. Timing issues are confined to the cell sizer, allowing the placement algorithm to focus solely on net lengths, resulting in superior layout densities and much lower power. The primary enablers to this new technology are: 1) gridded transistor sizing, 2) variable die routing that allows each net to be routed in the shortest possible length, 3) simultaneous cell placement, routing, gate sizing, and clock tree insertion, and 4) an effective incremental (ECO) placement that preserves net lengths from one iteration to the next. The variable die router is the key enabler. Superior placement and routing densities result from this new variable die approach. In addition, each net is routed at or near minimum length, and thus minor placement changes or cell size changes do not materially impact net lengths.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002

This paper investigates the application of simultaneous retiming and clock scheduling for optimizing synchronous circuits under setup and hold constraints. Two optimization problems are explored: (1) clock period minimization and (2) tolerance maximization to clock-signal delay variations. Exact mixed-integer linear programming formulations and efficient heuristics are given for both problems. When both long and short paths are considered, circuits optimized by the combined application of retiming and clock scheduling can achieve shorter clock periods or demonstrate greater tolerance to clock-signal delay variations than circuits optimized by retiming or clock scheduling. Experiments with benchmark circuits demonstrate the effectiveness of the combined optimization. In comparison with the best result obtained by either of the two optimizations, the joint application of retiming and clock scheduling increased operating speeds by more than 8% on the average. It also increased tolerance to clock delay variations by an average of 12% over a broad range of target clock frequencies. Larger relative improvements were achieved for shorter clock periods, thus suggesting that simultaneous retiming and clock scheduling can play an important role in high-speed design.

Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

In this paper, we propose a new timing-driven detailed placement technique for FPGAs based on optimizing critical paths. Our approach extends well beyond the previously known critical path optimization approaches and explores a significantly larger solution space. It is also complementary to single-net based timing optimization approaches. The new algorithm models the detailed placement improvement problem as a shortest path optimization problem, and optimizes the placement of all elements in the entire timing critical path simultaneously, while minimizing the costs of adjusting the placement of adjacent non-critical elements. Experimental results on industrial circuits using a modern FPGA device show an average placement clock frequency improvement of 4.5%.

1997

We study the problem of local register allocation (LRA): assign pseudo-registers to actual registersin a basic block so as to minimize the spill cost. Our version of LRA does not allow instructionscheduling, but only the insertion of spill code. We assume that the spill cost depends only on thenumber and type of load and store operations, but not on their position.Although LRA has been intensively studied, very little was known about it. LRA could besolved exactly by an algorithm that took ...

24th ACM/IEEE conference proceedings on Design automation conference - DAC '87

This paper describes the REAL REgister ALlocation program. REAL uses a track assignment algorithm taken from channel routing called the Left Edge algorithm. REAL is optimal for non-pipelined designs with no conditional branches. It is thought that REAL is also optimal for designs with conditional branches, pipelined or not. Experimental results are included in the report, which illustrate the optimal solutions found by REAL. REAL is part of the ADAM Advanced Design AutoMation system, and will be used to process designs output from MAHA and Sehwa.