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Computer Science
Software

Hardness and Algorithms for Local Register Allocation

Profile image of Ulrich KremerUlrich Kremer

1997

https://doi.org/10.7282/T3PC35XD
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19 pages

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Abstract

We study the problem of local register allocation (LRA): assign pseudo-registers to actual registersin a basic block so as to minimize the spill cost. Our version of LRA does not allow instructionscheduling, but only the insertion of spill code. We assume that the spill cost depends only on thenumber and type of load and store operations, but not on their position.Although LRA has been intensively studied, very little was known about it. LRA could besolved exactly by an algorithm that took ...

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References (20)

  1. Ravindra K. Ahuja, Thomas L. Magnanti, and James B. Orlin. Network Flows. Prentice-Hall, Englewood Cli , NJ, 1993.
  2. Alfred V. Aho, Ravi Sethi, and Je rey D. Ullman. Compilers: Principles, Techniques, and Tools. Addison-Wesley, Reading, MA, 1986.
  3. Preston Briggs, Keith D. Cooper, and Linda Torczon. Improvements to graph color- ing register allocation. ACM Transactions on Programming Languages and Systems, 16(3):428{455, May 1994.
  4. Bel66] L. A. Belady. A study of replacement algorithms for a virtual storage computer. IBM Systems Journal, 5(2):78{101, 1966.
  5. FH92] Christopher W. Fraser and David R. Hanson. Simple register spilling in a retargetable compiler. Software | Practice and Experience, 22(1):85{99, January 1992.
  6. FL88] Charles N. Fischer and Richard J. LeBlanc, Jr. Crafting a Compiler. Ben- jamin/Cummings, Menlo Park, CA, 1988.
  7. FL97] Martin Farach and Vincenzo Liberatore. On local register allocation. Technical Report TR97-33, DIMACS, 1997.
  8. Wei-Chung Hsu, Charles N. Fischer, and James R. Goodman. On the minimization of load/stores in local register allocation. IEEE Transactions on Software Engineering, 15(10):1252{1260, October 1989.
  9. Laurie J. Hendren, Guang R. Gao, Erik R. Altman, and Chandrika Mukerji. A register allocation framework based on hierarchical cyclic interval graphs. ACAPS Technical Memo 33, McGill University, February 1993.
  10. L. P. Horwitz, R. M. Karp, R. E. Miller, and S. Winograd. Index register allocation. Journal of the Association for Computing Machinery, 13(1):43{61, January 1966.
  11. HP96] John L. Hennessy and David A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann, San Mateo, CA, second edition, 1996.
  12. Ken72] Ken Kennedy. Index register allocation in straight line code and simple loops. In Randall Rustin, editor, Design and Optimization of Compilers, pages 51{63. Prentice- Hall, Englewood Cli s, NJ, 1972.
  13. Kre98] Ulrich Kremer. Optimal and near-optimal solution for hard compilation problems. Parallel Processing Letters, 1998. To appear.
  14. Edward S. Lowry and C. W. Medlock. Object code optimization. Communications of the ACM, 12(1):13{22, January 1969.
  15. F. Luccio. A comment on index register allocation. Communications of the ACM, 10(9):572{574, September 1967.
  16. Nak67] Ikuo Nakata. On compiling algorithms for arithmetic expressions. Communications of the ACM, 10(8):492{494, August 1967.
  17. NG93] Qi Ning and Guang R. Gao. A novel framework of register allocation for software pipelining. In Proceedings of the Twentieth Annual ACM SIGPLAN-SIGACT Sympo- sium on Principles of Programming Languages, pages 29{42, January 1993.
  18. Rajeev Raman. Priority queues: Small, monotone and trans-dichotomous. In Proc. ESA '96, number 1136 in Lecture Notes in Computer Science, pages 121{137, 1996.
  19. John Ruttenberg, G. R. Gao, A. Stoutchinin, and W. Lichtenstein. Software pipelin- ing showdown: Optimal vs. heuristics methods in production compilers. In Proc. SIGPLAN '96 Conf. on Programming Language Design and Implementation, pages 1{11, May 1996.
  20. SU70] Ravi Sethi and J. D. Ullman. The generation of optimal code for arithmetic expressions. Journal of the Association for Computing Machinery, 17(4):715{728, October 1970.

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