Retiming and clock scheduling for digital circuit optimization

This paper analyzes the e ect of resource sharing and assignment on the clock period of the synthesized circuit. The assignment phase assigns or binds operations of the scheduled behavioral description to a set of allocated resources. We focus on control-ow intensive descriptions, characterized by the presence of mutually exclusive paths due to the presence of nested conditional branches and loops. We show that clustering of multiple operations in the same state of the schedule, possibly leading to chaining of functional units (FUs) in the RTL circuit, is an e ective way to minimize the total number of clock cycles and hence the total execution time. We present an assignment algorithm which is particularly e ective for such design styles, by minimizing the data chaining and hence the clock period of the circuit, thereby leading to further reduction in the total execution time. Existing resource sharing and assignment approaches for reducing the clock period of the resulting circuit either increase the resource allocation or use faster modules, both leading to larger area requirements. In this paper we show that even when the type of available resource units and the number of resource units of each type is xed, di erent assignments may lead to circuits with signi cant di erences in clock period. We provide a comprehensive analysis of how resource sharing and assignment introduces long paths in the circuit. Based on the analysis, we develop an assignment algorithm which uses a high-level delay estimator to assign operations to a xed set of available resources so as to minimize the clock period of the resultant circuit, with no or minimal e ect on the area of the circuit. Experimental results on several conditional-intensive designs demonstrate the e ectiveness of the assignment algorithm.

Clock period minimization or reduction is the decrease in the time taken by critical path of the circuit. Critical path is the longest path without any delay elements in a circuit. Retiming is a technique which uses registers or delay distribution concept within the circuit without changing the basic operation of the circuit. It is of two types forward retiming and backward retiming. Retiming alters the clock period of circuit by inserting and deleting the registers. It specifies the transformation of the original circuit by adding and deleting registers into newly transformed circuit graph G (V, E, D, and W).Firstly the circuit is converted into data flow graph. DFG comprises of nodes and branches. Each node and branches represents combinational block and delay elements. Value of delay is calculated through algorithm WD. After calculating the delay values of each node, maximum value of delay and minimum value of edge weights is calculated using binary search algorithm and then Bellford-man algorithm is applied to calculate the feasible value of the clock period.

Proceedings of the 13th ACM Great Lakes Symposium on VLSI - GLSVLSI '03, 2003

We address the problem of minimizing dynamic power consumption for single-phase synchronous digital designs, under timing constraints, using an unification of basic retiming and supply voltage scaling. We assume that the number of supply voltages and their values are known for each computation element. Our main objective is then to change the location of registers using basic retiming while maximizing the number of computation elements off critical paths that can operate under a low available supply voltage, and can lead to a maximum dynamic power saving. We address the problem at the system-level. We formulate the problem as a Mixed Integer Linear Program (MILP). The exact optimal solution for the problem is then guaranteed. We also devise an algorithm to compute bounds on the values assigned by basic retiming to each computational element. Besides helping to find the optimal solution to the problem, these bounds also allow to reduce the run-time for finding this solution. The proposed approach can produce converter-free designs and can also minimize short-circuit power consumption. Experimental results have shown that dynamic power consumption can be reduced by factors that range from 2.78% to 37.24% for single-phase designs with minimal clock period. For these experimental results, the run-time for solving the MILP is under 2min.

ACM Transactions on Design Automation of Electronic Systems, 2001

In this paper, we present a method to optimize clocked circuits by relocating and changing the time of activation of registers to maximize throughput. Our method is based on software pipelining instead of retiming. The two methods have the same overall complexity but unlike previously published retiming methods, the time consuming step of searching an adequate clock period is avoided, since the optimal clock period is always a solution. The resulting circuit is a multi-phase-clocked circuit, where all the clocks have the same period. Edge-triggered flip-flops are used where the combinational delays exactly match that period, whereas level-sensitive latches are used elsewhere improving the area occupied by the circuit. Experiments on existing and newly developed benchmarks show a substantial performance improvement compared to previously published work.

International Journal of Engineering Research and, 2017

In this paper we illustrate the retiming technique to reduce the iteration period and to minimize the registers. So by this technique computation time is reduced for processors and fast speed is achieved. This is used in real time implementation to optimize performance. Shortest path algorithm such as Bellman ford and Floyd Warshall are used in retiming. These retiming techniques are explained in quantitative manner and the results are given thereafter. Retiming helps in reducing switching time. Minimization of the registers through retiming can help in reducing memory requirement and also reduce the requirement of area. And thereafter power consumption is also reduced due to less area and less switching time as given by the equation of dynamic power.

32nd Design Automation Conference, 1995

The introduction of clock s k ew at an edge-triggered ipop has an eect that is similar to the movement of the ip-op across combinational logic module boundaries, and these are continuous and discrete optimizations with the same eect. While this fact has been recognized before, this work, for the rst time, utilizes this information to nd a minimum/specied period retiming eciently. The clock period is guaranteed to be at most one gate delay larger than a tight l o w er bound on the optimal clock period; this bound is achievable using a combination of intentional skew and retiming. All ISCAS89 circuits can be retimed in a few minutes by this algorithm. 1 \astra" (): (Sanskrit) a sophisticated weapon.

Computers, IEEE Transactions on, 1990

This paper investigates the problem of improving the performance of a synchronous digital system by adjusting the path delays of the clock signal from the central clock source to individual flip-flops. Through the use of a model to detect clocking hazards, two linear programs are investigated: 1) Minimize the clock period, while avoiding clock hazards. 2) For a given period, maximize the minimum safety margin against clock hazard. These programs are solved for a simple example, and circuit simulation is used to contrast the operation of a resulting circuit with the conventionally clocked version. The method is extended to account for clock skew caused by relative variations in the drive capabilities of N-channel versus P-channel transistors in CMOS.

International Symposium on System Synthesis (IEEE Cat. No.01EX526), 2001

A method based on software pipelining has been recently proposed to optimize mono-phase clocked sequential circuits. The resulting circuits are multi-phase clocked sequential circuits, where all clocks have the same period. To preserve functionality of the original circuit, registers must be placed according to a correct schedule. This schedule also ensures the maximum throughput. In that method, it is question of (1) how to determine a schedule that requires the minimum number of registers, and (2) how to place these registers optimally. In this paper, problems and are tackled simultaneously. More precisely, we deal with the problem of determining schedules with the minimum register requirements, where the optimal register placement is done during the schedule determination. To optimally solve that problem, we provide a mixed integer linear program that we use to derive a linear program, which is polynomial-time solvable. We show that the dual of this linear program can be transformed to a minimum cost network flow problem, which can be solved more efficiently. Experimental results confirm the effectiveness of the approach, and show that significant reductions of the number of registers can be obtained. Also, they confirm that the obtained dual formulation can be solved much faster than its primal.

In this paper we have presented clock gating process for low power VLSI (very large scale integration) circuit design. Clock gating is one of the most quite often used systems in RTL to shrink dynamic power consumption without affecting the performance of the design. One process involves inserting gating requisites in the RTL, which the synthesis tool translates to clock gating cells in the clock-path of a register bank. This helps to diminish the switching activity on the clock network, thereby decreasing dynamic power consumption within the design. Due to the fact the translation accomplished via the synthesis tool is solely combinational; it is referred to as combinational clock gating. This transformation does not alter the behavior of the register being gated.

Integration, 2013

Conventional clock skew scheduling (CSS) for sequential circuits can be solved effectively using methods including the parametric shortest path algorithm and Howard's algorithm. Nevertheless, its application is practically limited due to the difficulties in reliably implementing a large set of arbitrary dedicated clock delays for flip-flops. Thus multi-domain clock skew scheduling (MDCSS) was proposed to tackle this by constraining the total number of clock delays. However, this new problem is hard to solve optimally in general. In this paper, we propose a novel method to efficiently solve it. Under mild restrictions, the problem is transformed into a special mixed integer linear programming problem, which can be solved optimally using similar techniques for the CSS problem. Then the solution quality is further improved by a critical-cycle-oriented refinement. As a result, our method obtains optimal solutions for 88 of the 93 tests on ISCAS89 benchmarks. The experimental results on large circuits in Opencores benchmarks also demonstrate its efficiency of at least one order faster than existing algorithms. To improve the runtime performance, we also devise a graph pruning algorithm that can be applied to methods for the MDCSS problem as a preprocessing step. Its application on our method shows a speedup of 2.66X on average.