Clock constraints in UML/MARTE CCSL

Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems - LCTES '09, 2009

The UML Prole for Modeling and Analysis of Real-Time and Embedded (RTE) systems has recently been adopted by the OMG. Its Time Model extends the informal and simplistic Simple Time package proposed by UML2 and oers a broad range of capabilities required to model RTE systems including both discrete/dense and chronometric/logical time. MARTE OMG specication introduces a Time Structure inspired from Time models of the concurrency theory and proposes a new clock constraint specication language (CCSL) to specify, within the context of UML, logical and chronometric time constraints. This paper introduces the formal semantics of CCSL clock constraints and proposes a process to use CCSL both as a high-level specication language for UML models and as a golden model to verify the conformance of implementations. A digital ltering video application is used as a running example to support the discussion. The application is rst formally specied with CCSL and the specication is rened based on feedback from the CCSL-dedicated simulator. In a second phase, an Esterel program of the application is considered. This program is instrumented with observers derived from the CCSL specication. Esterel Studio formal verication facilities are then used to check the conformity of the Esterel implementation with the CCSL specication. A specic library of Esterel observers has been built for this purpose.

2000

ABSTRACT: Design of real-time embedded,systems requires particular attention to the careful scheduling of application onto execution platform. Precise cycle allocation is often requested to obtain full communication,and computation throughput. Our objective is to provide a UML prole where events, actions, and objects can be annotated by ìlogicalî clocks. Initially, clocks are not necessarily related. The goal of the scheduling process

2010 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2010

The UML Profile for Modeling and Analysis of Real-Time and Embedded systems (MARTE) defines a broadly expressive Time Model to provide a generic timed interpretation for UML models. As a part of MARTE, Clock Constraint Specification Language (CCSL) allows the specification of systems with multiple clock domains as well as nondeterminism. In this paper, we propose to take advantage of Polychrony clock calculus, named hierarchization, to analyze timed systems specified in CCSL, and to generate code for simulation considering determinism. Hierarchization enables to identify the endochrony property in a system that allows code generation ensuring determinism. The presented work is being integrated into the TimeSquare environment dedicated to the simulation of MARTE timed systems.

Electronic Notes in Theoretical Computer Science, 2000

Dependability is a key feature of critical Real-Time Systems (RTS). In fact, errors may lead to disastrous consequences on life beings and economy. To ensure the absence or avoidance of such errors, it is important to focus on RTS veri�cation as early as possible. As MARTE UML pro�le is the standard de facto for modelling RTS, we suggest to ex- tend UML diagrams by a formal veri�cation stage. More precisely, in the �rst part we propose a transformation approach of Interaction Overview Diagrams and Timing Diagram merged with UML-MARTE annotations into Time Petri Nets (TPN) models Then, in the second part, we show how we can derive Timed Computational Tree Logic formulae from Ob- ject Constraint Language-Real Time (OCL-RT) constraints. This formal veri�cation is performed by the Romeo model-checker. Finally, we illus- trate our approach through a case study derived from a RT asynchronous system (Integrated Modular Avionics/based airborne system).

Science of Computer Programming, 1993

Embedding time granularity in a logical specification language for synchronous real-time systems, Science of Computer Programming 20 (1993) 141-171. Formal methods have proved to be highly beneficial in the requirements specification phase of software production and are particularly valuable in the development of real-time applications (the most critical software systems). Unfortunately, most common specification languages are inadequate for real-time applications because they lack a quantitative representation of time. In this paper, we define a logical language to specify the temporal constraints of the wide-ranging class of real-time systems whose components have dynamic behaviours regulated by very different time constants. We motivate the need for allowing the consistent treatment of different time scales in formal specifications of these systems with the purpose of enhancing the naturalness and practical usability of the notation. The logical specification language is based on a revised version of the specification language TRIO. We first present the features of the basic logical language; then, we semantically and axiomatically define its granularity extension in a topological logic framework. Finally, we show some examples of its application.

2013

High-level modeling languages and standards, such as Simulink, SysML, MARTE and AADL (Architecture Analysis & Design Language), are increasingly adopted in the design of embedded systems so that system-level analysis, verification and validation (V&V) and architecture exploration are carried out as early as possible. This paper presents our main contribution in this aim by considering embedded systems architectural modeling in AADL and functional modeling in Simulink; an original clock-based timing analysis and validation of the overall system is achieved via a formal polychronous/multi-clock model of computation. In order to avoid semantics ambiguities of AADL and Simulink, their features related to real-time and logical time properties are first studied. We then endue them with a semantics in the polychronous model of computation. We use this model of computation to jointly analyze the non-functional real-time and logical-time properties of the system (by means of logical and affine clock relations). Our approach demonstrates, through several case-studies conducted with Airbus and C-S Toulouse in the European projects CESAR and OPEES, how to cope with the system-level timing verification and validation of high-level AADL and Simulink components in the framework of Polychrony, a synchronous modeling framework dedicated to the design of safety-critical embedded systems.

Proceedings of the 2014 IEEE 15th International Conference on Information Reuse and Integration (IEEE IRI 2014), 2014

UML and MARTE are standardized modeling languages widely used in industry for the design of realtime systems. However, formal verification at early phases of the system lifecycle for UML/MARTE models remains an open issue mainly for dependability features. In this paper, we show how we can provide a formal verification of time properties from a UML/MARTE description. For this, we translate this latter description expressed (Timed Computation Tree Logic). We illustrate the proposed approach on a case study derived from a real-time asynchronous system (Integrated Modular Avionics (IMA)-based airborne system).

2009

The UML Profile for Modeling and Analysis of Real-Time and Embedded (RTE) systems has recently been adopted by the OMG. Its Time Model extends the informal and simplistic Simple Time package proposed by UML2 and offers a broad range of capabilities required to model RTE systems including both discrete/dense and chronometric/logical time. MARTE OMG specification introduces a Time Structure inspired from Time models of the concurrency theory and proposes a new clock constraint specification language (CCSL) to specify, within the context of UML, logical and chronometric time constraints. This paper introduces the formal semantics of CCSL clock constraints and proposes a process to use CCSL both as a high-level specification language for UML models and as a golden model to verify the conformance of implementations. A digital filtering video application is used as a running example to support the discussion. The application is first formally specified with CCSL and the specification is refined based on feedback from the CCSL-dedicated simulator. In a second phase, an Esterel program of the application is considered. This program is instrumented with observers derived from the CCSL specification. Esterel Studio formal verification facilities are then used to check the conformity of the Esterel implementation with the CCSL specification. A specific library of Esterel observers has been built for this purpose.

Electronic Proceedings in Theoretical Computer Science, 2010

Creol is an object-oriented modeling language in which inherently concurrent objects exchange asynchronous method calls. The operational semantics of Creol is written in an actor-based style, formulated in rewriting logic. The operational semantics yields a language interpreter in the Maude system, which can be used to analyze models. Recently, Creol has been applied to the modeling of systems with radio communication, such as sensor systems. With radio communication, messages expire and, if sent simultaneously, they may collide in the air. In order to capture these and other properties of distributed systems, we extended Creol's operational semantics with a notion of time. We exploit the framework of a language interpreter to use a lightweight notion of time, in contrast to that needed for a general purpose specification language. This paper presents a timed extension of Creol, including the semantics and the implementation strategy, and discusses its properties using an extended example. The approach can be generalized to other concurrent object or actor-based systems. * This research was done in the context of the EU project FP7-231620 HATS: Highly Adaptable and Trustworthy Software using Formal Methods (http://www.hats-project.eu).