Strained Si CMOS (SS CMOS) technology: opportunities and challenges

Solid-State Electronics, 2004

The purpose of this article is to briefly review the recent progress in terms of mobility and drive current enhancements achieved in strained-Si n-and p-metal oxide semiconductor field effect transistors (MOSFETs). Strained Si MOSFETs are potential candidates for future high performance CMOS applications, and the electron mobility enhancement factor over 3 and saturation drain current enhancement over 90% compared to bulk Si CMOS have been reported for surface channel device. The hole mobility enhancement factor over 2 has been achieved for the surface channel strained Si device while that for the buried channel compressively strained SiGe is reported to be over 5. Techniques for designing channel architectures of heterostructure CMOS (HCMOS) devices are discussed. The challenges in device design, thermal budget optimisation, SALICIDE issues and integration of different modules are addressed.

IEEE International Electron Devices Meeting 2003

We report the demonstration of a process-strained Si (PSS) CMOS technology using the concept of three-dimensional (3D) strain engineering. Methods of producing PSS include stress engineering of trench isolation, silicide, and cap layer, to improve NMOS and PMOS performance simultaneously. Each of these approaches results in a 5-10% enhancement in the ring oscillator (RO) speed. By taking advantage of preferential 3D strain engineering via one or combining more PSS techniques, CMOS performance can be further improved. PSS is a cost effective technology for meeting CMOS power-performance requirements.

IEEE Transactions on Electron Devices, 2008

A novel n-channel MOS transistor with a silicongermanium (SiGe) heterostructure embedded beneath the channel and silicon-carbon source/drain (Si:C S/D) stressors was demonstrated. The additional SiGe structure couples additional strain from the S/D stressors to the overlying Si channel, leading to enhanced strain effects in the channel region. We termed the SiGe region a strain-transfer structure due to its role in enhancing the transfer of strain from lattice-mismatched S/D stressors to the channel region. Numerical simulations were performed using the finite-element method to explain the strain-transfer mechanism. A significant drive current I Dsat improvement of 40% was achieved over the unstrained control devices, which is predominantly due to the strain-induced mobility enhancement. In addition, the impact of scaling the device design parameters on transistor drive current performance was investigated. Guidelines on further performance optimization in such a new device structure are provided.

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.

Static and dynamic power for strained-Si device is analyzed and compared with conventional bulk-Si technology. Optimum device design points are suggested with controlling physical/structural device parameters. Strained-Si CMOS circuits are studied, showing substantially-reduced power consumptions due to unique advantageous features of strained-Si device. The trade-offs for power and performance in strained-Si devices/circuits are discussed. Further, analysis and low-power design points are applied and extended to strained Si on SOI substrate (SSOI) CMOS technology.

Electronics ETF, 2014

Semiconductor industry is currently facing with thefact that conventional submicron CMOS technology isapproaching the end of their capabilities, at least when it comes toscaling the dimensions of the components. Therefore, muchattention is paid to device technology that use new technologicalstructures and new channel materials. Modern technologicalprocesses, which mainly include ultra high vacuum chemicalvapor deposition, molecular beam epitaxy and metal-organicmolecular vapor deposition, enable the obtaining of ultrathin,crystallographically almost perfect, strained layers of high purity.In this review paper we analyze the role that such layers have inmodern CMOS technologies. It’s given an overview of thecharacteristics of both strain techniques, global and local, withspecial emphasis on performance of NMOS biaxial strain andPMOS uniaxial strain. Due to the improved transport propertiesof strained layers, especially high mobility of charge carriers, theemphasis is on mechanisms to...

IEEE Transactions on Electron Devices, 2000

A novel n-channel MOS transistor with a silicongermanium (SiGe) heterostructure embedded beneath the channel and silicon-carbon source/drain (Si:C S/D) stressors was demonstrated. The additional SiGe structure couples additional strain from the S/D stressors to the overlying Si channel, leading to enhanced strain effects in the channel region. We termed the SiGe region a strain-transfer structure due to its role in enhancing the transfer of strain from lattice-mismatched S/D stressors to the channel region. Numerical simulations were performed using the finite-element method to explain the strain-transfer mechanism. A significant drive current I Dsat improvement of 40% was achieved over the unstrained control devices, which is predominantly due to the strain-induced mobility enhancement. In addition, the impact of scaling the device design parameters on transistor drive current performance was investigated. Guidelines on further performance optimization in such a new device structure are provided.

IEEE Transactions on Electron Devices, 2006

Semiconductor industry has increasingly resorted to strain as a means of realizing the required node-to-node transistor performance improvements. Straining silicon fundamentally changes the mechanical, electrical (band structure and mobility), and chemical (diffusion and activation) properties. As silicon is strained and subjected to high-temperature thermal processing, it undergoes mechanical deformations that create defects, which may significantly limit yield. Engineers have to manipulate these properties of silicon to balance the performance gains against defect generation. This paper will elucidate the current understanding and ongoing published efforts on all these critical properties in bulk strained silicon. The manifestation of these properties in CMOS transistor performance and designs that successfully harness strain is reviewed in the last section. Current manufacturable strained-silicon technologies are reviewed with particular emphasis on scalability. A detailed case study on recessed silicon germanium transistors illustrates the application of the fundamentals to optimal transistor design.

Semiconductor Science and Technology, 1998

The purpose of this review article is to report on the recent developments and the performance level achieved in the strained-Si/SiGe material system. In the first part, the technology of the growth of a high-quality strained-Si layer on a relaxed, linear or step-graded SiGe buffer layer is reviewed. Characterization results of strained-Si films obtained with secondary ion mass spectroscopy, Rutherford backscattering spectroscopy, atomic force microscopy, spectroscopic ellipsometry and Raman spectroscopy are presented. Techniques for the determination of bandgap parameters from electrical characterization of metal-oxide-semiconductor (MOS) structures on strained-Si film are discussed. In the second part, processing issues of strained-Si films in conventional Si technology with low thermal budget are critically reviewed. Thermal and low-temperature microwave plasma oxidation and nitridation of strained-Si layers are discussed. Some recent results on contact metallization of strained-Si using Ti and Pt are presented. In the last part, device applications of strained Si with special emphasis on heterostructure metal oxide semiconductor field effect transistors and modulation-doped field effect transistors are discussed. Design aspects and simulation results of n-and p-MOS devices with a strained-Si channel are presented. Possible future applications of strained-Si/SiGe in high-performance SiGe CMOS technology are indicated.

Semiconductor Science and Technology, 2004

This paper studies the effect of the strained silicon thickness on the characteristics of strained silicon MOSFETs on SiGe virtual substrates. NMOSFETs were fabricated on strained silicon substrates with various strained silicon thicknesses, both above and below the strained silicon critical thickness. The low field electron mobility and subthreshold characteristics of the devices were measured. Low field electron mobility is increased by about 1.8 times on all wafers and is not significantly degraded on any of the samples, even for a strained silicon thickness far greater than the critical thickness. From the subthreshold characteristics, however, it is shown that the off-state leakage current is greatly increased for the devices on the wafers with a strained silicon thickness that exceeds the critical thickness. The mechanism of the leakage was examined by using photon emission microscopy. Strong evidence is shown that the leakage mechanism is source/drain electrical shorting caused by enhanced dopant diffusion near misfit dislocations.

Strained silicon devices are one of the most important Technology Enhancers for further Si CMOS developments. The mobility enhancement which is obtained by applying appropriate strain provides higher charge carrier velocity in MOS channels, resulting in a higher current output under a fixed supply voltage (V) and gate oxide thickness (t ox ).The mechanism of mobility enhancement, methods of strain generation, challenges and drawbacks, improvements and key issues of strained silicon devices and their application for advanced VLSI devices is reviewed in this paper.