Peter Pirsch

Leibniz Universität Hannover, Faculty of Electrical Engineering and Computer Science, Emeritus

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VLSI Architectures for Image Communications

Integrated Circuit Design

Lecture Notes in Computer Science, 2000

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Applications Dram Frame Memory for Stand-Alone

A video coding subsystem for monolithic integration in a 0.25 pm CMOS technology has been develop... more A video coding subsystem for monolithic integration in a 0.25 pm CMOS technology has been developed. It consists of a programmable video signal processor core, up to 8 Mbit frame memory as embedded DRAM and video interfaces. The functionality of all major components has been verified by implementation on test chips in 0.5 ym CMOS technology. A system realization in 0.25 pm CMOS technology is planned. Investigations show that a die size of less than 89 mm2 for a single chip implementation can be achieved.

An FPGA architecture for velocity independent backprojection in FMCW-based SAR systems

2016 IEEE International Symposium on Signal Processing and Information Technology (ISSPIT), 2016

This paper introduces a new FPGA architecture optimized for Frequency Modulated Continuous Wave (... more This paper introduces a new FPGA architecture optimized for Frequency Modulated Continuous Wave (FMCW) Synthetic Aperture Radar (SAR). The architecture implements a Global-Backprojection-Algorithm (GBP) which has been modified to be independent of platform velocity (start-stop-approximation). The design supports parallelism of dedicated GBP processing modules in order to provide high performance. Compared to a MATLAB implementation on a single core Intel i5 at 3.2 GHz the dedicated implementation on a ML605 board provides a minimum speed-up factor of 94. The entire FPGA system was tested with real-life SAR data.

Grundschaltungen in CMOS-Technologie

Informationstechnik, 1996

Fur die Realisierung digitaler Funktionen mit Hilfe integrierter Schaltungen gibt es etliche Alte... more Fur die Realisierung digitaler Funktionen mit Hilfe integrierter Schaltungen gibt es etliche Alternativen. Diese Alternativen betreffen sowohl die Halbleitertechnologie als auch die Schaltungstechnik. Die meisten der heute gefertigten integrierten Schaltungen verwenden als Grundmaterial Silizium. Silizium ist das Basismaterial von Bipolar- als auch von Feldeffekt-Transistoren. In integrierten digitalen Schaltungen werden vor allem Feldeffekt-Transistoren mit isoliertem Gate verwendet, die im allgemeinen kurz als MOS-Transistoren bezeichnet werden. Die Bezeichnung MOS ergibt sich aus der ursprunglichen Herstellung mit den Schichten Metall fur das Gate, Siliziumdioxid fur die Gate-Isolation und Silizium fur das Substrat. Heutige MOS-Transistoren verwenden polykristallines Silizium (kurz Polysilizium) fur die Gate-Schicht. Von besonderer Bedeutung fur die Realisierung hochkomplexer anwendungsspezifischer integrierter Schaltungen (ASICs) ist die CMOS-Technologie (CMOS = Complementary MOS). Daher sollen nachfolgend exemplarisch am Beispiel der CMOS-Technologie Grundkenntnisse der digitalen Schaltungstechnik erlautert werden. Genauere Einzelheiten uber die Halbleitertechnologie, zugehorige Schaltungstechniken, Entwurfs- und Herstellungsaspekte konnen speziellen Lehrbuchern entnommen werden [13], [14], [15], [16], [17], [18], [19].

Multiprozessorsysteme

Architekturen der digitalen Signalverarbeitung, 1996

Synthetic aperture radar with fast factorized backprojection: a scalable, platform independent architecture for exhaustive FPGA resource utilization

International Conference on Radar Systems (Radar 2017), 2017

This paper introduces a Field Programmable Gate Array (FPGA) architecture for Synthetic Aperture ... more This paper introduces a Field Programmable Gate Array (FPGA) architecture for Synthetic Aperture Radar (SAR) processing. The architecture implements a Fast Factorized Backprojection (FFBP) algorithm for stripmap imagery. The designed architecture is platform independent as it only requires regular external memory, and by encapsulation the design in a superordinated system that controls board specific periphery, a switch between platforms is possible without design adjustments. The design supports scalable parallelism of dedicated processing modules in order to provide high performance and allow for exhaustive resource utilization of different FPGAs.

Video Coding and the Application Level Framing Protocol Architecture

ystems Interconnection: Basic Refer- ence Model, 1984. Interational Standard 7498. [12] Revision ... more ystems Interconnection: Basic Refer- ence Model, 1984. Interational Standard 7498. [12] Revision 8 of the JPEG technical specification. Joint Photographic Experts Group, August 1990. ISO/IEC JTC1/SC2/WG8, CCITT SGVIII. [13] S. H. Lee and L. T. Wu. Variable rate video transport in broadband packet net- works. In T. Russel Hsing, editor, Visual Communications and Image Processing &apos;88, pages 954-964, 1988. Proc. SPIE 1001. [14] Robert J. Moorhead, Joong S. Ma, and Cesar A. Gonzales. Realtime video transmission over a fast packet-switched network. In Ying wei Lin and Ram Srinivasan, editors, Digital Image Processing Applications &apos;89, pages 118-123, 1989. Proc. SPIE 1075. [15] Coding of moving pictures and associated audio (MPEG). International Orga- nization for Standardization/International Electrotechnical Institute, September 1990. ISO/IEC JTC1/SC2/WGll. 66 Bibliography

Array-Prozessorarchitekturen

Informationstechnik, 1996

Filterstrukturen

Informationstechnik, 1996

Realisierungen der diskreten Fourier-Transformation

Informationstechnik, 1996

Die diskrete Fourier-Transformation (DFT) ist Basis vieler Spektralanalyseverfahren. Die Spektral... more Die diskrete Fourier-Transformation (DFT) ist Basis vieler Spektralanalyseverfahren. Die Spektralanalyse kann beispielsweise zur Schatzung von Systemparametern und zu der Berechnung der Ubertragungsfunktion von Modellfiltern verwendet werden. Viele Anwendungen aus Gebieten wie Seismologie, Radartechnik und Sonar-technik benutzen Spektralanalyseverfahren auf der Basis der diskreten Fourier-Transformation. Eine wichtige Eigenschaft der Fourier-Transformation, das eine Faltung im Zeitbereich einer Multiplikation im Frequenzbereich entspricht, wird vielfach ausgenutzt. Insbesondere schnelle Algorithmen (FFT) unterstutzen die schnellere Durchfuhrung von Faltungen.

Guest Editors' Introduction

Schaltungsstrukturen für die Realisierung integrierter HDTV-Teilbandfilter

Continuous-Flow Matrix Transposition Using Memories

IEEE Transactions on Circuits and Systems I: Regular Papers, 2020

In this paper, we analyze how to calculate the matrix transposition in continuous flow by using a... more In this paper, we analyze how to calculate the matrix transposition in continuous flow by using a memory or group of memories. The proposed approach studies this problem for specific conditions such as square and non-square matrices, use of limited access memories and use of several memories in parallel. Contrary to previous approaches, which are based on specific cases or examples, the proposed approach derives the fundamental theory involved in the problem of matrix transposition in a continuous flow. This allows for obtaining the exact equations for the read and write addresses of the memories and other control signals in the circuits. Furthermore, the cases that involve non-square matrices, which have not been studied in detail in the literature, are analyzed in depth in this paper. Experimental results show that the proposed approach is capable of transposing matrices of 8192 x 8192 32-bit data received in series at a rate of 200 mega samples per second, which doubles the throughput of previous approaches.

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VLSI architectures and circuits for digital coding of high definition television

Von abstrakten Architekturtemplates zur hardwarenahen Architekturexploration

Standig wachsende technologische Moglichkeiten werden von immer komplexer werdenden Verfahren der... more Standig wachsende technologische Moglichkeiten werden von immer komplexer werdenden Verfahren der multimedialen Datenverarbeitung begleitet. Zusatzlich ist der Markt beherrscht von extrem kurzen Innovationszyklen der Produkte und sich standig im Fluss befindlichen Multimedia-Standards. Entsprechend sehen sich Systementwickler, die diese Verfahren effizient auf echtzeitfahigen Systemen implementieren, einer stetig wachsenden Designkomplexitat gegenuber. Um die geforderte Flexibilitat der Systeme effizient zur Verfugung stellen zu konnen, werden zunehmend programmierbare Losungen eingesetzt, die an die Anforderungen der jeweiligen Applikation angepasst werden. Entwurfsmethodiken bzw. Designflows, die sich dadurch auszeichnen, dass sie die Designkomplexitat, mit der der menschliche Designer konfrontiert ist, reduzieren, und in kurzer Zeit Design-Prototypen zur Verfugung stellen konnen, die die zukunftige System-Performance abschatzbar machen, sind daher ein zukunftsweisendes Forschungs...

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Architecture and VLSI implementation of a RISC core for a monolithic video signal processor

Proceedings of 1994 IEEE Workshop on VLSI Signal Processing

For a monolithic video signal processor a special RISC processor core has been developed. In orde... more For a monolithic video signal processor a special RISC processor core has been developed. In order to achieve an efficient implementation of hybrid video coding algorithms the applied Harvard architecture with 16 bit data path is adapted to tasks like quantization, variable length coding and run length coding. The RISC processor's die size is 68.79 mm 2 fabricated in a 0.8 μm CMOS technology. 4 kByte of program RAM and 512 Bytes of Data Memory are implemented on chip. The operating frequency is 66 MHz

VLSI architectures for MPEG

2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672)

Part Title 2 MPEG-4 V i 4 2lV.2 V i 4 v.2 ZAmd 1 Studio Frofile ... Peter Pinch, Mlden Berekovic.... more

Architecture of a coprocessor module for image compositing

1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196)

Abstract This paper proposes the architecture of a coprocesssor module for image compositing. The... more

Architecture of an image rendering co-processor for MPEG-4 systems

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors

The problem of efficient sharing of a resource is nearly ubiquitous. Except for pure public goods... more The problem of efficient sharing of a resource is nearly ubiquitous. Except for pure public goods, each agent's use creates a negative externality; often the negative externality is so strong that efficient sharing is impossible in the short run. We show that, paradoxically, the impossibility of efficient sharing in the short run enhances the possibility of efficient sharing in the long run, even if outcomes depend stochastically on actions, monitoring is limited and users are not patient. We base our analysis on the familiar framework of repeated games with imperfect public monitoring, but we extend the framework to view the monitoring structure as chosen by a designer who balances the benefits and costs of more accurate observations and reports. Our conclusions are much stronger than in the usual folk theorems: we do not require a rich signal structure or patient users and provide an explicit online construction of equilibrium strategies.

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