Chengzhi Pan

University of California, Irvine, Electrical Engineering and Computer Science, Alumnus

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Fast Parallel FFT on a Reconfigurable Computation Platform

This paper presents implementation of a very fast parallel complex FFT on M2, the second generati... more This paper presents implementation of a very fast parallel complex FFT on M2, the second generation of MorphoSys Reconfigurable computation platform, which is targeting on streamed applications such as multimedia and DSP. The proposed mapping comprises fast presorting, cascaded radix-2 stages, and post-reordering. Data and twiddle factors are 16-bit real and 16-bit imaginary in 2's complement format and scaling is performed to avoid overflow. The mapping is tested on our cycle-accurate simulator, "Mulate", and the performance is encouragingly better than other architectures such as Imagine and VIRAM. Moreover, the performance is scalable according to FFT sizes. Since there is no functionality specifically tailored to FFT, the results demonstrate the capability of MorphoSys architecture to extract parallelism from streamed applications. Further rationales are given based on the concepts of scalar operand networks and memory hierarchy.

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Design and Analysis of a Programmable Single-Chip Architecture for DVB-T BaseBand Receiver

This work treats the design and analysis of a programmable (or reconfigurable) DSP-domain-specifi... more This work treats the design and analysis of a programmable (or reconfigurable) DSP-domain-specific architecture called MorphoSys, upon which world's first single-chip software solution for DVB-T base-band receiver can be implemented. Based on the first version of MorphoSys, many modifications have been made to improve greatly both computation power and data movement efficiency. Sequential codes and SIMD codes can be parallelized; temporal granularity adjustment boosts up performance up to 4 times; numerous different types of data movement can be accelerated 8 to 64 times faster than sequential movement. As a complicated (21GOPS) and typical communication system, DVB-T base-band receiver is designed with low performance loss and mapped onto MorphoSys architecture (>28GOPS). This solidly contributes to the software defined radio development.

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Fast parallel soft Viterbi decoder mapping on a reconfigurable DSP platform

Annals of Physical and Rehabilitation Medicine, 2004

The Viterbi algorithm is used to decode convolutional codes (CC). Viterbi decoding is a computati... more The Viterbi algorithm is used to decode convolutional codes (CC). Viterbi decoding is a computation/communication intensive algorithm. Recently, with the emerging of WLAN standards delivering high rates, performance requirements of Viterbi decoders have increased dramatically. So far, such decoders have only been implemented using fixed ASIC with the datapath designed specially for the Viterbi algorithm, sacrificing flexibility. In this paper, we introduce a reconfigurable DSP platform targeting wireless communication algorithms in general with specific accelerators for the Viterbi algorithm.

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