System Level Assessment of an Optical NoC in an MPSoC Platform

2006

It is believed that the concept of integrated optical interconnect is a potential technological solution to alleviate some of the ever more pressing issues involved in exchanging data between cores in SoC architectures (inter-line crosstalk, latency, global throughput, connectivity and power consumption). This abstract summarises work carried out in the framework of the EU-funded PICMOS project on the quantitative comparison of optical interconnect to electrical interconnect in the context of on-chip data communication.

IEEE Journal of Selected Topics in Quantum Electronics, 2003

Based on a variety of optimization criteria, recent research has suggested that optical interconnects are a viable alternative to electrical interconnects for board-to-board, chip-to-chip, and on-chip applications. However, the design of modern high-performance computing systems must account for a variety of performance scaling factors that are not included in these analyses.

Multiprocessor system is growing and an attractive platform providing high performance, high energy efficiency with limited power and bandwidth. The Conventional electrical interconnects may not be fulfill the communication demand due to bandwidth density and energy consumption constraints. Optical interconnects with recent progress may be adopted due to its ultrahigh bandwidth, low latency and low energy consumption. The Optical interconnects include inter/ intra chip network, both are designed separately. Inter chip networks, exploiting the inherent properties of optical links. We place the chips far away from each other to reduce power density but still provide high performance, high energy efficiency. Inter chip network contain N data channel which are parallel to each other with the same design. Here all the core-clusters are interconnected with the parallel closed loop channel. The cluster access the channel with optical switching box. This approach utilize the advantages of optical interconnects in long distance communication. Optical interconnects dynamically partitions each data channel into multiple sections, each section improves the performance by designing the chip using optical interconnects. In this article, we propose a design to avoid the traffic and collision over network and also measure the losses of optical interconnects and save the energy upto 85% as well as improved throughput upto 90%.

2011

State-of-the-art System-on-Chip (SoC) consists of hundreds of processing elements, while trends in design of the next generation of SoC point to integration of thousand of processing elements, requiring high performance interconnect for high throughput communications. Optical on-chip interconnects are currently considered as one of the most promising paradigms for the design of such next generation Multi-Processors System on Chip (MPSoC). They enable significantly increased bandwidth, increased immunity to electromagnetic noise, decreased latency, and decreased power. Therefore, defining new architectures taking advantage of optical interconnects represents today a key issue for MPSoC designers. Moreover, new design methodologies, considering the design constraints specific to these architectures are mandatory. In this paper, we present a contention-free new architecture based on optical network on chip, called Optical Ring Network-on-Chip (ORNoC). We also show that our network scales well with both large 2D and 3D architectures. For the efficient design, we propose automatic wavelength-/waveguide assignment and demonstrate that the proposed architecture is capable of connecting 1296 nodes with only 102 waveguides and 64 wavelengths per waveguide.

4th International IEEE North-East Workshop on Circuits and Systems, NEWCAS 2006 - Conference Proceedings, 2006

The evolution of integrated circuit technology is causing system designs to move towards communication-based architectures. However, metallic interconnect networks can be very costly in terms of power and silicon area and can thus become a bottleneck in system on chip design. Integrated optical interconnect has been identified by the ITRS as a potential solution to overcome predicted interconnect limitations. This paper firstly presents the technological and device aspects of integrated optical interconnect for on-chip data transport. The second part of the paper concentrates on simulation-based quantitative comparisons of electrical to optical interconnect at the physical link level, and it is demonstrated that a ten-fold reduction in interconnect power consumption can be achieved through the use of optics. Finally some more advanced concepts are introduced in the form of optical networks on chip.

Active and Passive Optical Components for WDM Communication, 2001

Optical interconnections have become the medium of choice for the long haul communication. As the speed of the modern day computers are increasing, the speed of data transfer may reach a limit. This creates a motivation to replace electronic buses with all optical ones. Several avenues of research have emerged in optical interconnects for digital systems. In systems architecture level studies, the goal is to understand the role of the different levels of interconnection hierarchy within digital systems in the overall performance equation. Another avenue of studies identify active and passive components that will be most suitable to implement optical interconnects. These components are used to design the physical organization, the communication protocol in the existing computer architecture. Another type of studies may propose modification of the existing computer architecture, which can take advantage of the high bandwidth, multiwavelength, ultrafast optical communication and various advancement in long haul optical communication.

Anti-Counterfeiting, …, 2012

Network-on-chip (NoC) can improve the performance, power efficiency, and scalability of chip multiprocessors (CMPs). However, traditional NoCs using metallic interconnects consume a significant amount of power to deliver high communication bandwidth required in the near future. Optical NoCs are based on CMOS-compatible optical waveguides and optical routers, and promise significant bandwidth and power advantages. In this work, we review different designs of 5x5 and 4x4 optical routers for mesh or torus-based optical NoCs, and compare them for cost of optical resources and optical power loss. Besides, we use a 8x8 mesh-based optical NoC as a case study and analyze the thermal-induced power overhead while using different optical routers. Results show that the number of switching stages in an optical link directly affects the total optical power loss under thermal variations. By using passive-routing optical routers, the maximum number of switching stages in a XY-routing path is minimized to three, and the thermal-induced power overhead in the optical NoC is less than the matched networks using other routers.

IEEE Journal of Selected Topics in Quantum Electronics, 2000

Intrachip optical interconnects can outperform electrical wires but the required parameters for optical components are yet unknown. Here the ITRS is used as a reference point to derive the requirements that optical components must meet.

IEEE Micro, 2009

Optoelectronic Integration on Silicon II, 2005

As integrated circuit interconnect dimensions continue to shrink and signaling frequencies increase, interconnect performance degrades. The performance degradation is due to several factors such as power consumption, cross-talk, and signal attenuation. On-chip optical interconnects are a potential solution to these scaling issues because they offer the promise of providing higher bandwidth. In this paper, progress on the major on-chip optical