MOS Device Aging Analysis with HSPICE and CustomSim

Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 2013

Local oxide capacitance as a crucial parameter for characterization of hot-carrier degradation in long-channel n-MOSFETs J. Vac. Sci. Technol. B 31, 01A118 (2013) Mitigation of extreme ultraviolet mask defects by pattern shifting: Method and statistics J. Vac. Sci. Technol. B 30, 051605 (2012) Gallium nitride nanowire electromechanical resonators with piezoresistive readout J. Vac. Sci. Technol. B 29, 052001 (2011)

Microelectronics Reliability, 2000

Circuit aging simulation is seen as a true enhancement to device and circuit simulation. To predict aging of circuit performance, tested models for device parameters are needed in which the change in device behavior as function of time, given the biasing and temperature condition of the device in the circuit, is correctly modeled. The time scale here is the lifetime of the product. A circuit simulator in the transient mode can predict circuit aging using a transformation of the dc/ac biasing situation with an appropriate scaling mechanism. Device aging models that can be implemented in such a circuit simulator are presented here for nMOS and DMOS (double diused MOS) based on measurements and empirical modeling. Ó

Quality and Reliability Engineering International, 1995

Hot-carrier effects pose a significant reliability problem in modern MOS processes. An accurate method of predicting hot-carrier lifetimes is essential for the development of fine-geometry MOS technology. A hot-carrier degradation model developed by C. Hu et al. at the University of Berkeley is widely used to predict device lifetimes at given operating conditions from the results of accelerated tests. This paper demonstrates a new method of performing hot-carrier stress measurements which satisfies the key demand of this model. This method involves adjusting device drain voltage in order to maintain a constant ratio of substrate to drain currents. This method is employed to show that the Berkeley model makes a minimum lifetime prediction which is about an order of magnitude too short at accelerated stress conditions. This casts doubt on the suitability of the Berkeley model for use in circuit reliability simulation and for use in setting industrial reliability benchmarks. A new understanding of the importance of the gate-source voltage during hot-carrier reliability characterization using the Berkeley model is also discussed.

Journal of Applied Physics, 2018

This paper describes a new approach for modeling bias-temperature instability (BTI) in nanoscale transistors. The model uses non-iterative surface potential solvers enhanced with dynamic defect potential equations to enable accurate, physics-based circuit level simulations that incorporate BTI effects. Defect maps constructed from experimental data reported on high-k-metal-gate bulk complementary metal-oxide-semiconductor devices are used to parameterize the defect potential equation. By implementing the enhanced surface potential model in Verilog-A, both DC and AC BTI aging effects in combinational circuits are simulated and the results compared conventional threshold voltage shift methods for BTI modeling.This paper describes a new approach for modeling bias-temperature instability (BTI) in nanoscale transistors. The model uses non-iterative surface potential solvers enhanced with dynamic defect potential equations to enable accurate, physics-based circuit level simulations that i...

1988

Annual Conference of the PHM Society, 2011

An approach for predicting remaining useful life of power MOSFETs (metal oxide field effect transistor) devices has been developed. Power MOSFETs are semiconductor switching devices that are instrumental in electronics equipment such as those used in operation and control of modern aircraft and spacecraft. The MOSFETs examined here were aged under thermal overstress in a controlled experiment and continuous performance degradation data were collected from the accelerated aging experiment. Dieattach degradation was determined to be the primary failure mode. The collected run-to-failure data were analyzed and it was revealed that ON-state resistance increased as die-attach degraded under high thermal stresses. Results from finite element simulation analysis support the observations from the experimental data. Data-driven and model based prognostics algorithms were investigated where ON-state resistance was used as the primary precursor of failure feature. A Gaussian process regression algorithm was explored as an example for a data-driven technique and an extended Kalman filter and a particle filter were used as examples for model-based techniques. Both methods were able to provide valid results. Prognostic performance metrics were employed to evaluate and compare the algorithms. Celaya et al. This is an open-access article distributed under the terms of the Creative Commons Attribution 3.0 United States License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.

Microelectronics Journal, 2014

This paper presents a synthesis of leakage current effects on N-MOSFET performances, after thermal ageing in pulsed life tests. A 3000 h pulsed RF life test has been conducted on a dedicated RF S-band bench in operating modes. It is interesting to understand the degradation mechanism effects caused by the increase leakage current and in turn on drifts of critical parameters. It shows with tracking of a set of RF parameters (Pout, Gain and Drain Efficiency: DE) that only Hot Carrier Injection (HCI) phenomenon appears with incidence on RF. It is the main cause for device degradation leading to the interface state generation (traps), which results in a build up of negative charge at Si/SiO 2 interface. The physical processes responsible for the observed degradation at different stress conditions are studied by means of 2D ATLAS-SILVACO simulations to locate and confirm these phenomena.

Annual Conference of the Prognostics and Health Management Society, 2010, 2010

This paper presents research results dealing with power MOSFETs (metal oxide semiconductor field effect transistor) within the prognostics and health management of electronics. Experimental results are presented for the identification of the on-resistance as a precursor to failure of devices with die-attach degradation as a failure mechanism. Devices are aged under power cycling in order to trigger die-attach damage. In situ measurements of key electrical and thermal parameters are collected throughout the aging process and further used for analysis and computation of the on-resistance parameter. Experimental results show that the devices experience die-attach damage and that the on-resistance captures the degradation process in such a way that it could be used for the development of prognostics algorithms (data-driven or physics-based). This is an open-access article distributed under the terms of the Creative Commons Attribution 3.0 United States License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.

IEEE Journal of Solid-State Circuits, 1993

The physical models and a new integrated simulation tool are presented for estimating the hot-carrier-induced degradation of nMOS transistor characteristics and circuit performance. The proposed reliability simulation tool incorporates an accurate one-dimensional MOSFET model for representing the electrical behavior of locally damaged transistors. The hotcarrier-induced oxide damage can be specified by only a few parameters, avoiding extensive parameter extractions for the characterization of device damage. The physical degradation model used in the proposed simulation tool includes both of the fundamental device degradation mechanisms, i.e., charge trapping and interface trap generation. A repetitive simulation scheme has been adopted to ensure accurate prediction of the circuit-level degradation process under dynamic operating conditions.

CMOS ASIC lifetime and Physics-of-Faliure (PoF) modeling can be performed at mulitple levels including: System-on-Chip (SoC), Block, Circuit, Device as well as at the atomistic materials level. More computationally efficient methods at the SoC level, well as new compact PoF models at lower device levels, are needed within the device hierarchy that capture relavant reliaiblity degradation mechanisms and processes.