Papers by Sharifah Fatmadiana Wan Muhamad Hatta
Hydrothermal synthesis of zinc oxide/PEDOT:PSS composite for flexible temperature sensor application
Flexible and Printed Electronics
A flexible and printable temperature sensor was proposed for a fast detection of temperature meas... more A flexible and printable temperature sensor was proposed for a fast detection of temperature measurements. A hybrid composite of zinc oxide (ZnO) and a conductive polymer poly(3,4-ethylenedioxythiophene):poly(styrenesulfonicacid) (PEDOT:PSS) was utilized as the temperature-sensing layer. An interdigitated electrodes structure based on silver (Ag) ink was used to electrically connect the composite through a facile drop-casting technique. A standout aspect of this work is the presentation of ZnO/PEDOT:PSS as a temperature-sensing layer. The PEDOT:PSS flakes were connected by hydrothermally prepared ZnO nanorods, which increased the composite sheets’ electrical conductivity. The linearity, sensitivity, stability and dynamic response of the flexible sensor were examined from a temperature of 29 °C–60 °C. The sensor has high sensitivity of 1.06% °C−1 with response and recovery times of 5 s and 12.7 s, respectively. This work clearly demonstrates the potential of ZnO/PEDOT:PSS composite f...
Recent advances in flexible solution-processed thin-film transistors for wearable electronics
Materials Science in Semiconductor Processing
Influence of Design Considerations on Hot Carrier Injection Degradation of STI-based LDMOS Transistors
2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)
In this paper, the influence of design parameters on hot carrier injection (HCI) degradation of s... more In this paper, the influence of design parameters on hot carrier injection (HCI) degradation of shallow trench isolation (STI) based n-channel laterally diffused metal-oxide-semiconductor (n-LDMOS) transistors using TCAD simulation was analyzed. The design parameters involved in this study were STI depth, gate oxide thickness as well as p-substrate doping concentration simulated based on the stress-measure testing technique. The effect on the device parameters such as on-resistance (Ron), impact ionization rate, and interface traps concentration had been investigated and explained in detail. From the results obtained, it is found that larger STI depth and larger gate oxide thickness shows lower HCI effect. The Ron degradation is observed to reduce by 52.2% and 79.76% when the STI depth is increased to $0.3 \mu \mathrm{m}$ and $0.4 \mu \mathrm{m}$ respectively for 10ks stress time. It is also observed that higher p-substrate doping concentration exhibits higher HCI degradation.
The influence of shallow trench isolation angle on hot carrier effect of STI-based LDMOS transistors
2017 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)
Hot carrier reliability imposes challenges in the design of STI-based laterally diffused metal-ox... more Hot carrier reliability imposes challenges in the design of STI-based laterally diffused metal-oxide-semiconductor (LDMOS) devices as the device feature is miniaturized. Efforts to quantify the degradation are crucial in countering the device reliability risk. This paper investigates the effect of shallow trench isolation (STI) angle on hot carrier effect (HCI) of STI-based LDMOS devices. The effect on critical device parameters specifically the saturation drain current (Idsat), on-resistance (Ron) as well as the rate of impact ionization of the device had been studied and discussed in detail. From the result obtained, it is found that the drain current for device with 100° STI angle is reduced by 58.78% compared to device with 45° STI angle. Larger STI angle shows higher HCI degradation and the physical mechanism behind the results is analyzed from the Sentaurus 2D techplot.
Design and analysis of MEMS high sensitive capacitive pressure sensor
In this study, MEMS high sensitive capacitive pressure sensor based on poly-silicon diaphragm hav... more In this study, MEMS high sensitive capacitive pressure sensor based on poly-silicon diaphragm have been designed and analysed by using COMSOL Multiphysics Software. Three sensor designs: clamped, 8 slotted and 4 slotted with and without Teflon (polytetrafluoroethylene) coating were tested and compared to understand the sensitivity and deflection of the sensors. The pressure sensor was designed to evaluate the pressure in ranges of 0-60 mmHg which is in the range of Intraocular Pressure (IOP) for glaucoma. The capacitive pressure sensor is design using different structures of the diaphragm and it is identified that 4 slotted square diaphragms gives the highest sensitivities amongst the presented design. By coating the diaphragm and adding slots into the diaphragm, the displacement improves while mechanical and capacitance sensitivities increase
Uniformizing Routing Hotspots of Ring Oscillators on the Cyclone V FPGA for PUF Applications
2019 IEEE Regional Symposium on Micro and Nanoelectronics (RSM), 2019
Research on the possibility of using Ring Oscillator (RO) as a Physically Unclonable Function (PU... more Research on the possibility of using Ring Oscillator (RO) as a Physically Unclonable Function (PUF) has been carried out. However, until now, nothing has been realized because none of them meets the expected reliability. One of the factors that influence its reliability is the variety of routing hotspots. This paper proposes a technique for uniformizing routing hotspots in all RO locations. Ten ROs are placed close to each other, and each of them is equipped with a counter. Four variations in the arrangement of RO inside a Logic Array Blocks (LAB) are created. Then, routing hotspots in all RO locations are designed to be uniform. The uniformity process is done by rearranging the location of the logic fan-in and fan-out of the RO and counter. RO is activated vary from 0.4ms to 2ms. The number of pulses generated by ROs are recorded. Based on experiments on four Cyclone V chips, the average uniqueness was 43.79% and 46.04% for 5-stage and 11-stage RO, respectively. Reliability of 11-stage RO is higher when tested between 25°C and 40°C.
Impacts of fin width scaling on the electrical characteristics of 10-nm FinFET at different metal gate work function
2017 IEEE Regional Symposium on Micro and Nanoelectronics (RSM), 2017
This paper investigates the effects of top fin width scaling (Wtop = 4, 6, 8 nm) of p-and n-type ... more This paper investigates the effects of top fin width scaling (Wtop = 4, 6, 8 nm) of p-and n-type 10-nm FinFET on the electrical performance of the device, specifically optimized for low performance (LP) and high performance (Hp) devices. The work also studies the correlation of the metal work function to the device performance. It is observed that the transfer characteristics shown increased drain current in linear region towards increased Wtop for both p- and n-FinFET. The threshold voltage is shifted to the right for p-FinFET as the work function is increased. Oppositely for n-FinFET, they shifted to the left as the work function reduced. The Ion/Ioff ratio reduced as width increase. The observations on Ion/Ioff ratio for low performance device show the magnitude drops to 63% and 82% in n-FinFET and p-FinFET, respectively when the fin width is changed from 4 nm to 8 nm.
study on breakdown characteristics of A1GaN/GaN-based HFETs
2018 IEEE International Conference on Semiconductor Electronics (ICSE), 2018
GaN-based devices are gaining popularity due to its high electrical performance and are widely us... more GaN-based devices are gaining popularity due to its high electrical performance and are widely used in high frequency and high power microwave applications. Unfortunately, there are limitations faced by HFETs which are current leakage and breakdown characteristics which affect the performance of the device. This work focuses on the investigation of geometrical and process variation impact on the electrical characteristics and breakdown voltage of the AlGaN/GaN based High Field Effect Transistor (HFET). The Sentaurus Technology Computer Aided Design (TCAD) by Synopsys was used to facilitate this study on the electronics properties of the HFET specifically the current density in the two-dimensional electron gas (2DEG) channel, carrier mobility, band energy and transfer characteristics. It has been observed that process variations specifically substrate material selection have significant impact on the performance of the HFET as compared to geometric variation. HFETs with the Silicon Carbide substrate demonstrate higher breakdown voltage as compared to the conventional silicon substrate. Optimization of the conventional structure by means of introducing silicon carbide as the substrate demonstrates an increase of 183.33% in terms of breakdown voltage.
Design ofanRFBJT-LowNoiseAmplifier atGHz
A fully-integrated RF Low NoiseAmplifier (LNA) suitable for low-voltageapplications is proposed u... more A fully-integrated RF Low NoiseAmplifier (LNA) suitable for low-voltageapplications is proposed using bipolar junctiontransistors (BJT)cascadedstages. Theproposeddesign aims to provide gain with low biascurrent consequently lower power dissipationand lower Noise Figure (NF). The circuit isdesigned and simulated using MultiSim9 fromElectronics Workbench DesignSuite Edition 9.The proposed amplifier exhibits 3.296dB small-signal gain, reverse isolation of -6.68dB and0.359dBnoisefigure at 1GHz. produce high output impedance that achievinglargevoltage gain.is useful inThe schematic of the proposed LNA design is presented in Section II in whichthe elaborations on the LNA topology and typical trade-offs in thedesign are included. The experimental andsimulation results are presented and analysed in Section IV. Section V summarizes the maincontributions ofthis paper. Thefuture prospects ofthe design are presented in Section VI. II. CIRCUITDESIGNI. INTRODUCTION Wireless communication and its ...
ECS Journal of Solid State Science and Technology, 2018
FinFET technology has emerged as an excellent alternative to planar MOSFET for sub-nanometer scal... more FinFET technology has emerged as an excellent alternative to planar MOSFET for sub-nanometer scaled technology processes in order to achieve high performance and low power. The geometrical parameters of FinFET are particularly sensitive to the devices' figure-of-merits. In this work, the effects of critical geometrical factors of the 7 nm strained germanium FinFET were systematically investigated by studying the resulting I-V characteristics, DIBL, and subthreshold swing. Variation of structure parameters are implemented and optimized using the Taguchi method signal-to-noise ratio with orthogonal arrays of L 27 (3 13) as well as Pareto analysis of variance to obtain the best combinations of parameters for each response performance. The results reveals that the nominal threshold voltage achieved for n-FinFET and p-FinFET are 0.146V and −0.152V respectively. It was observed that design variations were shown to affect n-FinFET more compared to p-FinFET. Drive current can be increased up to approximately 22% for an optimized I on performance, while leakage can be reduced up to 10 3 in I off optimization. Moreover, it is also observed from the Pareto analysis that the performance of FinFET is mainly affected by the dominant factors of fin length, top fin width, and the interaction of both for n-and p-FinFET by more than 50% for each response.
Journal of Electronic Materials, 2017
The basic requirements on process design of extremely scaled devices involve appropriate work fun... more The basic requirements on process design of extremely scaled devices involve appropriate work function and tight doping control due to their significant effect on the threshold voltage as well as other critical electrical parameters such as drive current and leakage. This paper presents a simulation study of 22nm fin field-effect transistor (FinFET) performance based on various process design considerations including metal gate work function (WF), halo doping (N halo), source/drain doping (N sd), and substrate doping (N sub). The simulations suggest that the n-type FinFET (nFinFET) operates effectively with lower metal gate WF while the p-type FinFET (pFinFET) operates effectively with high metal gate WF in 22-nm strained technology. Further investigation shows that the leakage reduces with increasing N halo , decreasing N sd , and increasing N sub. Taguchi and Pareto analysis-of-variance approaches are applied using an L 27 orthogonal array combined with signal-to-noise ratio analysis to determine the best doping concentration combination for 22-nm FinFETs in terms of threshold voltage (V t), saturation current (I on), and off-state current (I off). Since there is a tradeoff between I on and I off , the design with the nominal-is-best V t characteristic is proposed, achieving nominal V t of 0.259 V for the nFinFET and À0.528 V for the pFinFET. Pareto analysis revealed N halo and N sub to be the dominant factor for nFinFET and pFinFET performance, respectively.
Influence of Design and Process Parameters of 32-nm Advanced-Process High-k p-MOSFETs on Negative-Bias Temperature Instability and Study of Defects
Journal of Electronic Materials, 2017
Negative-bias temperature instability (NBTI) has become a prominent factor limiting scaling of co... more Negative-bias temperature instability (NBTI) has become a prominent factor limiting scaling of complementary metal–oxide–semiconductor technology. This work presents a comprehensive simulation study on the effects of critical design parameters of 32-nm advanced-process high-kp-channel metal–oxide–semiconductor field-effect transistors on NBTI. The NBTI mechanism and defects were explored for various geometric and process design parameters over a wide range of values. The NBTI simulation method applied in this work follows the on-the-fly method to capture the mechanisms of fast and slow traps. This work illustrates the dependence of the threshold voltage (Vth) degradation on the stress oxide field and stress temperature as well as investigation of the Arrhenius plot for the devices. The temperature insensitivity during short stress time of 1 ms indicates absence of generated defects and presence of preexisting defects. It is also observed that significant defects are generated in the gate stack subsequent to NBTI. The slope obtained from the Vth degradation analysis at 1 ks and 375°C shows that changing the SiO2 interfacial layer thickness affects the Vth degradation by 96.16% more than changing the HfO2 thickness and by 80.67% more than changing the metal gate thickness. It is also found that the NBTI effect depends on process design considerations, specifically the boron concentration in the highly doped drain, the metal gate work function, and the halo doping concentration; it was observed that higher boron dose and high metal work function may lead to higher Vth degradation. However, the halo doping concentration in the advanced 32-nm structure has an insignificant effect on NBTI.
Effect of gate length on Negative Bias Temperature Instability of 32nm advanced technology HKMG PMOSFET
2016 IEEE International Conference on Semiconductor Electronics (ICSE), 2016
Negative Bias Temperature Instability (NBTI) has become a key reliability concern in semiconducto... more Negative Bias Temperature Instability (NBTI) has become a key reliability concern in semiconductor industries as devices are scaled down. A simulation study had been done on 32 nm technology node PMOS using Synopsys TCAD Sentaurus simulator tool. This paper presents the effect of gate length on NBTI of 32 nm advanced technology high-k metal gate (HKMG) PMOSFET. The effect on the device parameters such as threshold voltage (Vth), drain current (Id) and the lifetime of the device had been studied and discussed in detail. It is found that NBTI is not highly dependent on gate length at low oxide field (Eox) while at higher Eox, longer gate length is shown to significantly affect the Vth degradation where Vth degradation in longer gate length is found to be lowered by 23.39% compared to the shorter.
Comparison of DC and pulse train analysis on submicrometer pMOSFETs lifetime prediction using on-the-fly method
2015 IEEE Regional Symposium on Micro and Nanoelectronics (RSM), 2015
Lifetime of pMOSFETs is limited by negative bias temperature instability (NBTI). NBTI causes the ... more Lifetime of pMOSFETs is limited by negative bias temperature instability (NBTI). NBTI causes the degradation of drive current and threshold voltage of p-MOSFETs. This paper presents the comparison of DC and pulse train analysis on sub micrometer pMOSFETs lifetime prediction using on-the-fly (OTF) method. The SiO2 conventional PMOS transistor having effective oxide thickness (EOT) between 1.8nm and 2.8nm were simulated by applying various simulation conditions. The lifetime prediction was studied by varying the stress voltage and size of EOT for pMOSFETs. Results of this simulation demonstrate the impact of EOT variability on operational voltage, Vgop and interface trap vs stress time for both DC and pulse train analysis.
A study of the states kinetics in NBTI degradation by two-stage NBTI model implementation
2015 IEEE Regional Symposium on Micro and Nanoelectronics (RSM), 2015
This paper presents a simulation framework for reliability analysis of PMOS devices in the TCAD S... more This paper presents a simulation framework for reliability analysis of PMOS devices in the TCAD Sentaurus environment. The degradation of parameter is based on the numerical solution for the two-stage NBTI model mechanism. We demonstrate and analyze the voltage degradation, Vth of a high-k HfO2 dielectric pMOSFET structure with effective oxide thickness (EOT) of 1.092 nm. After 1000s of stress, the threshold voltage shift of higher stress bias shows higher degradation (~0.07V) compared to the lower stress bias (~0.008V).
IOP Conference Series: Materials Science and Engineering, 2015
A study of the NBTI reliability of high-k p-MOSFET device for application in subthreshold operati... more A study of the NBTI reliability of high-k p-MOSFET device for application in subthreshold operation based on different defect mechanism is presented. The impact of the different defect mechanism is studied based on modelling the sub-threshold operation using Two-Stage NBTI model and NBTI-induced positive charges based on energy profiling approach. The time exponent of 0.1 is observed in sub-threshold operation modelled based on the Two-Stage NBTI model while time exponent of 0.3 is observed in sub-threshold operation modelled based energy profiling approach. Considerable threshold voltage shifts are observed during sub-threshold operation based on both defect mechanisms. Extraction of E'centres and E'/Pb H Complex as well as positive charges was found to be temperature dependence hence the degradation is also thermally activated during subthreshold operation for both defect mechanisms.
Nanomaterials
Perovskite solar cells (PSCs) have already achieved efficiencies of over 25%; however, their inst... more Perovskite solar cells (PSCs) have already achieved efficiencies of over 25%; however, their instability and degradation in the operational environment have prevented them from becoming commercially viable. Understanding the degradation mechanism, as well as improving the fabrication technique for achieving high-quality perovskite films, is crucial to overcoming these shortcomings. In this study, we investigated details in the changes of physical properties associated with the degradation and/or decomposition of perovskite films and solar cells using XRD, FESEM, EDX, UV-Vis, Hall-effect, and current-voltage (I-V) measurement techniques. The dissociation, as well as the intensity of perovskite peaks, have been observed as an impact of film degradation by humidity. The decomposition rate of perovskite film has been estimated from the structural and optical changes. The performance degradation of novel planner structure PSCs has been investigated in detail. The PSCs were fabricated in-...
Chinese Journal of Physics, 2020
This is a PDF file of an article that has undergone enhancements after acceptance, such as the ad... more This is a PDF file of an article that has undergone enhancements after acceptance, such as the addition of a cover page and metadata, and formatting for readability, but it is not yet the definitive version of record. This version will undergo additional copyediting, typesetting and review before it is published in its final form, but we are providing this version to give early visibility of the article. Please note that, during the production process, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
Gate-all-around nanowire field-effect transistor (GAA NWFET) is a viable alternative to reduce sh... more Gate-all-around nanowire field-effect transistor (GAA NWFET) is a viable alternative to reduce short channel effects. A 3D model of the GAA NWFET was explored by studying the effect of process parameters such as nanowire materials, gate oxide materials and high-κ coverage angles on vital transistor performance metrices specifically threshold voltage, leakage current, current ratio, subthreshold swing (SS) and drain induce barrier lowering (DIBL). It has been observed that the nanowire material of InP provides the lowest threshold voltage and highest drive current. Gate oxide material of HfO2 showed improved leakage current by 88.39%, current ratio by 1439.63%, SS by 24.16% and DIBL by 13.11% relative to the conventional NWFET with SiO2 gate oxide. Moreover, as the high-κ dielectric (HfO2) covers the gate oxide over the channel region, the gate electrostatic control over the channel region increases, thus reducing SS to an ideal value. An exhaustive Taguchi Method with Conceptual Sig...
Modelling of Thin-film Transistor for Glucose Sensing Application
2022 IEEE International Conference on Semiconductor Electronics (ICSE)
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Papers by Sharifah Fatmadiana Wan Muhamad Hatta