Hot-carrier reliability lifetimes as predicted by Berkeley's model

2005

In this paper the degradation in the drain current and threshold voltage of the P-MOS transistors are observed by operating the device under voltage stress conditions. Using the observartion results the effect of hot-carriers was investigated statistically and a new statistical method for modeling was proposed to be an alternative to those given in the literature. The linear regression method is used to estimate the Power, Weibull and Logarithmic parameters and the correlation coefficient is used to confirm the results. The observed and the estimated values of the degradation are compared with each other.

IEEE Journal of Solid-State Circuits, 1994

Long-term ring-oscillator hot-carrier degradation data and simulation results are compared to demonstrate that a circuit reliability simulator BERT can predict CMOS digital circuit speed degradation from transistor dc stress data. We present generalized hot-carrier-reliability design rules that translate device-level degradation rate to CMOS circuit lifetime. The design rules, which consist of lifetime and speed degradation factors, can roughly predict CMOS circuit degradation during the initial design, and can help reliability engineers to quickly estimate the overall product hot-carrier reliability. The NMOSFET and PMOSFET lifetime factors were found to obey 4/ f trise and lo/ f t~l respectively. Typically, the NMOSFET and PMOSFET speed degradation factors are 1/4 and 1/2, respectively, with saturation region drain current as the monitor, while for a 100 MHz operating frequency and for an input rise time of 0.35 ns, the NMOSFET and PMOSFET time factors are 120 and 300, respectively.

Proceedings of International Reliability Physics Symposium RELPHY-96, 1996

The hot-carrier degradation of n-channel MOSFETs has been studied under three dominant degradation modes. The time dependence of device parameter shift under single-bias DC stressing experiments has been modeled using conventional techniques. However, these models result in incorrect prediction of the device behavior when all the three degradation modes are activated in a single device in different sequences. A novel approach to model the device degradation has been presented to account for the coupling between the degradation modes. The new coupled model predicts the time dependence of the device degradation much more accurately than the popular conventional models and is particularly suitable for use in circuit reliability simulators.

IEEE Transactions on Electron Devices, 1988

A consistent model for the degradation of n-channel and p-channel transistors under hot-carrier injection conditions is presented. This model is derived using the charge-pumping technique for the evaluation of the interface characteristics, in combination with the behavior of the drain and the substrate currents after degradation. It is demonstrated that for n-channel transistors the degradation is mainly caused by the generation of interface traps. Only in the region of hole injection ( Vg = V , ) the degradation is dominated by the trapped holes, which mask the effect of the generated interface traps. It is found that the degradation of p-channel transistors, although completely different at first sight, occurs by the same mechanisms. For this case, the degradation is caused by trapped negative charge, which masks the influence of the interface traps. The latter are nevertheless generated in comparable amounts as in n-channel transistors. Based on these insights, improved procedures for accelerated lifetime experiments are proposed for both channel types. Finally, the peculiar degradation behavior of n-channel transistors under alternating injection conditions is discussed and fully explained based on the static stress degradation model.

IEEE Electron Device Letters, 2000

Active threshold voltage V TH control via wellsubstrate biasing can be utilized to satisfy International Roadmap for Semiconductors performance and standby power requirements for CMOS technology beyond the hp65-nm node. In this letter, the impact of substrate bias V SUB on hot-carrier reliability is presented. The impact varies with the gate length and body effect factor. These findings are explained, and the effects of future scaling are discussed using a quasi-two-dimensional model. Significant and important improvement in hot-carrier lifetime with forward-bias V SUB can be expected for deeply scaled CMOS devices, making it an attractive method for extending the scalability of bulk-Si transistor technology.

2019 IEEE International Integrated Reliability Workshop (IIRW)

We investigate correlation between linear drain currents (I d,lin) in unstressed n-channel FinFETs and relative I d,lin changes (∆I d,lin) during hot-carrier degradation (HCD). For this analysis we simulate 200 different realizations of a FinFET where each of these devices has its own unique distribution of random dopants. Our study shows that devices with superior performance (with higher time-zero I d,lin values) degrade faster than initially "worse" transistors (with lower initial I d,lin currents) and, correspondingly, device lifetime also decreases with the time-zero I d,lin .

Microelectronics Journal, 2009

An analytical CMOS transistor ageing model is presented and a new procedure that allows the extraction of its parameters are presented in this paper. Then, we show how this model can be used to forecast and understand the drifts of the main characteristics of a CMOS circuit. Further, we demonstrate that this model can also be used to help the analog designer to choose and/or modify a circuit in order to minimise the hot-carrier induced degradations. Finally, we use an ageing simulation tool realised in VHDL-AMS to validate the analytical study, and we present our first experimental results.

Microelectronics Reliability, 1999

A uni®ed model for hot-carrier-induced degradation in LDD n-MOSFETs is presented. A novel oxide spacer charge pumping method enables interface trap generation in the spacer and overlap/channel regions to be distinctly separated. An excellent correlation between trap generation in the spacer region and linear drain current degradation at high gate voltage is observed. Moreover, trap generation in the overlap/channel region is found to correlate well with linear drain current degradation at low gate voltage. The results point unambiguously to a twomechanism degradation model involving drain resistance increase by trap generation in the spacer region, and carrier mobility reduction by trap generation in the overlap/channel region. The combined eect of a timeindependent lateral electron temperature pro®le and a ®nite density of interface trap precursors within the LDD region leads to a self-limiting degradation behavior. This insight forms the basis of a time-dependent trap generation model, which indicates the existence of a single degradation curve. The fact that the degradation curves at dierent stress drain voltages fall onto a time-scaled version of the single degradation curve provides strong support for the model. This also oers a straightforward and yet accurate means by which the hot-carrier lifetime corresponding to a speci®c failure criterion may be extracted. Finally, a power-law relationship between hot-carrier lifetime and substrate current is also observed for the LDD devices, thus preserving the physical essence based on which earlier lifetime models for conventional drain devices are established.

Microelectronics Reliability, 1996

The role of hot-carrier-induced interface states in NMOSFETs is discussed. A new model is proposed based on measurements in several 0.7/~m CMOS technologies of different suppliers. Our model for the first time enables accurate interface state prediction over many orders of magnitude in time for all stress conditions under pinch-off and incorporates saturation. It can easily be implemented in a reliability circuit simulator, enabling more accurate NMOSFET parameter degradation calculations (e.g. AIo, Agm etc.).

Microelectronics Reliability, 1998

In this paper, we consider the reliability of n-channel MOSFETs using the Substrate Hot Electron (SHE) technique. We confirm that there is a dependence of oxide degradation upon the current density during SHE injection (as previously observed by ourselves and others). In order to explain this effect, the detrapping of previously trapped electrons must be taken into account A new theoretical model is presented which accounts for the main features of the phenomenon. We consider the technologically important low field case (< 2MVcm "~) for a range current densities (from 0.05 to 2 macro 2 ) and injected charge densities up to 10 C/cm 2. The device lifetime for these different conditions is calculated and shown to be also a function of the current density. It is clear that in order to calculate the lifetime during normal operation from accelerated testing, the precise hot electron injection current density must be known, furthermore it must be demonsWated that the same degradation mechanisms hold at very high fields and/or current densities. This result has profound implications for device reliability predictions made using accelerated hot electron measurements and calls into question lifetime predictions made where the effect is not taken into account.