Hardware Prototyping of Arm Based System on Chip

2004

2006 43rd ACM/IEEE Design Automation Conference, 2006

Traditionally, design space exploration for Systems-on-Chip (SoCs) has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, a shift from computationbound to communication-bound design becomes mandatory. Towards this end, this paper presents a comprehensive evaluation of two communication architectures targeting multimedia applications. Specifically, we compare and contrast the Network-on-Chip (NoC) and Point-to-Point (P2P) communication architectures in terms of power, performance, and area. As the main contribution, we present complete P2P and NoC-based implementations of a real multimedia application (MPEG-2 encoder), and provide direct measurements using a FPGA prototype and actual video clips, rather than simulation and synthetic workload. From an experimental standpoint, we show that the NoC architecture scales very well in terms of area, performance, power and design effort, while the P2P architecture scales poorly on all accounts except performance.

IEEE Distributed Systems Online, 2007

A new multiprocessor system-on-chip prototyping flow based on the Portable Operating System Interface (Posix) standard and a multiprocessor hardware platform lets you quickly prototype Posixbased applications. Modern MPSoCs (multiprocessor systems on chip) contain a huge amount of software and rely on complex hardware components. As application complexity grows, programmable multiprocessor platforms are becoming more desirable. In fact, chips with several processors (such as general purpose processors and digital signal processors) are emerging in the industry, either for low-end applications such as audio codec or high-end applications such as video encoders. Reconfigurable hardware platforms recently emerged as effective solutions to validate and prototype MPSoC designs early in a design flow. Such prototyping platforms make simultaneous hardware and software development possible and enable early software design and debugging, 1-3 thus allowing for early software and hardware integration-which is the critical step in MPSoC system designs. Applications running on these new multiprocessor platforms usually require sophisticated multitasking operating systems to execute the system parts mapped to software. These operating systems provide a suitable abstraction, allowing easy development of application software. 4 Using a standard API at this level makes this process even more effective and enhances software portability and reuse across different operating systems. However, the same portability doesn't apply from a hardware perspective, where changes to the underlying configurable hardware architecture are still seen as a major source of "nonportability" and usually lead to long, tedious redesign cycles.

International Journal of Embedded Systems, 2005

System-on-chip (SoC) is developing as a new paradigm in electronic system design. This allows an entire hardware/software system to be built on a single chip, using predesigned components. This paper examines the achievements and future of novel approach and flow for an efficient design of application-specific multiprocessor system-on-chip (called GAM-SoC). The approach is based on a generic architecture model which is used as a template throughout the design process. The key characteristics of this model are its great modularity, flexibility and scalability which make it reusable for a large class of applications. In the flow, architectural parameters are first extracted from a high-level system specification and then used to instantiate architectural components, such as processors, memory modules, IP-hardware blocks, and on-chip communication networks. The flow includes the generation of hardware/software wrappers that adapts the processor to the onchip communication network in an application-specific way. The feasibility and effectiveness of this approach are illustrated by significant demonstration examples. Index Terms-Component-based design, generic architecture model, systematic design methodology, on-chip communication wrappers, AHB-AMBA, multiprocessor SoC. I. INTRODUCTION o accommodate the ever increasing performance requirements of application domains such as xDSL technology, networking, wireless, game applications, multiprocessor SoCs are more and more required [34]. Often, the multiprocessor SoC architectures require for applicationspecific optimization heterogeneous processors (DSP, CPUs), signal processing hardware, hardware controllers, DRAMs, Flash Memories, high-performance on-chip communication interfaces, and sophisticated communication protocols [11].

10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007), 2007

This paper describes a case study in a new rapid prototyping-based design framework for exploring and validating complex multiprocessor architectures for multimedia applications. The goal of the presented methodology is to speed up and improve the verification flow of a multiprocessor system that will finally be implemented as an ASIC. The case study consists of a 64-bit compatible AMBA AHB system bus which connects up to 14 32-Bit RISC processors to a host interface. A typical parallel computing application has been implemented for the parameterized multiprocessor system. The employed FPGA emulation environment increases by up to 200 the simulation frequency of the global system on a workstation (2.2 GHz AMD Dual Opteron with 8 GB RAM). Moreover a standalone emulation can be performed at the maximum achievable frequency (65 MHz). Track Area 3-System, hardware and embedded software specification, modeling and validation.