Leandro Moller

Processadores Reconfiguráveis: Estado da Arte

Evaluation of adaptive management techniques in NoC-Based MPSoCs

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012), 2012

A Generic FPGA Emulation Framework MORAES, Fernando Gehm ; MOREIRA, Matheus ; LUCAS, Carlo ; CORR... more A Generic FPGA Emulation Framework MORAES, Fernando Gehm ; MOREIRA, Matheus ; LUCAS, Carlo ; CORREA, Dairan ; CARDOSO, Douglas ; MAGNAGUAGNO, Maurício ; CASTILHOS, Guilherme ; CALAZANS, Ney In: ICECS, 2012, p. 233-236. ... Proposal and Evaluation of a Task Migration Protocol for NoC-based MPSoCs MORAES, Fernando Gehm ; MADALOZZO, Guilherme ; CASTILHOS, Guilherme ; CARARA, Everton Alceu In: ISCAS, 2012, p. 644-647. ... MAZENOC: Novel Approach for Fault-Tolerant NoC Routing ...

Validation of executable application models mapped onto network-on-chip platforms

... Jari Nurmi ∗ , Manfred Glesner and Fernando Moraes ∗ Department of Computer Systems Tampe... more

Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms

The design space of multiprocessor systems based on Network-on-Chip (NoC) interconnects is very l... more The design space of multiprocessor systems based on Network-on-Chip (NoC) interconnects is very large. Considering the intercon-nect structure alone, designers must choose or parameterise a large number of components according to application-specific constraints, such as buffering and flow control mechanism, network topology, word width, packet structure, or routing algorithm.

Download

Graphical interface for debugging RTL Networks-on-Chip

One problem of Multiprocessor Systems-on-Chip (MPSoCs) based on Networks-on-Chip (NoCs) is tracin... more One problem of Multiprocessor Systems-on-Chip (MPSoCs) based on Networks-on-Chip (NoCs) is tracing the dozens of parallel communications that are transferred in the system. The goals of tracing communications are usually either debugging or monitoring the NoC for design space exploration. On Register Transfer Level (RTL) NoCs the tracing is frequently verified by waveforms, which provides limited useful information about the global status of the NoC. The goal of this work is to improve the tracing capabilities of RTL NoCs and provide a global picture of what is happening in the NoC. This is accomplished by using a Java tool to represent graphically relevant events of the NoC. The input of this tool is a list of relevant events generated by the RTL simulator during the simulation of an MPSoC. The HERMES NoC is used as test case for the tool.

Download

Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip Interconnects

Abstract This paper presents an approach supporting designer-driven interactive design space expl... more

A simplified executable model to evaluate latency and throughput of networks-on-chip

This paper proposes a technique that mixes simulation and an analytical method to evaluate the ch... more This paper proposes a technique that mixes simulation and an analytical method to evaluate the characteristics of Networks-on-Chips (NoCs). The advantage of this technique is to reduce the simulation time by reducing the complexity of the NoC model while still obtaining accurate results for latency and throughput. The basis of this technique is: (i) to send the whole payload data at once in the packet header; (ii) to reduce the NoC simulation complexity by omitting the flit by flit payload forwarding; (iii) to use an algorithm for controlling the release of the packet trailer in order to close the connection at the right time. For the evaluation of this technique, an actor-oriented model of a NoC, JOSELITO, was created. Simulation results show that JOSELITO is in average 2.3 times faster in 88% of the executed case studies than the implementation without using the proposed technique. The worst case simulation results for latency and throughput have, respectively, 5.26% and 0.1% error compared to the corresponding Register Transfer Level (RTL) model.

Download

A case study of hierarchically heterogeneous application modelling using UML and ptolemy II

2010 International Symposium on System-on-Chip Proceedings, SoC 2010, 2010

The heterogeneity of the state-of-the art embedded systems containing multicore platforms require... more The heterogeneity of the state-of-the art embedded systems containing multicore platforms requires the application design flow to enable the creation of parallel applications using multiple Models of Computation. Components of such systems may interact in various ways, often using ad hoc methods. However, due to the poor reusability and analysability of ad hoc solutions, more structured approaches to heterogeneous modelling are needed. This paper takes advantage of the hierarchically heterogeneous modelling style of the Ptolemy II framework and presents a case study of building and simulating an autonomous vehicle application model using various Models of Computation.

Download

MultiNoC: A Multiprocessing System Enabled by a Network on Chip

Design, Automation and Test in Europe, 2005

The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an ... more The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed interconnection structure is a Network on Chip, or NoC. NoCs are emerging as a viable alternative to increasing demands on interconnection architectures, due to the following characteristics: (i) energy efficiency and reliability; (ii) scalability of bandwidth, when compared to traditional bus architectures; (iii) reusability; (iv) distributed routing decisions. An external host computer feeds MultiNoC with application instructions and data. After this initialization procedure, MultiNoC executes some algorithm. After finishing execution of the algorithm, output data can be read back by the host. Sequential or parallel algorithms conveniently adapted to the MultiNoC structure can be executed. The main motivation to propose this design is to enable the investigation of current trends to increase the number of embedded processors in SoCs, leading to the concept of "sea of processors" systems.

Download

A NoC-Based Infrastructure to Enable Dynamic Self Reconfigurable Systems

Innovations for Computational Processing and Communication, 2010

Platform-based designed SoC includes one or more processors, RTOS, intellectual property blocks, ... more Platform-based designed SoC includes one or more processors, RTOS, intellectual property blocks, memories and an interconnection infrastructure. An associated advantage of processor is flexibility at the software level. Hardware is not flexible. Thus, dedicated IP blocks must be inserted at design time. An alternative is to provide the platform with reconfigurable hardware blocks with sufficient capacity to implement any envisaged dedicated IP block. Dynamic self-reconfigurable systems (DSRSs) introduce flexibility to ...

Dynamic and Partial Reconfiguration in FPGA SoCs: Requirements Tools and a Case Study

New Algorithms, Architectures and Applications for Reconfigurable Computing, 2005

Current technology allows building integrated circuits (ICs) complex enough to contain all major ... more Current technology allows building integrated circuits (ICs) complex enough to contain all major elements of a complete end product, which are accordingly called Systems-on-Chip (SoCs)[1]. A SoC usually contains one or more programmable processors, on-chip memory, peripheral devices, and specifically designed complex hardware modules. SoCs are most often implemented as a collection of reusable components named intellectual property cores (IP cores or cores). An IP core is a complex hardware module, created for reuse and that ...

Infrastructure for dynamic reconfigurable systems

Proceedings of the 19th annual symposium on Integrated circuits and systems design - SBCCI '06, 2006

Platform-based design is a method to implement complex SoCs, avoiding chip design from scratch. A... more Platform-based design is a method to implement complex SoCs, avoiding chip design from scratch. A promising evolution of platform-based design are MPSoC. Such generic architectures might furnish enough performance for several classes of embedded systems. An associated advantage of these architectures is flexibility at the software level. In principle, hardware is not flexible. Thus, dedicated IP blocks must be inserted before chip design, or enough area can be reserved for them when using reconfigurable blocks. Dynamic self-reconfigurable systems (DSRSs) introduce flexibility to hardware. In DSRSs, IP blocks are loaded according to application demand, reducing area, power consumption and system cost. An MPSoC based platform, associated with dynamic reconfiguration, provides both hardware and software flexibility. This paper has two main goals. First, to present the necessary infrastructure for DSRSs, identifying which components are required in these systems, such as a configuration controller, configuration ports and reconfigurable IP interfaces. The second objective is to discuss practical implementations choices and area-performance tradeoffs. The paper employs case studies to access the advantages and problems related to different implementations for the communication infrastructure (bus and NoC), the configuration controller (hardware and software) and IP interfaces (LUT and tristate based).

Download

Seismic surveys in the Northern Red Sea: asymmetric crustal structure

Tectonophysics, 1991

ABSTRACT

Download

Crustal and upper mantle structure in the Ryukyu Island Arc deduced from deep seismic sounding

Geophysical Journal International, 1990

Crustal and upper mantle structure in the Ryukyu Island Arc ... T. Iwasaki,'" N. Hirata... more

ANoC-based Infrastructure to Enable Dynamic Self Reconfigurable Systems

ABSTRACT Platform-based designed SoC includes one or more processors, RTOS, intellectual property... more

Communication Infrastructure Modeling of Many-Core Architectures

Sistemas Dinamicamente Reconfiguráveis com Comunicação via Redes Intrachip

... Figura 22 Diagrama de blocos de uma célula do XC6200 e respectiva unidade funcional ... 80 ... more

Arquitetura Multiprocessada em SoCs: Estudo de Diferentes Topologias de Conexão

Towards a unique FPGA-based identification circuit using process variations

A compact chip identification (ID) circuit with improved reliability is presented. Ring oscillato... more A compact chip identification (ID) circuit with improved reliability is presented. Ring oscillators are used to measure the spatial process variation and the ID is based on their relative speeds. A novel averaging and postprocessing scheme is employed to accurately determine the faster of two similar-frequency ring oscillators in the presence of noise. Using this scheme, the average number of unstable bits i.e. bits which can change in value between readings, measured on an FPGA is shown to be reduced from 5.3% to 0.9% at 20 • C. Within the range 20 − 60 • C, the percentage of unstable bits is within 2.8%. An analysis of the effectiveness of the scheme and the distribution of the errors is given over different temperature ranges and FPGA chips.

Download

Reconfiguração Parcial e Remota de Cores FPGAs

VII IBERCHIP Workshop. Montevideo, Uruguai. Março, Mar 1, 2001

In application areas such as multimedia, telecommunications and embedded systems in general, high... more In application areas such as multimedia, telecommunications and embedded systems in general, high performance is an essential issue. The strategy of using a conventional microprocessor executing the tasks of such systems in software usually may not correspond to the performance expectations or requirements. Combining conventional microprocessors with (re) configurable hardware devices such as RAM-based FPGAs it is possible to obtain an economically interesting product and yet efficient for a more vast ...

Download

Uploads

Papers by Leandro Moller

Log In